KR20000043904A - Method for forming contact hole of semiconductor device - Google Patents
Method for forming contact hole of semiconductor device Download PDFInfo
- Publication number
- KR20000043904A KR20000043904A KR1019980060342A KR19980060342A KR20000043904A KR 20000043904 A KR20000043904 A KR 20000043904A KR 1019980060342 A KR1019980060342 A KR 1019980060342A KR 19980060342 A KR19980060342 A KR 19980060342A KR 20000043904 A KR20000043904 A KR 20000043904A
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist pattern
- oxide film
- contact hole
- film
- low temperature
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 8
- 238000007517 polishing process Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 2
- 229920000642 polymer Polymers 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- -1 spacer nitride Chemical class 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 자기정렬콘택(SAC) 공정시 콘택홀이 형성될 부분에 포토레지스트 패턴으로 덮은 다음 이후의 공정에서 이를 제거하므로써, 액티브 영역의 감소 없이 미세한 콘택홀을 재현성 있게 형성할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor device, and in particular, by covering a portion where a contact hole is to be formed in a self-aligned contact (SAC) process during a semiconductor device manufacturing process with a photoresist pattern and then removing it in a subsequent process, The present invention relates to a method for forming a contact hole in a semiconductor device capable of reproducibly forming minute contact holes without reducing the active area.
일반적으로, 반도체 소자가 고집적화 되어감에 따라 콘택홀의 크기는 줄어들고 상대적으로 그 깊이는 깊어져 애스팩트 비(aspect ratio)가 증가된다. 애스팩트 비의 증가는 도전층의 매립을 어렵게 하여 결국 콘택 저항의 증가를 초래한다. 애스팩트 비를 감소시키고 매립 특성을 좋게 하기 위한 방안으로 콘택홀을 와인 글라스(wine glass) 모양으로 형성하기도 한다. 그러나, 반도체 소자가 256M 급 이상으로 고집적화 되어 감에 따라 포토리소그라피(photolithography) 공정에서 노광 장비의 해상력의 한계로 인하여 양호한 형상을 갖는 콘택홀을 형성하기가 어려워지고 있어, 현재에는 256M 급 이상의 소자에서 자기정렬콘택(SAC) 공정이 널리 적용되고 있다. 자기정렬콘택 공정은 질화막 또는 옥시나이트라이드(oxynitride)막을 식각 정지층으로 사용하는데, 산화막 식각 시에 질화막 또는 옥시나이트라이드막에 대한 고선택비를 얻기 위해 다량의 폴리머를 사용하기 때문에 액티브 영역의 감소 및 재현성 있는 결과를 얻기 어려운 문제가 있다.In general, as semiconductor devices become highly integrated, the size of the contact hole is reduced and its depth is relatively deep, thereby increasing the aspect ratio. Increasing the aspect ratio makes it difficult to bury the conductive layer, resulting in an increase in contact resistance. In order to reduce the aspect ratio and improve the landfill characteristics, the contact hole may be formed in the shape of a wine glass. However, as semiconductor devices are highly integrated to 256M or higher, it is difficult to form contact holes having a good shape due to the limitation of the resolution of the exposure equipment in the photolithography process. Self-aligned contact (SAC) process is widely applied. The self-aligned contact process uses a nitride film or an oxynitride film as an etch stop layer, which reduces the active area because a large amount of polymer is used to obtain a high selectivity for the nitride film or the oxynitride film during oxide etching. And problems that are difficult to obtain reproducible results.
따라서, 본 발명은 반도체 소자의 제조 공정중 자기정렬콘택 공정시 액티브 영역의 감소 없이 미세한 콘택홀을 재현성 있게 형성할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of reproducibly forming minute contact holes without reducing an active area during a self-aligned contact process during a semiconductor device manufacturing process.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택홀 형성 방법은 질화막으로 둘러싸인 워드 라인이 다수 형성된 반도체 기판이 제공되는 단계: 상기 다수의 워드 라인을 포함한 반도체 기판에서 콘택홀이 형성될 지역에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 포함한 전체 구조상에 산화막을 형성하는 단계; 상기 산화막과 포토레지스트 패턴을 화학기계적 연마 공정으로 연마하여 평탄화 시키는 단계; 및 상기 포토레지스트 패턴을 제거하여 콘택홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method including: providing a semiconductor substrate having a plurality of word lines surrounded by a nitride film: a photo in a region where contact holes are to be formed in the semiconductor substrate including the plurality of word lines Forming a resist pattern; Forming an oxide film on the entire structure including the photoresist pattern; Planarizing the oxide film and the photoresist pattern by a chemical mechanical polishing process; And forming a contact hole by removing the photoresist pattern.
도 1a 내지 도 1f는 본 발명의 실시예에 따라 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 워드 라인11: semiconductor substrate 12: word line
13: 마스크 질화막 14: 스페이서 질화막13: mask nitride film 14: spacer nitride film
15: 포토레지스트 패턴 16: 산화막15: photoresist pattern 16: oxide film
16A: 배선간 절연막 17: 콘택홀16A: insulating film between wirings 17: contact hole
18: 콘택 플러그18: contact plug
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시예에 따라 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 상부에 마스크 질화막(13)이 존재하고, 측부에 스페이서 질화막(14)이 존재하는 워드 라인(12)이 다수 형성된 반도체 기판(11)이 제공된다.Referring to FIG. 1A, a semiconductor substrate 11 having a plurality of word lines 12 including a mask nitride film 13 and a spacer nitride film 14 on a side thereof is provided.
도 1b를 참조하면, 다수의 워드 라인(12)을 포함한 반도체 기판(11) 상에 포토리소그라피 공정으로 비트 라인용 및 캐패시터의 하부 전극용 콘택홀 또는 기타 콘택홀이 형성될 지역을 덮는 포토레지스트 패턴(15)을 형성한다.Referring to FIG. 1B, a photoresist pattern covering a region where a contact hole or other contact hole for a bit line and a lower electrode of a capacitor is to be formed by a photolithography process on a semiconductor substrate 11 including a plurality of word lines 12. (15) is formed.
이러한 포토레지스트 패턴(15)은 반도체 기판(11) 전체에 콘택홀이 형성될 부분마다 고립 패턴(island pattern) 형태로 다수개 형성된다.The photoresist pattern 15 is formed in plural in an island pattern for each portion of the semiconductor substrate 11 where contact holes are to be formed.
도 1c를 참조하면, 포토레지스트 패턴(15)을 포함한 전체 구조상에 저온에서 증착 가능한 산화막(16)을 충분히 증착 한다.Referring to FIG. 1C, an oxide film 16 that can be deposited at low temperature is sufficiently deposited on the entire structure including the photoresist pattern 15.
상기에서, 산화막(16)은 하부층인 포토레지스트 패턴(15)이 열 손상을 입지 않도록 하기 위해 저온에서 증착이 이루지는 저온 산화막(LTO) 또는 희생 산화막(low temperature TEOS)을 주로 사용하며, 저온 산화막 대신에 옥시나이트라이드막(oxy-nitride film), 실리콘-리치 산화막(Si-rich oxide film), 플라즈마 증가형 화학기상증착막(PE-CVD film)을 사용할 수 있다.In the above, the oxide film 16 mainly uses a low temperature oxide film (LTO) or a low temperature TEOS, which is deposited at a low temperature, in order to prevent thermal damage of the photoresist pattern 15, which is a lower layer, and a low temperature oxide film. Instead, an oxynitride film, a silicon-rich oxide film, or a plasma enhanced chemical vapor deposition film (PE-CVD film) may be used.
도 1d를 참조하면, 화학기계적 연마(CMP) 공정으로 산화막(16) 및 포토레지스트 패턴(15)을 일정 두께 연마하여 표면 평탄화를 이루게 한다.Referring to FIG. 1D, the oxide film 16 and the photoresist pattern 15 are polished to a predetermined thickness by a chemical mechanical polishing (CMP) process to achieve surface planarization.
도 1e를 참조하면, 산화막(16)에 높은 선택비를 갖는 스트립(strip) 공정으로 포토레지스트 패턴(15)을 제거하고, 이로 인하여 남아있는 산화막(16) 및 질화막(13 및 14)에 의해 정의되는 콘택홀(17)이 형성된다. 산화막(16)은 상기의 공정중 포토레지스트 패턴(15)의 열 손상을 방지하기 위해 저온에서 증착 하여 그 막질이 미세 배선간 절연막으로 사용하기에 부적합하여 소자의 오동작을 유발시킬 수 있기 때문에 고온에서 막질을 조밀화시켜 미세 배선간 절연막(16A)으로 사용한다.Referring to FIG. 1E, the photoresist pattern 15 is removed by a strip process having a high selectivity to the oxide film 16, and is defined by the remaining oxide film 16 and the nitride films 13 and 14. The contact hole 17 is formed. The oxide film 16 is deposited at a low temperature in order to prevent thermal damage of the photoresist pattern 15 during the above process, and the film quality thereof is not suitable for use as an insulating film between fine wirings, which may cause malfunction of the device. The film quality is densified and used as the fine inter-wire insulating film 16A.
이후, 도 1f에 도시된 바와 같이, 콘택홀(17)을 포함한 전체 구조상에 플러그용 도전물을 증착한 후, 마스크 질화막(13)을 연마 정지층으로한 화학기계적 연마 공정으로 배선간 절연막(16A) 및 플러그용 도전물을 연마하여 콘택홀(17) 내부에 콘택 플러그(18)를 형성한다.Thereafter, as shown in FIG. 1F, after the plug conductive material is deposited on the entire structure including the contact hole 17, the inter-wire insulating film 16A is subjected to a chemical mechanical polishing process using the mask nitride film 13 as a polishing stop layer. And the conductive material for the plug are polished to form the contact plug 18 in the contact hole 17.
한편, 전술한 바와 같이 미세 배선간 절연막(16A)은 저온에서 증착한 산화막(16)을 고온 처리하여 형성하거나, 아니면 콘택 플러그(18)를 형성한 후 산화막(16)을 습식 식각으로 제거하고, 고온 산화막 즉 미세 배선간 절연막으로 사용될 수 있는 산화막을 증착한 후, 마스크 질화막(13)을 연마 정지층으로한 화학기계적 연마 공정으로 고온 산화막 연마하여 형성할 수 있다.On the other hand, as described above, the fine inter-wire insulating film 16A is formed by high temperature treatment of the oxide film 16 deposited at a low temperature, or after the contact plug 18 is formed, the oxide film 16 is removed by wet etching. After depositing a high temperature oxide film, that is, an oxide film that can be used as a fine inter-wire insulating film, the mask nitride film 13 may be formed by polishing the high temperature oxide film by a chemical mechanical polishing process using the polishing stop layer.
상기한 본 발명의 실시예는 자기정렬콘택 공정시 콘택홀이 형성될 부분에 먼저 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 포함한 나머지 부분에 저온 산화막을 증착하고, 저온 산화막 및 포토레지스트 패턴을 화학기계적 연마 공정으로 연마하여 평탄화 시킨 후, 포토레지스트 패턴을 제거하여 미세 콘택홀을 형성하는 기술이다. 이러한 본 발명의 원리는 상기한 비트 라인용 및 캐패시터의 하부 전극용 콘택홀뿐만 아니라 반도체 소자의 제조 공정중 모든 콘택홀 형성 공정에 적용할 수 있다.In the above-described embodiment of the present invention, a photoresist pattern is first formed in a portion where a contact hole is to be formed during a self-aligned contact process, a low temperature oxide film is deposited on the remaining portions including the photoresist pattern, and the low temperature oxide film and the photoresist pattern are chemically After polishing and planarizing by a mechanical polishing process, a photoresist pattern is removed to form a fine contact hole. The principle of the present invention can be applied to all the contact hole forming processes in the manufacturing process of the semiconductor device as well as the contact hole for the bit line and the lower electrode of the capacitor.
상술한 바와 같이, 본 발명은 포토레지스트 패턴을 이용하여 미세한 콘택홀을 용이하게 형성할 수 있어 소자 제조공정시 256M 급 이상의 콘택홀 형성에 적용 가능하여 소자의 고집적화를 실현시킬 수 있고, 건식 식각 선택비를 이용하는 기존 자기정렬콘택 공정에 비해 공정 마진(process margin)이 확보되고 재현성 있는 결과를 얻을 수 있다.As described above, the present invention can easily form a fine contact hole using a photoresist pattern can be applied to the formation of a contact hole of 256M or more during the device manufacturing process to realize high integration of the device, dry etching selection Compared with the existing self-aligned contact process using the ratio, the process margin is secured and reproducible results can be obtained.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060342A KR20000043904A (en) | 1998-12-29 | 1998-12-29 | Method for forming contact hole of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060342A KR20000043904A (en) | 1998-12-29 | 1998-12-29 | Method for forming contact hole of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000043904A true KR20000043904A (en) | 2000-07-15 |
Family
ID=19567160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980060342A KR20000043904A (en) | 1998-12-29 | 1998-12-29 | Method for forming contact hole of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000043904A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030003906A (en) * | 2001-07-04 | 2003-01-14 | 삼성전자 주식회사 | Method of forming contact of semiconductor device and semiconductor memory device fabricated by the same method |
| KR100431086B1 (en) * | 2002-07-11 | 2004-05-12 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100444546B1 (en) * | 2000-11-20 | 2004-08-16 | 토쿄오오카코교 가부시기가이샤 | Method for forming a hole-patterned photoresist layer |
| KR100782485B1 (en) * | 2006-08-18 | 2007-12-05 | 삼성전자주식회사 | Structures electrically connecting aluminum and copper lines and methods of forming the same |
-
1998
- 1998-12-29 KR KR1019980060342A patent/KR20000043904A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444546B1 (en) * | 2000-11-20 | 2004-08-16 | 토쿄오오카코교 가부시기가이샤 | Method for forming a hole-patterned photoresist layer |
| KR20030003906A (en) * | 2001-07-04 | 2003-01-14 | 삼성전자 주식회사 | Method of forming contact of semiconductor device and semiconductor memory device fabricated by the same method |
| KR100431086B1 (en) * | 2002-07-11 | 2004-05-12 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100782485B1 (en) * | 2006-08-18 | 2007-12-05 | 삼성전자주식회사 | Structures electrically connecting aluminum and copper lines and methods of forming the same |
| US8211793B2 (en) | 2006-08-18 | 2012-07-03 | Samsung Electronics Co., Ltd. | Structures electrically connecting aluminum and copper interconnections and methods of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20030013761A (en) | Structure of Trench Isolation and Method of Forming The Same | |
| JPH01290236A (en) | Method of levelling wide trench | |
| US6033962A (en) | Method of fabricating sidewall spacers for a self-aligned contact hole | |
| US6566236B1 (en) | Gate structures with increased etch margin for self-aligned contact and the method of forming the same | |
| KR20000043904A (en) | Method for forming contact hole of semiconductor device | |
| KR100315034B1 (en) | Manufacturing method of semiconductor device | |
| KR20020057789A (en) | Method of producing a semiconductor device | |
| KR100275136B1 (en) | Method for forming polysilicon plug-pad in semiconductor device | |
| KR100301148B1 (en) | Forming method for hard mask of semiconductor device | |
| US6303484B1 (en) | Method of manufacturing dummy pattern | |
| KR100367695B1 (en) | Method for forming via contact in semiconductor device | |
| KR100585084B1 (en) | Self-align contact etch method of semiconductor device | |
| KR100304946B1 (en) | Method for manufacturing semiconductor device | |
| KR20030075745A (en) | Method of Forming Metal Gate in Semiconductor Device | |
| KR100226767B1 (en) | Method of manufacturing semiconductor device | |
| KR100772077B1 (en) | A method for forming contact hole of semiconductor device | |
| KR100346843B1 (en) | Method of forming interlayer dielectric film and method of manufacturing semiconductor device | |
| US6207581B1 (en) | Method of fabricating node contact hole | |
| KR20080029565A (en) | Method for forming contact plug in semiconductor device | |
| KR100439477B1 (en) | Fabricating method of Tungsten plug in semiconductor device | |
| KR100785862B1 (en) | Method for forming gate electrode and sidewall spacer using damascene | |
| KR20010058980A (en) | Method for manufacturing capacitor in semiconductor device | |
| KR100871370B1 (en) | Method for forming metal line of semiconductor device | |
| KR20040060197A (en) | Method for manufacturing dual damascene contact hole of the semiconductor device | |
| JP2001332621A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |