KR100304946B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100304946B1 KR100304946B1 KR1019940016480A KR19940016480A KR100304946B1 KR 100304946 B1 KR100304946 B1 KR 100304946B1 KR 1019940016480 A KR1019940016480 A KR 1019940016480A KR 19940016480 A KR19940016480 A KR 19940016480A KR 100304946 B1 KR100304946 B1 KR 100304946B1
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- conductive layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
Abstract
Description
제1도는 종래의 반도체장치의 제조방법을 도시한 공정순서도.1 is a process flowchart showing a conventional method for manufacturing a semiconductor device.
제2도는 본 발명의 반도체장치의 제조방법을 도시한 공정순서도.2 is a process flowchart showing a method of manufacturing a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film
3 : 게이트절연막 4 : 게이트전극3: gate insulating film 4: gate electrode
5 : 평탄화층 6 : 비트라인5: planarization layer 6: bit line
7 : 산화막 8 : 스토리지노드콘택7: oxide film 8: storage node contact
9 : 제1도전층 15 : 유전체막9: first conductive layer 15: dielectric film
16 : 커패시터 플레이트전극 17 : 평탄화층16 capacitor plate electrode 17 planarization layer
18,22 : 포토레지스트 19 : 더미층18,22 photoresist 19 dummy layer
20 : 제2도전층 측벽20: second conductive layer sidewall
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 반도체 메모리장치의 커패시터 형성 및 주변회로(periphery circuit)와 셀어레이(cell array)간의 광범위한 평탄화공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a capacitor forming and a planarization process between a peripheral circuit and a cell array in a semiconductor memory device.
종래의 3차원 구조의 커패시터를 갖춘 반도체 메모리장치의 제조방법을 제1도를 참조하여 설명하면 다음과 같다.A conventional method of manufacturing a semiconductor memory device having a capacitor having a three-dimensional structure will be described with reference to FIG. 1.
먼저, 제1(a)도와 같이 실리콘기판(1)위에 필드산화막(2)을 형성하여 소자분리공정을 행한 후, 통상의 트랜지스터 제조공정을 통해 게이트절연막(3), 게이트전극(4), 소오스 및 드레인영역(도시하지 않음)을 형성하여 셀트랜지스터를 형성한다. 이어서 기판 전면에 절연층(5)을 형성한 후, 이위에 비트라인(6)을 형성하고 전면에 산화막(7A), 질화막(7B), 산화막(7C)을 차례로 형성한 다음 사진식각공정을 통해 상기 산화막(7C), 질화막(7B), 산화막(7A)을, 절연층(5)을 선택적으로 식각하여 스토리지노드 콘택(8A)을 형성한 후, 다시 질화막(8B)을 증착하고 에치백하여 상기 스토리지노드 콘택(8A) 측면이 질화막측벽(8B)를 형성한다.First, as shown in FIG. 1 (a), the field oxide film 2 is formed on the silicon substrate 1, and the device isolation process is performed. Then, the gate insulating film 3, the gate electrode 4, and the source are processed through a conventional transistor manufacturing process. And a drain region (not shown) to form a cell transistor. Subsequently, after the insulating layer 5 is formed on the entire surface of the substrate, a bit line 6 is formed thereon, and an oxide film 7A, a nitride film 7B, and an oxide film 7C are sequentially formed on the entire surface, and then a photolithography process is performed. The oxide film 7C, the nitride film 7B, and the oxide film 7A are selectively etched to form the storage node contact 8A by selectively etching the insulating layer 5, and then the nitride film 8B is deposited and etched back. The side of the storage node contact 8A forms the nitride film side wall 8B.
이어서 제1(b)도와 같이 기판 전면에 폴리실리콘(9)을 증착하고 이위에 산화막(10)을 형성한 후, 산화막(10)위에 사진식각공정시 난반사를 방지하기 위해 HSG(Hemispherical grain)폴리실리콘(11)을 증착한다.Subsequently, polysilicon 9 is deposited on the entire surface of the substrate as shown in FIG. 1 (b), and an oxide film 10 is formed thereon, and then HSG (Hemispherical grain) poly to prevent diffuse reflection during the photolithography process on the oxide film 10. Silicon 11 is deposited.
다음에 제1(c)도와 같이 포토레지스트(도시하지 않음)를 이용한 사진식각공정을 통해 상기 산화막(10)을 스토리지노드패턴으로 패터닝하고 이 산화막패턴을 이용하여 그 하부의 폴리실리콘층(9)을 식각하여 스토리지노드패턴 구조물을 형성한 다음, 상기 HSG폴리실리콘을 제거한다. 이어서 폴리실리콘을 증착하고 에치백하여 상기 스토리지노드패턴 구조물의 측면에 폴리실리콘측벽(13)을 형성한다. 이때, 주변회로부(B영역)는 스토리지노드패턴 형성을 위한 포토레지스트패턴이 형성되지 않으므로 산화막(10)과 폴리실리콘층(9)이 제거되고 폴리실리콘측벽(13)형성을 위한 폴리실리콘층도 제거되어 셀어레이영역(A영영)과 주변회로(B영역)의 단차가 더욱 심화된다.Next, as shown in FIG. 1C, the oxide layer 10 is patterned into a storage node pattern through a photolithography process using a photoresist (not shown), and the polysilicon layer 9 below the oxide layer pattern is formed using the oxide layer pattern. After etching to form a storage node pattern structure, the HSG polysilicon is removed. Next, polysilicon is deposited and etched back to form a polysilicon sidewall 13 on the side of the storage node pattern structure. In this case, since the photoresist pattern for forming the storage node pattern is not formed in the peripheral circuit part (B region), the oxide layer 10 and the polysilicon layer 9 are removed, and the polysilicon layer for forming the polysilicon side wall 13 is also removed. As a result, the step between the cell array area A and the peripheral circuit area B is further deepened.
이어서 제1(d)도에 도시된 바와 같이 주변회로부(B영역)상에만 마스킹층으로서 포토레지스트(14)를 도포한 후, 습식식각을 통해 산화막(7C)과 산화막(10)을 제거하여 폴리실리콘층(9)과 폴리실리콘측벽(13)으로 이루어진 스토리지노드를 형성한다.Subsequently, as shown in FIG. 1 (d), the photoresist 14 is applied as a masking layer only on the peripheral circuit portion (region B), and then the oxide film 7C and the oxide film 10 are removed by wet etching. A storage node consisting of a silicon layer 9 and a polysilicon sidewall 13 is formed.
다음에 제1(e)도에 도시된 바와 같이 상기 주변회로부상의 포토레지스트를 제거한 후, 상기 스토리지노드(9,13) 전면에 유전체막(15)을 형성하고, 유전체막(15) 전면에 폴리실리콘을 증착하고 패터닝하여 플레이트전극(16)을 형성한 다음 기판 전면에 산화막(17)을 형성함으로써 반도체 메모리장치를 완성한다.Next, as shown in FIG. 1 (e), after removing the photoresist on the peripheral circuit portion, a dielectric film 15 is formed on the entire storage node 9 and 13 and a dielectric film 15 is formed on the entire surface of the dielectric film 15. The semiconductor memory device is completed by depositing and patterning polysilicon to form a plate electrode 16 and then forming an oxide film 17 on the entire surface of the substrate.
상술한 종래기술에 있어서는 커패시터 스토리지노드패턴 구조물을 형성하기 위해 식각저지층으로서 질화막(7B), 산화막(7C) 및 질화막(8B)등의 증착공정이 필요하게 되고, HSG폴리실리콘을 제거하기 위한 식각공정이 추가되는등 공정이 복잡해지며, 제조공정중 셀어레이영역에만 산화막(10)이 남게 되어 셀어레이영역과 주변회로부의 단차가 심화된다. 이러한 셀어레이영역과 주변회로부와의 단차로 인해 금속배선 공정이 일반조명으로는 하프마이크론의 사진식각공정이 불가능하게 되므로 MLR(Multi-Layer Resist), 딥 UV(Deep Ultra-violet), PSM(Phase Shift Mask)등과 같은 변형된 사진공정 및 다단계 식각공정이 요구되어 전체공정이 매우 복잡해지는 문제가 있다.In the above-described prior art, in order to form a capacitor storage node pattern structure, a deposition process such as a nitride film 7B, an oxide film 7C, and a nitride film 8B is required as an etch stop layer, and an etching process for removing HSG polysilicon is performed. The process is complicated, such as the addition of a process, and the oxide film 10 remains only in the cell array region during the manufacturing process, thereby increasing the step difference between the cell array region and the peripheral circuit portion. Due to the difference between the cell array area and the peripheral circuit part, the metallization process cannot use the half-micron photo etching process under general lighting, so MLR (Multi-Layer Resist), Deep Ultra-violet (PSM) and PSM (Phase) There is a problem that the entire process is very complicated because a modified photo process and a multi-step etching process such as a shift mask) are required.
본 발명은 상술한 문제를 해결하기 위한 것으로, 단순한 공정에 의해 3차원 구조의 커패시터를 갖춘 반도체 메모리장치를 제조함과 아울러 셀어레이영역과 주변회로영역간의 광범위한 평탄화를 이룰 수 있는 방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and to provide a method for manufacturing a semiconductor memory device having a three-dimensional capacitor by a simple process and attaining a wide planarization between the cell array region and the peripheral circuit region. For that purpose.
상기 목적을 달성하기 위한 본 발명의 반도체장치 제조방법은 셀어레이영역과 주변회로영역으로 이루어진 반도체기판상에 트랜지스터를 형성하는 공정과, 상기 기판상에 평탄화층을 형성하여 기판 표면을 평탄화시키는 공정, 상기 평탄화된 기판상에 습식식각액에 대해 표면부위의 식각속도가 다른 부분에 비해 느린 산화막을 형성하는 공정, 상기 상기 평탄화층 및 산화막을 선택적으로 식각하여 스토리지노드 콘택을 형성하는 공정, 기판 전면에 제1도전층을 형성하는 공정, 상기 제1도전층을 커패시터 스토리지노드 패턴으로 패터닝하는 공정, 기판 전면에 더미층을 형성하는 공정, 상기 더미층을 선택적으로 식각하여 상기 제1도전층으로 된 스토리지노드 패턴이 형성되어 있지 않은 부분상에만 더미층패턴을 형성하는 공정, 상기 더미층패턴의 측면에 제2도전층 측벽을 형성하여 상기 제1도전층으로 된 스토리지노드 패턴과 제2도전층 측벽으로 이루어진 스토리지노드를 형성하는 공정, 주변회로영역상부에만 선택적으로 마스킹층을 형성하는 공정, 습식식각을 행하여 셀어레이영역의 상기 더미층패턴 및 상기 산화막의 표면부위를 제거하는 공정, 상기 주변회로영역상의 마스킹층을 제거하는 공정, 상기 스토리지노드의 전표면에 유전체막을 형성하는 공정, 상기 유전체막 전면에 커패시터 플레이트전극을 형성하는 공정으로 이루어진다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a transistor on a semiconductor substrate consisting of a cell array region and a peripheral circuit region, a step of forming a planarization layer on the substrate to planarize the surface of the substrate, Forming a slow oxide film on the planarized substrate as compared to a portion where the etch rate of the surface portion is different from that of the wet etching solution; and selectively etching the planarization layer and the oxide film to form a storage node contact; A process of forming a first conductive layer, patterning the first conductive layer in a capacitor storage node pattern, forming a dummy layer on the entire surface of the substrate, selectively etching the dummy layer to form a storage node as the first conductive layer. Forming a dummy layer pattern only on a portion where a pattern is not formed, the side of the dummy layer pattern Forming a sidewall of the second conductive layer on the surface to form a storage node comprising the first conductive layer and a sidewall of the second conductive layer; selectively forming a masking layer only on the peripheral circuit region; Etching to remove the dummy layer pattern and the surface portion of the oxide film in the cell array region, removing the masking layer on the peripheral circuit region, forming a dielectric film on the entire surface of the storage node, the dielectric film The capacitor plate electrode is formed on the front surface.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 반도체장치 제조방법을 공정순서에 따라 도시하였다.2 shows a method of manufacturing a semiconductor device according to the present invention in accordance with the process sequence.
먼저, 제2(a)도에 도시된 바와 같이 실리콘기판(1)위에 필드산화막(2)을 형성하여 소자분리공정을 행한 후, 통상의 트랜지스터 제조공정을 통해 게이트절연막(3), 게이트전극(4), 소오스 및 드레인영역(도시하지 않음)을 형성하여 셀트랜지스터를 형성한다. 이어서 평탄화층으로서, 예컨대 산화막(5)을 증착하여 1차평탄화를 시키면 셀어레이영역(A)과 주변회로부(B)는 게이트전극(4)의 조밀도차이에 의해 단차가 발생하게 된다. 다음에 상기 산화막(5)상에 비트라인(6)을 형성하고, 그 전면에 다시 절연막으로서, 예컨대 산화막(7)을 형성한다. 이때, 산화막(7)은 증착시 보론(Bron), 인(Phosphorus)등의 불순물농도를 조절하여 후속공정에서 HF 또는 HF+NHF3등의 식각액을 이용하여 습식식각을 행할 때 식각속도가 5-10배정도 느리게 되도록 한다.First, as shown in FIG. 2 (a), the field oxide film 2 is formed on the silicon substrate 1 to perform a device isolation process, and then the gate insulating film 3 and the gate electrode 4), source and drain regions (not shown) are formed to form a cell transistor. Subsequently, when the planarization layer, for example, the oxide film 5 is deposited and subjected to the first planarization, the step difference occurs between the cell array region A and the peripheral circuit portion B due to the density difference between the gate electrodes 4. Next, the bit line 6 is formed on the oxide film 5, and the oxide film 7 is formed again as an insulating film on the entire surface thereof. At this time, the oxide film 7 controls the concentration of impurities such as boron, phosphorus, etc. during deposition, and the etching rate is 5- when wet etching is performed using an etchant such as HF or HF + NHF 3 in a subsequent process. Try to be 10 times slower.
다음에 제2(b)도에 도시된 바와 같이 상기 산화막(5,7)을 선택적으로 식각하여 커패시터 스토리지노드와 실리콘기판을 연결하기 위한 스토리지노드 콘택(8)을 형성한 후, 스토리지노드 형성용 제1도전층(9)으로서, 도우프드(doped) 폴리실리콘을 증착한다. 이때, 스토리지노드를 사진식각공정으로 패터닝, 형성할 때 난반사를 방지하여 사진식각공정을 용이하게 하기 위해 HSG(Hemispherical Grain)폴리실리콘을 100-300Å정도 증착한 후, 이위에 도우프드 폴리실리콘(9)을 증착하기도 한다. 이어서 상기 폴리실리콘층(9)상에 포토레지스트(18)를 도포한 후, 선택적으로 노광 및 현상하여 스토리지노드패턴(18)을 형성한 다음, 이 스토리지노드패턴(18)을 마스크로 하여 상기 폴리실리콘층(9)을 식각한다.Next, as shown in FIG. 2 (b), the oxide layers 5 and 7 are selectively etched to form storage node contacts 8 for connecting the capacitor storage node and the silicon substrate. As the first conductive layer 9, doped polysilicon is deposited. At this time, in order to prevent the diffuse reflection and to facilitate the photolithography process when patterning and forming the storage node by the photolithography process, after depositing about 100-300Å HSG (Hemispherical Grain) polysilicon, the doped polysilicon (9 ) May be deposited. Subsequently, the photoresist 18 is coated on the polysilicon layer 9, and then selectively exposed and developed to form a storage node pattern 18, and then the polysilicon layer 18 is used as a mask. The silicon layer 9 is etched.
이어서 제2(c)도에 도시된 바와 같이 스토리지노드패턴(18)을 제거한 후, 더미층(Dummy lqyer)(19)으로서, 산화막을 형성한 후, 사진식각공정을 통해 상기 더미산화막(19)을 선택적으로 식각하여 상기 제1도전층인 폴리실리콘층(9)이 남아 있지 않음 부분상에만 남기고 제1도전층(9)의 표면을 노출시킨 다음, 결과물 전면에 제2도전층으로서, 폴리실리콘을 증착하고 이방성식각하여 상기 산화막(19)의 측면에 폴리실리콘측벽(20)을 형성함으로써 제1도전층인 폴리실리콘(9)과 상기 폴리실리콘측벽(20)으로 이루어진 스토리지노드를 형성한다. 이어서 포토레지스트(22)를 도포한 후, 이를 선택적으로 노광 및 현상하여 주변회로부(B영역)상에만 남긴다.Subsequently, as shown in FIG. 2C, after the storage node pattern 18 is removed, an oxide film is formed as a dummy layer 19 and the dummy oxide film 19 is formed by a photolithography process. Is selectively etched to expose the surface of the first conductive layer 9 without leaving the polysilicon layer 9, which is the first conductive layer, only on a portion thereof, and then, as the second conductive layer on the entire surface of the resultant, polysilicon By depositing and anisotropically etching to form a polysilicon side wall 20 on the side of the oxide film 19 to form a storage node consisting of the first conductive layer polysilicon 9 and the polysilicon side wall 20. Then, after the photoresist 22 is applied, it is selectively exposed and developed to remain only on the peripheral circuit portion (B area).
다음에 제2(d)도에 도시된 바와 같이 상기 주변회로부상의 포토레지스트(22)를 마스크로 하여 HF 또는 HF+NHF3등을 이용한 습식식각을 행하게 되면 셀어레이영역의 상기 더미산화막(19) 및 상기 산화막(7)의 표면부위가 제거된다. 이는 상기 산화막(7)의 표면부위에 앞서 보론, 인등의 불순물을 농도를 조절하여 산화막(7)을 증착시켰기 때문에 산화막(12)의 습식식각시 산화막(7) 표면부위의 식각속도가 느려지게 되어 표면부위만이 제거되는 것이다. 이때, 상기 산화막(7)은 500-1000Å정도가 남도록 두께를 설정하여 형성한다. 다음에 상기 포토레지스트(22)를 제거해낸다. 이때, 주변회로부상의 상기 더미산화막(19)은 습식식각시 상기 포토레지스트(22)에 의해 보호되므로 습식식각공정에 끝난후에는 주변회로부(B)와 셀어레이영역(A)의 단차는 더미산화막(19)의 두께만큼 개선되게 된다. 이어서 상기 노출된 스토리지노드(9,20)의 전표면에 유전체막(15)을 형성하고, 유전체막(15) 전면에 제3도전층으로서, 폴리실리콘을 증착하고 패터닝하여 커패시터 플레이트전극(16)을 형성한다.Next, as shown in FIG. 2 (d), when wet etching using HF or HF + NHF 3 is performed using the photoresist 22 on the peripheral circuit portion as a mask, the dummy oxide layer 19 in the cell array region 19 is formed. ) And the surface portion of the oxide film 7 are removed. Since the oxide film 7 is deposited by adjusting the concentration of impurities such as boron and phosphorus before the surface portion of the oxide film 7, the etching rate of the surface portion of the oxide film 7 is decreased during the wet etching of the oxide film 12. Only the surface area is removed. At this time, the oxide film 7 is formed by setting the thickness so as to remain about 500-1000Å. Next, the photoresist 22 is removed. At this time, since the dummy oxide film 19 on the peripheral circuit portion is protected by the photoresist 22 during the wet etching, the step between the peripheral circuit portion B and the cell array region A is a dummy oxide film after the wet etching process. It is improved by the thickness of 19. Subsequently, a dielectric film 15 is formed on the entire surfaces of the exposed storage nodes 9 and 20, and polysilicon is deposited and patterned as a third conductive layer on the entire surface of the dielectric film 15 to form the capacitor plate electrode 16. To form.
다음에 제2(e)도에 도시된 바와 같이 기판 전면에 평탄화층으로서, BPSG(Boro phospho-silicata galss)등과 같은 산화막(17)을 형성하고 열처리를 행함으로써 더미산화막(19)에 의해 주변회로부와 셀어레이영역간의 단차가 개선된 반도체 메모리장치를 완성한다.Next, as shown in FIG. 2 (e), the peripheral circuit portion is formed by the dummy oxide film 19 by forming an oxide film 17 such as BPSG (Boro phospho-silicata galss) or the like as a planarization layer on the entire surface of the substrate. The semiconductor memory device with improved level difference between the cell and the cell array region is completed.
이상과 같이 본 발명은 더미산화막(19)에 의해 셀어레이영역과 주변회로부간의 단차가 개선되어 전체적인 평탄화구조가 이루어지므로 공정후반부에서 금속배선공정시 하프마이크론 사진식각공정이 일반조명 및 일단계식각으로도 가능하게 된다.As described above, according to the present invention, the level difference between the cell array region and the peripheral circuit portion is improved by the dummy oxide film 19, so that the overall planarization structure is achieved. It is also possible.
또한, 스토리지노드 패터닝시 종래와는 달리 HSG 폴리실리콘을 스토리지노드 형성을 위한 폴리실리콘층의 하부층으로 사용하여 난반사를 억제하는 효과를 동일하게 유지하면서 HSG폴리실리콘의 식각은 그 상부의 폴리실리콘층(9)과 함께 이루어지므로 식각공정이 종래보다 간단해진다.In addition, when patterning the storage node, unlike the conventional method, the etching of the HSG polysilicon is performed using the HSG polysilicon as the lower layer of the polysilicon layer for forming the storage node while maintaining the same effect of suppressing diffuse reflection. 9), the etching process is simpler than before.
또한, 종래에는 식각저지층으로서 질화막등을 사용하였으나, 본 발명에서는 산화막(7)의 증착시 상층부의 불순물 농도를 조절한 산화막을 사용하여 이 상층부에 의해 식각저지시킴으로써 공정이 간단해지고, 이 산화막(7) 상층부위의 부분적으로 식각된 영역은 커패시터전극용으로 사용되므로 커패시터용량이 증대되게 된다.In addition, although a nitride film or the like is conventionally used as an etch stop layer, in the present invention, the process is simplified by etch stop by the upper layer part using an oxide film in which the impurity concentration of the upper layer part is controlled when the oxide film 7 is deposited. 7) The partially etched area of the upper layer is used for the capacitor electrode, which increases the capacitor capacity.
이상 상술한 바와 같이 본 발명에 의하면, 단순한 공정에 의해 대용량의 커패시터를 형성할 수 있으며, 주변회로부 및 셀어레이간의 전체적인 평탄화가 이루어지게 되어 사진식각공정이 용이하게 된다.As described above, according to the present invention, a large-capacity capacitor can be formed by a simple process, and the entire planarization between the peripheral circuit unit and the cell array is performed, thereby facilitating a photolithography process.
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| KR100517152B1 (en) * | 2003-02-04 | 2005-09-26 | 동부아남반도체 주식회사 | Method for manufacturing the embeded semiconductor device with pip capacitor and logic transistor |
| KR100543201B1 (en) * | 1998-10-13 | 2007-04-25 | 주식회사 하이닉스반도체 | Capacitor Manufacturing Method of Semiconductor Memory Device |
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| US9082966B2 (en) * | 2013-09-26 | 2015-07-14 | Micron Technology, Inc. | Methods of forming semiconductor devices and structures with improved planarization, uniformity |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260453A (en) * | 1989-03-31 | 1990-10-23 | Toshiba Corp | Semiconductor memory device and its manufacture |
| JPH0410651A (en) * | 1990-04-27 | 1992-01-14 | Mitsubishi Electric Corp | Semiconductor memory and manufacture of the same |
| JPH0482263A (en) * | 1990-07-25 | 1992-03-16 | Sharp Corp | Semiconductor storage device |
| JPH05243518A (en) * | 1992-02-27 | 1993-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH05304269A (en) * | 1992-04-24 | 1993-11-16 | Nec Corp | Semiconductor device |
-
1994
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260453A (en) * | 1989-03-31 | 1990-10-23 | Toshiba Corp | Semiconductor memory device and its manufacture |
| JPH0410651A (en) * | 1990-04-27 | 1992-01-14 | Mitsubishi Electric Corp | Semiconductor memory and manufacture of the same |
| JPH0482263A (en) * | 1990-07-25 | 1992-03-16 | Sharp Corp | Semiconductor storage device |
| JPH05243518A (en) * | 1992-02-27 | 1993-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH05304269A (en) * | 1992-04-24 | 1993-11-16 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100543201B1 (en) * | 1998-10-13 | 2007-04-25 | 주식회사 하이닉스반도체 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| KR100517152B1 (en) * | 2003-02-04 | 2005-09-26 | 동부아남반도체 주식회사 | Method for manufacturing the embeded semiconductor device with pip capacitor and logic transistor |
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