JPH05243518A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a difference in height between a memory cell part of DRAM using a stack-type cell and a peripheral circuit part and thereby to facilitate subsequent formation of a wiring pattern. CONSTITUTION:A switching transistor 5 is formed on a P-type Si substrate 1 and a bit line 7 of W polycide and a charge storage electrode 8 of a polycrystalline Si film are formed in connection on one part of an n-type diffused layer 3 of the transistor and on the other part thereof respectively. On the substrate thus prepared, a capacity insulation film 9 an SiN film and a SiO2 film is formed and then a polycrystalline Si film 10 to be an opposed electrode is deposited by 200nm. After a silicon nitride film 11 is deposited thereon by 50nm, this film is patterned by a technique of photolithography in such a manner as to stipulate the region of the opposed electrode. Next, an exposed part of the polycrystalline Si film 10 is thermally oxidized at 850 deg.C to turn it an SiO2 film 12 the film thickness thereof is made about 440nm. Accordingly, a difference in height between a memory cell part 31 and a peripheral circuit part 32 is reduced from 850nm before the oxidation to 610nm after it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using polycrystalline silicon as a conductive material, particularly a stack type DRAM.
(Dynamic Random Access Memory).

[0002]

2. Description of the Related Art In a semiconductor device with higher integration, which requires the finest processing, a DRAM is a trench formed by digging a capacitance portion into a silicon substrate to obtain a sufficient storage capacitance. A type cell or a stack type cell in which a capacitive portion is three-dimensionally stacked and formed is adopted. Among them, in the stack type cell, as miniaturization progresses, the capacity electrode portion must be raised in order to obtain a sufficient storage capacity. However, in the lithography technique for pattern formation, the finer the resolution limit, the shallower the depth of focus. Generally, the resolution limit is proportional to the wavelength of the light source used and inversely proportional to the numerical aperture of the lens of the exposure apparatus, so to form a fine pattern, the wavelength of the light source used should be shortened or the numerical aperture of the lens should be increased. And respond.
On the other hand, on the other hand, the depth of focus is proportional to the wavelength of the light source and inversely proportional to the square of the numerical aperture of the lens. Therefore, the smaller the resolution limit is, the shallower the depth of focus becomes. Therefore, in order to form a fine pattern, it is necessary to suppress the step difference in the base as small as possible.

A method of manufacturing a DRAM using the above-described conventional stack type cell will be described below with reference to the drawings.

FIG. 4 shows a DR using a conventional stack type cell.
It is process sectional drawing which shows the manufacturing method of AM. In FIG. 4, 5 is a switching transistor, 8 is a charge storage electrode, and 20 is a counter electrode. First, as shown in FIG. 4A, a switching transistor 5 is formed on a p-type semiconductor substrate 1, and a bit line 7 is formed in one of the n-type diffusion layers 3 of the transistor 5 and a bit line 7 is formed in the other n-type diffusion layer 3. After forming the charge storage electrode 8 made of crystalline silicon, a capacitive insulating film 9 made of a multilayer film of a silicon nitride film and a silicon oxide film is formed, and a polycrystalline silicon film 10 serving as a counter electrode is further formed thereon. Next, as shown in FIG. 4B, the polycrystalline silicon film 10 is patterned by photolithography and etching to form a counter electrode 20. After that, BPSG is deposited as the second interlayer insulating film 13 and then annealed and reflowed to reduce the maximum inclination angle of the interlayer insulating film 13 in the step portion 30 between the memory cell portion 31 and the peripheral circuit portion 32. Let For example, in a 64M DRAM, it is considered that a storage capacitance of about 30fF is necessary to obtain a sufficient storage charge. For that purpose, the height of the charge storage electrode 8 is required to be approximately 800 nm when the capacity insulating film having a memory cell area of 1.5 um ² and equivalent to 6 nm in terms of SiO ² film is used.

[0005]

However, in the above-described structure, when a polycrystalline silicon film having a film thickness of 200 nm is used for the counter electrode 20, the charge accumulation is performed between the memory cell section 31 and the peripheral circuit section 32. Height of electrode 8 and counter electrode 2
A step difference of about 1 μm corresponding to a film thickness of 0 occurs, and the step difference of the step portion 30 in the second interlayer insulating film 13 cannot be sufficiently relaxed. Therefore, there has been a problem that it becomes extremely difficult to form a wiring pattern that must be performed thereafter. That is, although a fine pattern of 0.35 μm is required to be formed in 64M DRAM, the finer the pattern becomes, the smaller the depth of focus becomes in the photolithography technique, which makes it difficult to form a fine pattern on a large step. Is.

In view of the above problems, the present invention is directed to a semiconductor device in which a step difference between a memory cell portion and a peripheral circuit portion is suppressed to be small even if a height of a charge storage electrode is formed, and a wiring pattern is easily formed later. A manufacturing method is provided.

[0007]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a capacitor insulating film and a counter electrode on a semiconductor substrate on which a charge storage electrode connected to a switching transistor is formed. Sequentially forming a conductive film consisting of the above, a step of forming an oxidation resistant film that defines a region of a counter electrode on the conductive film, and a step of selectively oxidizing the conductive film not covered with the oxidation resistant film. And a step of forming a pattern of the counter electrode by oxidation without etching the conductive film.

[0008]

According to the present invention, since the conductive film of the counter electrode material on the peripheral circuit is converted into an insulating film by oxidation without being removed by etching with the above-described structure, a volume difference due to the oxidation causes a difference in level due to the height of the charge storage electrode. By absorbing the portion, the step difference between the memory cell portion and the peripheral circuit portion can be reduced.

[0009]

EXAMPLE 1 A method for manufacturing a semiconductor device according to an example of the present invention will be described below with reference to the drawings.
FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, which will be described with reference to FIG.

First, as shown in FIG. 1A, a switching transistor 5 is formed on a p-type semiconductor substrate 1 having an insulating film 2 for element isolation, and the switching transistor 5 is formed.
A silicon nitride film is formed as a capacitive insulating film 9 on a substrate formed by connecting a bit line 7 made of tungsten polycide to one side of the n-type diffusion layer 3 and a charge storage electrode 8 made of a polycrystalline silicon film 800 nm connected to the other side. After forming a so-called ONO film made of a silicon oxide film, a polycrystalline silicon film 10 serving as a counter electrode is deposited to a thickness of 200 nm. Next, as shown in FIG. 1B, the silicon nitride film 1 is formed on the polycrystalline silicon film 10.
After depositing 1 of 50 nm, the silicon nitride film 11 is patterned by photolithography and etching technique so as to define the counter electrode region.

Next, as shown in FIG. 1C, the exposed portion of the polycrystalline silicon film 10 is oxidized in a pyro atmosphere (850 ° C., 60 minutes) to change into a SiO 2 film 12.
Since the ONO film as the capacitance insulating film 9 is formed on the entire surface of the substrate during oxidation, an oxidation preventing film is formed so that the oxidizing species do not penetrate into the lower layer and the wiring layer such as the lower bit line 7 is not oxidized. Play a role of. At this time, since the thickness of the polycrystalline silicon film was 200 nm, the thickness of the SiO 2 film 12 after oxidation was about 440 nm. Therefore, this oxidation reduces the step between the memory cell portion 31 and the peripheral circuit portion 32 to 610 nm as compared with 850 nm (the height of the charge storage electrode 8 + the film thickness of the silicon nitride film 11 of 50 nm) before the oxidation. .. Next, as shown in FIG. 1D, a BPSG film is deposited to a thickness of 500 nm as the second interlayer insulating film 13 and 900
Annealing for 30 minutes in a nitrogen atmosphere for reflow, the maximum inclination angle of the second interlayer insulating film 13 in the step portion 30 between the memory cell portion 31 and the peripheral circuit portion 32 is about 3
It becomes possible to set it to 0 degree, and the subsequent wiring layer can be formed extremely easily.

As described above, according to this embodiment, even if a stack type cell having a conventional simple structure is formed to be high, the counter electrode is converted into an insulating film by oxidation without etching. Since the step difference between the memory cell portion and the peripheral circuit portion can be effectively reduced by the expansion, it becomes possible to easily form a fine wiring pattern later.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a sectional view showing the steps of a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
Will be explained.

First, as shown in FIG. 2A, a switching transistor 5 is formed on a p-type semiconductor substrate 1 having an element isolation insulating film 2, and the switching transistor 5 is formed.
On a substrate formed by connecting the bit line 7 made of tungsten polycide to one of the n-type diffusion layers 3 and the charge storage electrode 8 made of a polycrystalline silicon film 800 nm to the other,
The capacitive insulating film 9 is made of a silicon nitride film and a silicon oxide film,
After forming a so-called ONO film, a polycrystalline silicon film 10 serving as a counter electrode is deposited to a thickness of 200 nm. Next, FIG. 2 (b)
After depositing a silicon nitride film 11 on the polycrystalline silicon film 50 to a thickness of 50 nm, the silicon nitride film 11 is patterned by photolithography and etching techniques so as to define a counter electrode region.

Next, as shown in FIG. 2C, the exposed portion of the polycrystalline silicon film 10 is oxidized in a pyro atmosphere (850 ° C., 60 minutes) to change into a SiO 2 film 12. At this time, since the thickness of the polycrystalline silicon film was 200 nm, the thickness of the SiO 2 film 12 after oxidation was about 440 nm. Next, as shown in FIG. 2D, the silicon nitride film 11 is selectively removed with a hot phosphoric acid solution, and then a BPSG film is deposited to a thickness of 500 nm as a second interlayer insulating film 13 in a nitrogen atmosphere at 900 degrees. After annealing for 30 minutes and reflowing, the step portion 3 between the memory cell portion 31 and the peripheral circuit portion 32 is formed.
The maximum inclination angle of the second interlayer insulating film 13 of 0 can be set to 30 degrees or less, and the subsequent wiring layer can be formed extremely easily. In the case of this embodiment, the memory cell portion 31 is removed by removing the silicon nitride film 11 after the oxidation.
And the peripheral circuit portion 32 have a step difference of 850 nm before oxidation (height of the charge storage electrode 8 + thickness of the silicon nitride film 11 of 50 nm).
This means that it is reduced to 560 nm compared to Therefore, it is possible to further reduce the step difference as compared with the first embodiment, and the maximum inclination angle of the second interlayer insulating film 13 in the step portion can also be set to 30 degrees or less.

As described above, according to the present embodiment, even if a stack type cell having a conventional simple structure is formed to be high, the counter electrode is converted into an insulating film by oxidation without etching, and then used as a mask for oxidation. By removing the used silicon nitride film, the step difference between the memory cell portion and the peripheral circuit portion can be effectively reduced due to the volume expansion due to the oxidation, so that it is possible to easily form a fine wiring pattern later. ..

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a sectional view showing the steps in a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
Will be explained.

First, as shown in FIG. 3A, a switching transistor 5 is formed on a p-type semiconductor substrate 1 having an element isolation insulating film 2, and the switching transistor 5 is formed.
On a substrate formed by connecting the bit line 7 made of tungsten polycide to one of the n-type diffusion layers 3 and the charge storage electrode 8 made of a polycrystalline silicon film 800 nm to the other,
The capacitive insulating film 9 is made of a silicon nitride film and a silicon oxide film,
After forming a so-called ONO film, a polycrystalline silicon film 10 serving as a counter electrode is deposited to a thickness of 200 nm. Next, FIG. 3 (b)
After depositing a silicon nitride film 11 on the polycrystalline silicon film 10 to a thickness of 50 nm, the silicon nitride film 11 is patterned by photolithography and etching techniques so as to define a counter electrode region. Next, as shown in FIG. 3C, a BPSG film is used as the second interlayer insulating film 13.
Deposit 0 nm.

Next, as shown in FIG. 3D, a portion of the polycrystalline silicon film 10 which is not covered with the silicon nitride film 11 is oxidized in a pyro atmosphere (850 ° C., 60 minutes) to make SiO 2
At the same time as changing to the film 12, the second interlayer insulating film 13
To reflow. As a result, the second interlayer insulating film 1 in the step portion 30 between the memory cell portion 31 and the peripheral circuit portion 32 is formed.
The maximum inclination angle of 3 can be set to about 30 degrees, and the subsequent wiring layer can be formed extremely easily. In the case of this embodiment, the effect of reducing the step difference is equivalent to that of the first embodiment,
The number of steps can be reduced by simultaneously performing oxidation and reflow.

As described above, according to this embodiment, even if a stack type cell having a conventional simple structure is formed high, the counter electrode is converted into an insulating film by oxidation without etching, and at the same time the interlayer on the counter electrode is etched. Since the insulating film can be reflowed, the effect of effectively reducing the step between the memory cell part and the peripheral circuit part due to the volume expansion due to oxidation can be realized in a few steps, and the subsequent formation of a fine wiring pattern can be easily performed. Is possible.

Although the ONO film functions as an antioxidant film as described above in the first to third embodiments, a silicon nitride film is previously formed on the first interlayer insulating film 6 before the charge storage electrode 8 is formed. If so, a more sufficient antioxidant effect can be obtained. Also, when a high dielectric film other than ONO is used as the capacitive insulating film, a silicon nitride film is formed in advance on the first interlayer insulating film 6 before the charge storage electrode 8 is formed, so that an antioxidation effect can be obtained. Obtainable.

[0024]

As described above, according to the present invention, a step of sequentially forming a capacitive insulating film and a conductive film to be a counter electrode on a semiconductor substrate on which a charge storage electrode connected to a switching transistor is formed; And a step of selectively oxidizing the conductive film that is not covered with the oxidation resistant film, without etching the conductive film. By forming the pattern of the counter electrode by oxidation, even if the stack type cell of the conventional simple structure is formed to be high, the counter electrode is not etched but the volume expansion by changing to the insulating film by oxidation is effective. Since the step difference between the memory cell portion and the peripheral circuit portion can be reduced, the subsequent wiring pattern can be easily formed. Further, it becomes possible to form the charge storage electrode beyond the height which has been limited by the conventional photolithography. Furthermore, since the conventional stack type cell having a simple structure can be used, it is not necessary to adopt a complicated three-dimensional structure that requires a large number of steps, so that the practical effect thereof is extremely large.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

4A to 4C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 5 Switching transistor 7 Bit line 8 Charge storage electrode 9 Capacitance insulating film 20 Counter electrode

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, wherein pattern formation is performed by oxidation without etching a conductive layer made of polycrystalline silicon. 2. A step of sequentially forming a capacitive insulating film and a conductive film to be a counter electrode on a semiconductor substrate having a charge storage electrode connected to a switching transistor, and defining a region of the counter electrode on the conductive film. A step of forming an oxidation resistant film and a step of selectively oxidizing the conductive film not covered with the oxidation resistant film are provided, and the patterning of the counter electrode is performed by oxidation without etching the conductive film. A method for manufacturing a semiconductor device, comprising: 3. A method of manufacturing a semiconductor device according to claim 2, further comprising the step of removing the oxidation resistant film. 4. A step of sequentially forming a capacitive insulating film and a conductive film to be a counter electrode on a semiconductor substrate on which a charge storage electrode connected to a switching transistor is formed, and a region of the counter electrode is defined on the conductive film. A step of forming an oxidation resistant film, a step of depositing a fluid insulating film on the oxidation resistant film by a heat treatment in an oxidizing atmosphere, and a selective oxidation of the conductive film not covered with the oxidation resistant film. And a step of performing reflow of the insulating film at the same time, and a patterning of the counter electrode is performed by oxidation without etching the conductive film.