KR0151071B1 - Soi type semiconductor device & its manufacturing method - Google Patents

Abstract

A method of manufacturing a semiconductor memory device using a silicon-on-insulator (SOI) structure is disclosed. After forming a first insulating film on the first semiconductor substrate, a trench is formed by etching the first insulating film and the semiconductor substrate by a photolithography process. A dielectric film and a storage node are sequentially formed in the trench to form a trench capacitor, and then a second insulating film is formed on the resultant. After the SOI layer is formed on the second insulating film of the first semiconductor substrate, the gate of the transistor is formed thereon. After the second insulating layer is etched to form a contact hole exposing the storage node of the trench capacitor, a storage node contact is formed to connect the storage node and the SOI layer. The formation of storage node contacts is very simple and easy, and there is no problem of talking between trenches.

Description

Method of manufacturing a semiconductor memory device having a silicon-on-insulator structure

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first semiconductor substrate 12: first insulating film

14: trench 16: storage node

18: second insulating film 20: SOI layer

22: active area 24: gate

26: storage node contact 28: third insulating film

30: bit line

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a dynamic random access memory (DRAM) having a structure of a silicon on insulator (hereinafter referred to as SOI).

Semiconductor memory devices, particularly DRAM stationary devices, use capacitors as information storage means, and controllable signal transmission means connected thereto constitute a memory cell together with a switching transistor. In such DRAM devices, the reduction of cell capacitance due to the reduction of the memory cell area is a serious obstacle to increasing the density of DRAM, which not only reduces the readability of the memory cell and increases the soft error rate but also device operation at low voltage. This makes it difficult to consume excessive power during operation. Therefore, many methods for increasing capacitance within a limited cell area have been proposed, and can be generally divided into three types. That is, (1) thinning the dielectric film, (2) using a material having a high dielectric constant, and (3) increasing the effective area of the capacitor.

Among these, the first method has a disadvantage in that it is difficult to apply to a large-capacity memory device when the thickness of the dielectric film is reduced to 100 Å or less because reliability is degraded by Fowler-Nordheim current.

In the second method, the tantalum pentoxide (Ta ₂ O ₅ ) film having excellent coverage for a three-dimensional memory cell structure having a large aspect ratio instead of a dielectric film composed of a composite film of a nitride / oxide film is used. Research is widespread. However, since Ta ₂ O ₅ has a large leakage current and a small breakdown voltage in a thin film state, it is difficult to apply it to mass production products at this time.

Therefore, the third method is currently being developed the most, and the main method is to increase the effective capacitor area by increasing the height or depth of the capacitor while using the existing dielectric film made of a composite film of nitride / oxide film. However, this method has a problem in that as the semiconductor device is scaled down, the margin between the contact itself and other wiring connecting the source / drain of the capacitor and the transistor becomes smaller.

Recently, a trench type DRAM has been developed in which the junction between the trench storage node and the array device is self-aligned. (Refer to '93 IDEM, pp. 627-630, A 0.6 μm ² 256 Mb Trench. DRAM Cell With Self-Aligned Buried strap). However, the above-described structure is difficult to apply to DRAMs that are highly integrated at 1 Giga level or more because trench-specific problems such as the problem of talking between trenches and trenches are still not solved.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device that can easily increase capacitance while solving the problems of the conventional method described above.

In order to achieve the above object, the present invention comprises the steps of forming a first insulating film on the first semiconductor substrate; Forming a trench by etching the first insulating layer and the semiconductor substrate by a photolithography process; Forming a trench capacitor by sequentially forming a dielectric layer and a storage node in the trench; Forming a second insulating film on a resultant product in which the trench capacitor is formed; Forming a silicon-on-insulator (SOI) layer on the second insulating film of the first semiconductor substrate; Forming a gate of a transistor on the SOI layer; Etching the second insulating layer to form a contact hole exposing a storage node of the trench capacitor; And forming a storage node contact connecting the storage node and the SOI layer.

According to one aspect of the invention, the step of forming the trench capacitor, forming a dielectric film on the inner wall of the trench; Forming a conductive layer on a resultant material on which the dielectric film is formed; And etching the conductive layer by a chemical mechanical polishing (CMP) method to form a storage node made of the conductive layer only inside the trench.

According to another aspect of the present invention, the forming of the SOI layer includes: planarizing a surface of the second insulating film; Adhering a second semiconductor substrate on the planarized second insulating film; And grinding and polishing the second semiconductor substrate to form an SOI layer.

According to another aspect of the present invention, the forming of the storage node contact comprises: depositing a conductive layer on a resultant in which the contact hole is formed; And etching back the conductive layer.

According to still another aspect of the present invention, the method may further include forming the active region of the SOI layer by etching the SOI layer by a photolithography process before forming the gate.

According to the present invention, the formation of a storage node contact is very simple and easy as compared with the conventional method of manufacturing a trench type DRAM, and the first semiconductor substrate serves only as a plate node of the capacitor and is perfectly connected to the SOI layer thereon. Because it's nice, there's no talking problem between trenches.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 1A shows the steps of forming the first insulating film 12 and the trench 14. An insulating material, for example, CVD oxide, is deposited on the N ⁺ type first semiconductor substrate 10 to form the first insulating film 12. Subsequently, after the first insulating layer 12 is patterned by a photolithography process, the first semiconductor substrate 10 is etched to a predetermined depth by using the patterned first insulating layer 12 as an etching mask. 14) form. The trench 14 can change its width and depth in accordance with the desired capacitance.

FIG. 1B shows the step of forming the capacitor and the second insulating film 18. After forming a dielectric film (not shown) on the inner wall of the trench 14, for example, a dielectric film made of a composite film of a nitride / oxide film, sufficient to completely fill the inside of the trench 14 on the resultant. By thickness, a conductive layer, such as a polysilicon layer doped with impurities, is deposited. Subsequently, the conductive layer is etched by the CMP method to form the storage node 16 made of polysilicon doped with impurities only in the trench 14. As a result of the above process, the trench capacitor is completed. In this case, the first semiconductor substrate 10 surrounding the trench 14 is used as a plate node of the trench capacitor. Subsequently, an insulating material, for example, CVD oxide, is deposited on the resultant trench capacitor to form a second insulating film 18. After the formation of the second insulating film 18, the method may further include planarizing the surface of the second insulating film 18 by polishing or etching back.

1C illustrates the step of forming the SOI layer 20. A second semiconductor substrate made of a new wafer is bonded to the second insulating film 18 of the first semiconductor substrate 10 using a conventional wafer bonding method. Subsequently, the second semiconductor substrate is etched by grinding and CMP to form an SOI layer 20 made of a second semiconductor substrate having a predetermined thickness on the second insulating layer 18.

FIG. 1D shows the step of forming the gate 24. After etching the SOI layer 20 by a conventional photolithography process, the active region 22 of the SOI layer is formed by embedding the etched portion with an insulator. In this case, the portion buried with the insulator becomes an element isolation region. Subsequently, a gate insulating film and a gate 24 are sequentially formed on the resultant product in which the active region 22 is formed. Subsequently, source and drain (not shown) regions are formed in the active region 22 by a conventional transistor manufacturing process.

1E illustrates forming a storage node contact 26. The second insulating film 18 is etched by a photolithography process to form a contact hole exposing the storage node 16 of the trench capacitor, and then a conductive layer such as a polysilicon layer doped with impurities is deposited on the resultant. do. Subsequently, the conductive layer is etched back to form a storage node contact 26 connecting the storage node 16 and the active region 22 of the SOI layer, for example, a source region.

FIG. 1F illustrates the step of forming the bit line 30. The third insulating layer 28 is formed by depositing an insulating material on the resultant material on which the storage node contact 26 is formed. After forming the third insulating layer 28, a step of forming a planarization layer thereon may be further provided. Subsequently, the second insulating layer 28 is etched by a photolithography process to form bit line contact holes exposing the active region 22, for example, the drain region, of the SOI layer. Next, a bit line 30 is formed by depositing a conductive layer on the resultant bit line contact hole and patterning it by a photolithography process. Next, although not shown, the DRAM cell is completed by performing a metal wiring process.

Therefore, according to the manufacturing method of the semiconductor memory device according to the present invention as described above, since the capacitor is formed in a trench type, there is no limitation of the capacitor depth, so it is very easy to secure the capacitance. In addition, since the formation of the storage node contacts is very simple and easy as compared with the conventional method of manufacturing a trench type DRAM, the first semiconductor substrate serves only as a plate node of the capacitor and is completely insulated from the SOI layer thereon. There is no talking problem between the trench and the trench.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (5)

Forming a first insulating film on the first semiconductor substrate; Forming a trench by etching the first insulating layer and the semiconductor substrate by a photolithography process; Forming a trench capacitor by sequentially forming a dielectric layer and a storage node in the trench; Forming a second insulating film on a resultant product in which the trench capacitor is formed; Forming a silicon-on-insulator (SOI) layer on the second insulating film of the first semiconductor substrate; Forming a gate of a transistor on the SOI layer; Etching the second insulating layer to form a contact hole exposing a storage node of the trench capacitor; And forming a storage node contact connecting the storage node and an SOI layer. The method of claim 1, wherein the forming of the trench capacitor comprises: forming a dielectric film on an inner wall of the trench; Forming a conductive layer on a resultant material on which the dielectric film is formed; And etching the conductive layer by a chemical mechanical polishing (CMP) method to form a storage node made of the conductive layer only inside the trench. The method of claim 1, wherein the forming of the SOI layer comprises: planarizing a surface of the second insulating layer; Adhering a second semiconductor substrate on the planarized second insulating film; And grinding and polishing the second semiconductor substrate to form an SOI layer. The method of claim 1, wherein the forming of the storage node contact comprises: depositing a conductive layer on a resultant in which the contact hole is formed; And etching back the conductive layer to form a storage node contact connecting the storage node and the SOI layer. The method of claim 1, further comprising forming an active region of the SOI layer by etching the SOI layer by a photolithography process before forming the gate.