CN103824884A - Super-junction MOSFET and formation method of super-junction MOSFET - Google Patents
Super-junction MOSFET and formation method of super-junction MOSFET Download PDFInfo
- Publication number
- CN103824884A CN103824884A CN201210468002.4A CN201210468002A CN103824884A CN 103824884 A CN103824884 A CN 103824884A CN 201210468002 A CN201210468002 A CN 201210468002A CN 103824884 A CN103824884 A CN 103824884A
- Authority
- CN
- China
- Prior art keywords
- groove
- epitaxial loayer
- termination environment
- junction mosfet
- super junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 31
- 230000015572 biosynthetic process Effects 0.000 title claims description 18
- 230000001413 cellular effect Effects 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 19
- 238000002513 implantation Methods 0.000 description 10
- 238000000137 annealing Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010019133 Hangover Diseases 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention brings forward a super-junction MOSFET with an equilibrium structure. The super-junction MOSFET comprises a cellular area which is formed on a substrate and a terminal area which embraces the cellular area. Straight strip-type grooves with equal spacing distance are respectively formed in the cellular area and the terminal area. A first conductive type first epitaxial layer is formed in each groove. Second conductive type second epitaxial layers are formed between the grooves. The grooves of the terminal area are arranged in consistent mode along direction from outside to inside. According to the super-junction MOSFET, the grooves of each side of the terminal area are arranged in consistent mode along direction from the terminal area to the cellular area, i.e. the grooves of each side of the terminal area are vertically arranged along direction from outside to inside, or the grooves of each side of the terminal area are arranged in parallel along direction from outside to inside. The grooves of each side of the terminal area are arranged in consistent mode so that discharge of high voltage and heavy current of the super-junction MOSFET is average at each side, a flow discharge channel is larger and flow discharge capability is higher.
Description
Technical field
The invention belongs to essential electronic element field, relate to the preparation of semiconductor device, particularly structure of a kind of super junction MOSFET, this super junction MOSFET and forming method thereof.
Background technology
At present, high-voltage power MOSFET (Metal Oxide Semiconductor Field EffectTransistor, MOS (metal-oxide-semiconductor) memory) is widely used in high-power circuit.In ON state situation, it should have lower conducting resistance; In OFF state situation, it should have higher puncture voltage.For traditional power VDMOSFET FET, generally improve puncture voltage by the mode that increases epitaxial thickness and reduction epi dopant concentration.But along with the raising of puncture voltage, epilayer resistance increases rapidly.Research shows, for desirable N ditch power MOSFET, has the relation of Ron ∝ VB2.5 between conducting resistance and puncture voltage.Contradiction between conducting resistance and puncture voltage, should have high puncture voltage to have again low conducting resistance, becomes the obstacle of manufacturing high-performance power device.
In order to overcome the contradiction between conventional power MOSFET conducting resistance and puncture voltage, there is a kind of new desirable device architecture, be called super junction MOSFET device, in the structure of this super junction, due to the mutual balance of electric charge comprising in N-shaped the N-shaped post adulterating and the p-type post that comprises p-type doping, make Electric Field Distribution different from conventional power MOSFET, the critical field strength of drift region is almost steady state value, therefore, puncture voltage only depends on the thickness of epitaxial loayer, and irrelevant with doping content, epitaxy layer thickness is larger, and the puncture voltage of device is larger.In addition, in super junction MOSFET device, the concentration of drift region also can be done highlyer, and this has guaranteed lower conducting resistance.
Super junction is based on charge compensation principle, it is the device of many electronic conductions, eliminate hangover delay when IGBT turn-offs, the low conduction loss of the low switching losses of power MOSFET and IGBT is combined, realize the design optimization between break-over of device resistance and puncture voltage, utilized the MOSFET of super junction that high voltage and large electric current can be provided.There are some researches show, the conducting resistance of super junction MOSFET and the pass of puncture voltage are Ron ∝ V
b 1.32, this is a breakthrough to relation between traditional conducting resistance and puncture voltage.
Super junction MOSFET requires P type post and N-type post balanced proportion, and P type post and N-type post are exhausted each other in the time bearing back-pressure.Owing to digging the restriction of deep trouth process conditions, the length-width ratio of the domain figure of deep trouth requires to be greater than 10, makes to draw bar shaped domain and has certain restriction.In Fig. 1, P type post and N-type post near corner's deep trouth circular arc converges mutually with deep trouth vertical bar are difficult to balance, can become withstand voltage weak spot.In Fig. 2, P type post and N-type post are balances everywhere, but the terminal area on its top and the left side is by being different in export-oriented cellular region, and the Electric Field Distribution on these both sides is also different, also can produce thus withstand voltage some difference.In device application, in inductive load situation, high-voltage great-current when it turn-offs may most ofly only flow away from the right and left (or upper and lower both sides), and it is disadvantageous that this energy is released to chip, easily causes local overheating and defective chip.
Summary of the invention
The present invention is intended at least solve the technical problem existing in prior art, has proposed to special innovation structure of a kind of super junction MOSFET, this super junction MOSFET and forming method thereof.
In order to realize above-mentioned purpose of the present invention, according to a first aspect of the invention, the invention provides a kind of super junction MOSFET structure, it comprises cellular region and termination environment, described termination environment surrounds described cellular region, in described cellular region He in termination environment, be formed with respectively the vertical bar type groove that spacing is equal, in described groove, be formed with the first epitaxial loayer of the first conduction type, between described groove, be the second epitaxial loayer of the second conduction type, the groove on each limit, described termination environment is consistent along the arrangement mode of direction outside in.
Super junction MOSFET structure of the present invention is along the direction from termination environment to cellular region, the arrangement mode of the groove on each limit, termination environment is consistent, the groove that is each limit, termination environment is all arranged along direction outside in, and arragement direction is vertical with direction outside in, or arragement direction is parallel with direction outside in.The groove arrangement mode on each limit, termination environment is consistent, and it is that current by pass is large uniformly that this super junction MOSFET structure is released at the electric current on each limit under high-voltage great-current, and discharge capacity is strong.
In order to realize above-mentioned purpose of the present invention, according to a second aspect of the invention, the invention provides a kind of formation method of super junction MOSFET structure, comprise the steps:
S1: substrate is provided, and described substrate is the first conduction type;
S2: form the second epitaxial loayer of the second conduction type on described substrate, form cellular region and termination environment in described the second epitaxial loayer, described termination environment surrounds described cellular region;
S3: form respectively the vertical bar type groove that spacing is equal in described cellular region He in termination environment, the groove on each limit, described termination environment is consistent along the arrangement mode of direction outside in, forms the first epitaxial loayer of the first conduction type in described groove.
Utilize in the structure that super junction MOSFET Structure formation method of the present invention forms the ratio of the first epitaxial loayer of All Ranges and the area of the second epitaxial loayer all identical, there is no withstand voltage weak spot, the voltage endurance capability of device is high, it is average under high-voltage great-current, releasing at the electric current on each limit, current by pass is large, discharge capacity is strong, and manufacture process and existing power device technique compatibility completely.
In order to realize above-mentioned purpose of the present invention, according to a third aspect of the present invention, the invention provides a kind of super junction MOSFET, comprise substrate, the first epitaxial loayer and the second epitaxial loayer obtaining according to super junction MOSFET structure as above, described the second epitaxial loayer is divided into two parts by described the first epitaxial loayer, the first epitaxial loayer and the second epitaxial loayer are formed on described substrate, described substrate is the first conduction type, described the first epitaxial loayer is the first conduction type, and described the second epitaxial loayer is the second conduction type; The first diffusion region, described the first diffusion region is formed in described the first epitaxial loayer and in a part the second epitaxial loayer adjacent with described the first epitaxial loayer, and described the first diffusion region is the first conduction type; The second diffusion region, described the second diffusion region is formed in described the first diffusion region, and described the second diffusion region is the second conduction type, and the first diffusion region between described the second diffusion region and the second epitaxial loayer is conducting channel; Gate dielectric layer, described gate dielectric layer is formed on described the second epitaxial loayer, conducting channel and a part of the second diffusion region; Grid, described grid is formed on described gate dielectric layer; Dielectric layer, described dielectric layer is formed on described grid, has the contact hole connecting to described the first diffusion region on described dielectric layer; Source metal, described source metal is formed on described dielectric layer and the first diffusion region, and described source metal is connected with the first diffusion region by contact hole; Drain metal layer, described drain metal layer is formed under substrate.
The super junction MOSFET that utilizes super junction MOSFET structure of the present invention to form, voltage endurance capability equilibrium between multiple super junction MOSFET, the voltage endurance capability of device is high.
In a kind of preferred implementation of the present invention, in described lateral trench and longitudinal groove intersection, the spacing of lateral trench and longitudinal groove is the half of two equidirectional groove pitch.
The present invention is in lateral trench and longitudinal groove intersection, the spacing of lateral trench and longitudinal groove is the half of two equidirectional groove pitch, can guarantee that like this groove All Ranges in MOSFET structure is all uniformly distributed, the discharge capacity of regional is identical, there is no withstand voltage weak spot.
In another kind of preferred implementation of the present invention, in the unit are of described cellular region and termination environment, the area ratio that described groove occupies is identical.
The groove area occupied ratio of cellular region of the present invention and termination environment is identical, and in zones of different, the first epitaxial loayer is identical with the ratio of the area of the second epitaxial loayer, there is no withstand voltage weak spot, and the voltage endurance capability of device is high.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is the domain of a kind of super junction cellular region of the prior art and termination environment;
Fig. 2 is the domain of another kind of super junction cellular region of the prior art and termination environment;
Fig. 3 is the domain of cellular region and termination environment in the present invention's the first preferred implementation;
Fig. 4 is the domain of cellular region and termination environment in the present invention's the second preferred implementation;
Fig. 5 is the lateral trench of domain shown in Fig. 3 and longitudinal groove intersection schematic diagram;
Fig. 6 is super junction MOSFET cross-sectional view of the present invention.
Reference numeral:
1 substrate; 2 first epitaxial loayers; 3 second epitaxial loayers; 4 first diffusion regions; 5 second diffusion regions;
6 gate dielectric layers; 7 grids; 8 dielectric layers; 9 source metal; 10 drain metal layer;
11 cellular region; 12 termination environments; 13 grooves; The line of demarcation of 14 cellular region and termination environment.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " longitudinally ", " laterally ", " on ", orientation or the position relationship of the indication such as D score, 'fornt', 'back', " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward " be based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, rather than indicate or imply that the device of indication or element must have specific orientation, construct and operation with specific orientation, therefore can not be interpreted as limitation of the present invention.
In description of the invention, unless otherwise prescribed and limit, it should be noted that, term " installation ", " being connected ", " connection " should be interpreted broadly, for example, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be to be directly connected, and also can indirectly be connected by intermediary, for the ordinary skill in the art, can understand as the case may be the concrete meaning of above-mentioned term.
The invention provides the structure of a kind of super junction MOSFET, comprise cellular region 11 and termination environment 12, described termination environment 12 surrounds described cellular region 11, in this cellular region 11 and termination environment 12 is interior is formed with respectively the vertical bar type groove 13 that spacing is equal, the degree of depth of groove 13 can be according to the requirement of MOSFET puncture voltage is designed, in the time needing the large MOSFET of high-breakdown-voltage, the degree of depth that should corresponding increase groove 13.In groove 13, being formed with the first epitaxial loayer 2 of the first conduction type, is the second epitaxial loayer 3 of the second conduction type between groove 13.The groove 13 of termination environment 12 is consistent along the arrangement mode of direction outside in.
Fig. 3 is the domain of cellular region 11 and termination environment 12 in the present invention's the first preferred implementation, is only the size that has provided each region of signal in figure, and concrete size can design according to the requirement of device parameters.As seen from the figure, in the present embodiment, 14Jiang cellular region 11, line of demarcation and the termination environment 12 of cellular region and termination environment are cut apart, the groove 13 of cellular region 11 is longitudinally arranged, the groove 13 of 11 the right and left termination environments 12, cellular region is longitudinally arranged, and the groove 13 of termination environment, both sides 12 Shang Xia 11, cellular region is laterally arranged.As can be seen here, the groove 13 on 12 4 limits, termination environment is arranged along direction outside in, and arragement direction is vertical with direction outside in.
Fig. 4 is the domain of cellular region 11 and termination environment 12 in the present invention's the second preferred implementation, as seen from the figure, in the present embodiment, the groove 13 of cellular region 11 is longitudinally arranged, the groove 13 of 11 the right and left termination environments 12, cellular region is laterally arranged, the groove 13 of termination environment, both sides 12 Shang Xia 11, cellular region is longitudinally arranged, and the groove 13 of termination environment, both sides 12 Shang Xia 11, cellular region and the groove 13 of cellular region 11 are connected.As can be seen here, the direction of the groove 13 on 12 4 limits, termination environment is arranged along direction outside in, and arragement direction is parallel with direction outside in.
Super junction MOSFET structure of the present invention is along the direction of 12Xiang cellular region, termination environment 11, the arrangement mode of the groove 13 on 12Ge limit, termination environment is consistent, the groove 13 that is 12Ge limit, termination environment is all arranged along direction outside in, and arragement direction is vertical with direction outside in, or arragement direction is parallel with direction outside in.Groove 13 arrangement modes on 12Ge limit, termination environment are consistent, and make this super junction MOSFET structure is that current by pass is large uniformly at the leakage current on each limit under high-voltage great-current, and discharge capacity is strong.
The present invention is in lateral trench and longitudinal groove intersection, and the spacing of lateral trench and longitudinal groove is the half of two equidirectional groove pitch.As shown in Figure 5, at laterally deep trouth vertical bar and longitudinally deep trouth vertical bar intersection, laterally deep trouth vertical bar is A with the spacing of longitudinal deep trouth vertical bar, this spacing is the half of equidirectional deep trouth spacing 2A, like this in the unit are of cellular region 11 and termination environment 12, the area ratio that groove 13 occupies is identical, in cellular region 11 and termination environment 12, groove 13 area occupied ratios are identical, in Fig. 5, the cell area that black lines is divided is identical, is a unit are, and the area ratio shared in each cell internal channel 13 is identical.The groove 13 area occupied ratios of cellular region 11 and termination environment 12 are identical, and in zones of different, the discharge capacity of regional is identical, there is no withstand voltage weak spot, and the voltage endurance capability of device is high.In a kind of preferred implementation of the present invention, in the unit are of cellular region 11 and termination environment 12, the area ratio that groove 13 occupies is all 1 mutually: 4-1: 2.
The present invention also provides a kind of formation method of super junction MOSFET structure, comprises the steps:
S1: substrate 1 is provided, and this substrate 1 is the first conduction type;
S2: form the second epitaxial loayer 3 of the second conduction type on substrate 1, in the interior formation of this second epitaxial loayer 3 cellular region 11 and termination environment 12, and termination environment 12 surrounds cellular region 11;
S3: in cellular region 11 and termination environment 12 is interior forms respectively the vertical bar type groove 13 that spacing is equal, the groove 13 on 13Ge limit, termination environment is consistent along the arrangement mode of directions outside in, at the first epitaxial loayer 2 of interior formation the first conduction type of groove 13.
In a preferred embodiment of the present invention, the formation method of this super junction MOSFET structure specifically comprises the steps:
The first step: substrate 1 is provided, and this substrate 1 is the first conduction type, this substrate 1 is any backing material of preparation MOSFET, can be specifically but be not limited to SOI, silicon, germanium, GaAs, in the present embodiment, preferably adopts silicon.
Second step: epitaxial growth forms the second epitaxial loayer 3 of the second conduction type on substrate 1, this second epitaxial loayer 3 is divided into cellular region 11 and termination environment 12, and makes termination environment 12 surround cellular region 11.
The 3rd step: in cellular region 11 and termination environment 12 is interior forms respectively the vertical bar type groove 13 that spacing is equal, the groove 13 on 12Ge limit, termination environment is consistent along the arrangement mode of directions outside in, at the first epitaxial loayer 2 of interior formation the first conduction type of groove 13.Specifically can be but be not limited to photoetching in the method for interior formation the first epitaxial loayer 2 of groove 13, in the situation that mask is sheltered, carry out Implantation, and diffusion, the method for annealing.
The second epitaxial loayer 3 between the first epitaxial loayer 2 and groove 13 in groove 13 of the present invention can adopt extension and Implantation to form, and also can adopt repeatedly extension and Implantation to form.In the time adopting repeatedly extension and Implantation to form, specifically extension and Implantation step are each time: on substrate 1, form the first epitaxial loayer 2 by epitaxial growth method, then on the first epitaxial loayer 2, form the second epitaxial loayer 3 by the mode of Implantation.
In the other preferred implementation of the present invention, also can adopt the method for dry etching or wet etching to form groove 13, then can adopt but the method that is not limited to chemical vapor deposition forms the second epitaxial loayer 3.
The structure of utilizing super junction MOSFET Structure formation method of the present invention to form is all identical with the ratio of the area of the second epitaxial loayer 3 at the first epitaxial loayer 2 of regional, there is no withstand voltage weak spot, the voltage endurance capability of device is high, it is average under high-voltage great-current, releasing at the electric current on each limit, current by pass is large, discharge capacity is strong, and manufacture process and existing power device technique compatibility completely.
The structure of utilizing invention to form, the present invention has also prepared super junction MOSFET, comprise substrate 1, the first epitaxial loayer 2 and the second epitaxial loayer 3 that super junction MOSFET structure obtains according to the present invention, this first epitaxial loayer 2 and the second epitaxial loayer 3 are all formed on substrate 1, and the second epitaxial loayer 3 is divided into two parts by the first epitaxial loayer 2, this substrate 1 is the first conduction type, and the first epitaxial loayer 2 is the first conduction type, and the second epitaxial loayer 3 is the second conduction type.
In the present embodiment, specifically can adopt epitaxially grown method to form the second epitaxial loayer 3, Implantation is carried out in then photoetching in the situation that mask is sheltered, and diffusion, and the method for annealing forms the first epitaxial loayer 2.In the first epitaxial loayer 2 and in a part the second epitaxial loayer 3 adjacent with the first epitaxial loayer 2, be formed with the first diffusion region 4, this first diffusion region 4 is the first conduction type, the method that forms the first diffusion region 4 can be but be not limited to photoetching, in the situation that sheltering, mask carries out Implantation, and diffusion, the method for annealing.In the first diffusion region 4, be formed with the second diffusion region 5, this second diffusion region 5 is the second conduction type, the first diffusion region 4 between the second diffusion region 5 and the second epitaxial loayer 3 is conducting channel, the method that forms the second diffusion region 5 can be but be not limited to photoetching, in the situation that sheltering, mask carries out Implantation, and diffusion, the method for annealing.On the second epitaxial loayer 3, conducting channel and a part of the second diffusion region 5, be formed with gate dielectric layer 6, on gate dielectric layer 6, be formed with grid 7, on grid 7, be formed with dielectric layer 8, this dielectric layer 8 can only cover on grid 7, also can cover as shown in Figure 6 on grid 7 and a part of the second diffusion region 5, grid 7 and the second diffusion region 5 all can also be covered.On dielectric layer, have the contact hole connecting to the first diffusion region 5, on dielectric layer 8 and the first diffusion region 5, be formed with source metal 9, this source metal 9 is connected with the first diffusion region 4 by contact hole.Under substrate 1, be formed with drain metal layer 10.
In a kind of preferred implementation of the present invention, to make super junction MOSFET as example on N-shaped substrate 1, for the device of preparing on p-type substrate, according to contrary doping type doping.As shown in Figure 6, when form (not shown in FIG.) behind cellular region 11 of the present invention and termination environment 12 on substrate 1, in the first epitaxial loayer 2 of cellular region 11 and the adjacent N-shaped interior formation p-type of the second epitaxial loayer 3 the first diffusion region 4 thereof, in heavily doped the second diffusion region 5 of the interior formation N-shaped in this first diffusion region 4, the first diffusion region 4 between the second diffusion region 5 and N-shaped the first epitaxial loayer 2 is conducting channel, the concrete grammar that forms diffusion region is photoetching, in the situation that sheltering, mask carries out Implantation, and diffusion, the method for annealing.On N-shaped the second epitaxial loayer 3, conducting channel and a part of the second diffusion region 5, be formed with gate dielectric layer 6, this gate dielectric layer 6 can be to prepare any gate dielectric material using in transistor, can be but be not limited to silicon dioxide, the concrete grammar that forms gate dielectric layer can be but be not limited to chemical vapor deposition.On gate dielectric layer 6, be formed with grid 7, this grid 7 can be but be not limited to polysilicon gate or metal gates, in the present embodiment, preferably adopts polysilicon gate, and the concrete grammar that forms grid 7 can be but be not limited to chemical vapor deposition.On grid 7, be formed with the dielectric layer 8 of insulation, this dielectric layer 8 can for but be not limited to oxide, the nitride of silicon, the nitrogen oxide of silicon, the boron-phosphorosilicate glass of silicon, in the present embodiment, preferably adopt boron-phosphorosilicate glass layer, this dielectric layer has the contact hole connecting to the first diffusion region, on dielectric layer 8 and the first diffusion region 4, be formed with source metal 9, this source metal 9 is connected with the first diffusion region 4 by contact hole, is formed with drain metal layer 10 under substrate 1.
Voltage endurance capability equilibrium between the multiple super junction MOSFET of the present invention, the voltage endurance capability of device is high.And super junction MOSFET of the present invention is in direction outside in, groove 13 arrangement modes on 12Ge limit, termination environment are consistent, groove 13 arragement directions that are termination environment 12 all distribute with direction outside in,, and arragement direction is vertical with direction outside in; Or groove 13 arragement directions of termination environment 12 all distribute with direction outside in, and arragement direction is parallel with direction outside in.Groove 13 arrangement modes on 12Ge limit, termination environment are consistent, the high-voltage great-current of super junction MOSFET to release on each limit be average, current by pass is larger, discharge capacity is just stronger.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, those having ordinary skill in the art will appreciate that: in the situation that not departing from principle of the present invention and aim, can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is limited by claim and equivalent thereof.
Claims (12)
1. a super junction MOSFET structure, it is characterized in that, comprise cellular region and termination environment, described termination environment surrounds described cellular region, in described cellular region He in termination environment, be formed with respectively the vertical bar type groove that spacing is equal, in described groove, being formed with the first epitaxial loayer of the first conduction type, is the second epitaxial loayer of the second conduction type between described groove, and the groove on each limit, described termination environment is consistent along the arrangement mode of direction outside in.
2. super junction MOSFET structure as claimed in claim 1, is characterized in that, the groove on each limit, described termination environment is arranged along direction outside in, and described arragement direction is vertical with direction outside in.
3. super junction MOSFET structure as claimed in claim 1, is characterized in that, the groove on each limit, described termination environment is arranged along direction outside in, and described arragement direction is parallel with direction outside in.
4. the super junction MOSFET structure as described in claim 1-3 any one, is characterized in that, in described lateral trench and longitudinal groove intersection, the spacing of lateral trench and longitudinal groove is the half of two equidirectional groove pitch.
5. the super junction MOSFET structure as described in claim 1-3 any one, is characterized in that, in the unit are of described cellular region and termination environment, the area ratio that described groove occupies is identical.
6. super junction MOSFET structure as claimed in claim 5, is characterized in that, in the unit are of described cellular region and termination environment, the area ratio that described groove occupies is all 1 mutually: 4-1: 2.
7. a formation method for super junction MOSFET structure, is characterized in that, comprises the steps:
S1: substrate is provided, and described substrate is the first conduction type;
S2: form the second epitaxial loayer of the second conduction type on described substrate, form cellular region and termination environment in described the second epitaxial loayer, described termination environment surrounds described cellular region;
S3: form respectively the vertical bar type groove that spacing is equal in described cellular region He in termination environment, the groove on each limit, described termination environment is consistent along the arrangement mode of direction outside in, forms the first epitaxial loayer of the first conduction type in described groove.
8. the formation method of super junction MOSFET structure as claimed in claim 7, is characterized in that, the groove on each limit, described termination environment is arranged along direction outside in, and described arragement direction is vertical with direction outside in.
9. the formation method of super junction MOSFET structure as claimed in claim 7, is characterized in that, the groove on each limit, described termination environment is arranged along direction outside in, and described arragement direction is parallel with direction outside in.
10. the formation method of the super junction MOSFET structure as described in claim 7-9 any one, is characterized in that, in described lateral trench and longitudinal groove intersection, the spacing of lateral trench and longitudinal groove is the half of two equidirectional groove pitch.
The formation method of 11. super junction MOSFET structures as described in claim 7-9 any one, is characterized in that, in the unit are of described cellular region and termination environment, the area ratio that described groove occupies is identical.
12. 1 kinds of super junction MOSFET, is characterized in that, MOSFET structure comprises:
Substrate, the first epitaxial loayer and the second epitaxial loayer obtaining according to the super junction MOSFET structure as described in claim 1-6 any one, described the second epitaxial loayer is divided into two parts by described the first epitaxial loayer, the first epitaxial loayer and the second epitaxial loayer are formed on described substrate, described substrate is the first conduction type, described the first epitaxial loayer is the first conduction type, and described the second epitaxial loayer is the second conduction type;
The first diffusion region, described the first diffusion region is formed in described the first epitaxial loayer and in a part the second epitaxial loayer adjacent with described the first epitaxial loayer, and described the first diffusion region is the first conduction type;
The second diffusion region, described the second diffusion region is formed in described the first diffusion region, and described the second diffusion region is the second conduction type, and the first diffusion region between described the second diffusion region and the second epitaxial loayer is conducting channel;
Gate dielectric layer, described gate dielectric layer is formed on described the second epitaxial loayer, conducting channel and a part of the second diffusion region;
Grid, described grid is formed on described gate dielectric layer;
Dielectric layer, described dielectric layer is formed on described grid, has the contact hole connecting to described the first diffusion region on described dielectric layer;
Source metal, described source metal is formed on described dielectric layer and the first diffusion region, and described source metal is connected with the first diffusion region by contact hole;
Drain metal layer, described drain metal layer is formed under substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210468002.4A CN103824884A (en) | 2012-11-19 | 2012-11-19 | Super-junction MOSFET and formation method of super-junction MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210468002.4A CN103824884A (en) | 2012-11-19 | 2012-11-19 | Super-junction MOSFET and formation method of super-junction MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103824884A true CN103824884A (en) | 2014-05-28 |
Family
ID=50759845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210468002.4A Pending CN103824884A (en) | 2012-11-19 | 2012-11-19 | Super-junction MOSFET and formation method of super-junction MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103824884A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617133A (en) * | 2015-01-23 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Trench-type super-junction device layout structure and manufacturing method thereof |
| CN106057888A (en) * | 2015-04-02 | 2016-10-26 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN113782584A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Super junction device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101401205A (en) * | 2006-03-13 | 2009-04-01 | 飞兆半导体公司 | Periphery design for charge balance power devices |
| US20110278650A1 (en) * | 2010-05-12 | 2011-11-17 | Renesas Electronics Corporation | Power semiconductor device |
| JP2012142336A (en) * | 2010-12-28 | 2012-07-26 | Renesas Electronics Corp | Semiconductor device |
-
2012
- 2012-11-19 CN CN201210468002.4A patent/CN103824884A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101401205A (en) * | 2006-03-13 | 2009-04-01 | 飞兆半导体公司 | Periphery design for charge balance power devices |
| US20110278650A1 (en) * | 2010-05-12 | 2011-11-17 | Renesas Electronics Corporation | Power semiconductor device |
| JP2012142336A (en) * | 2010-12-28 | 2012-07-26 | Renesas Electronics Corp | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617133A (en) * | 2015-01-23 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Trench-type super-junction device layout structure and manufacturing method thereof |
| CN106057888A (en) * | 2015-04-02 | 2016-10-26 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN106057888B (en) * | 2015-04-02 | 2020-12-04 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN113782584A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Super junction device |
| CN113782584B (en) * | 2021-08-05 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Superjunction device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108807548B (en) | Extensible SGT architecture with improved FOM | |
| CN102610643B (en) | Trench MOSFET device | |
| US8519476B2 (en) | Method of forming a self-aligned charge balanced power DMOS | |
| CN102376762B (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| KR20080044127A (en) | High voltage semiconductor device and method of fabricating the same | |
| CN105280711A (en) | Charge Compensation Structure and Manufacturing Therefor | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN103258846A (en) | Dual gate lateral mosfet | |
| CN105576025A (en) | Shallow-trench half-super-junction VDMOS device and manufacturing method thereof | |
| CN102130176B (en) | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer | |
| CN103824884A (en) | Super-junction MOSFET and formation method of super-junction MOSFET | |
| CN206976353U (en) | A kind of channel-type semiconductor device for optimizing terminal structure | |
| CN102544104A (en) | High-voltage resistant tunneling transistor and preparation method thereof | |
| CN104599974A (en) | Semiconductor structure and forming method thereof | |
| CN113690303A (en) | Semiconductor device and method for manufacturing the same | |
| TWI529943B (en) | Trench power mosfet and manufacturing method thereof | |
| WO2023284481A1 (en) | Body gate laterally double-diffused metal-oxide semiconductor field effect transistor and method for preparing same | |
| CN103050535A (en) | Super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure having groove type terminal structure and preparation method thereof | |
| CN102983161B (en) | Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices | |
| CN102522338B (en) | Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region | |
| CN102403354A (en) | CoolMOS device and manufacturing method for same | |
| CN110534566B (en) | IGBT power device | |
| CN104716178A (en) | LDMOS device with deep hole and manufacturing method of LDMOS device | |
| CN203013734U (en) | Super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) | |
| CN113659011A (en) | Integrated device based on super junction MOSFET and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140528 |