CN101916729B - Method for producing SOI (Silicon on Insulator) LDMOS (Laterally Diffused Metal Oxide Semiconductor) device provided with multi-layer super-junction structure - Google Patents
Method for producing SOI (Silicon on Insulator) LDMOS (Laterally Diffused Metal Oxide Semiconductor) device provided with multi-layer super-junction structure Download PDFInfo
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Abstract
The invention discloses a method for producing a silicon on insulator LDMOS device provided with a multi-layer super-junction structure, which comprises the steps of: carrying out ion implantation on a part of top layer silicon by adopting SOI substrate to form a first layer of super-junction structure; then preparing an extensionality layer on the SOI substrate provided with at least one layer of super-junction structure, manufacturing the other layer of super-junction structure by utilizing the same technological conditions for manufacturing the first layer of super-junction structure, and ensuring that the n-type pillar regions and the p-type pillar regions of the upper layer and the lower layer are alternately arranged to form a multi-layer super-junction structure comprising at least two layers of super-junction structure; and manufacturing body regions, grid regions, source regions, drain regions and body contact regions to finish the device. The multi-layer super-junction structure is formed by adopting the extensionality and ion implantation technology, the p-type pillar regions and the n-type pillar regions of the upper and the lower layer super-junction structures are alternately arranged to further increase the contact area among the p-type pillar regions and the n-type pillar regions without bringing remarkable side effects; and the anti-breakdown capacity of the device produced by the invention is higher than that of the traditional super-junction LDMOS.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (LDMOS; Lateral Double-diffused MOSFET) manufacture method of device architecture; Especially a kind of manufacture method with silicon-on-insulator LDMOS device of multi-layer super-junction structure belongs to technical field of manufacturing semiconductors.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit).Be primarily characterized in that to add one section relatively long light dope drift region between channel region and the drain region, this drift region doping type is consistent with drain terminal, through adding the drift region, can play the effect of sharing puncture voltage.
So-called super junction LDMOS is a kind of modified model LDMOS, and promptly the low-doped N type drift region of traditional LDMOST is replaced by one group of n type post district that alternately arranges and p type post district.In theory; Because the charge compensation between the p/n post district; Super junction LDMOS can obtain very high puncture voltage, and highly doped N type post district then can obtain very low conducting resistance, and therefore ultra junction device can be obtained a good balance between puncture voltage and conducting resistance.
The super junction LDMOS device; Its essence is and introduce the pn knot in the drift region that when device is operated in maximum breakdown voltage following time, the drift region can exhaust as far as possible fully; Like this; Except having born the main voltage in n post district, pn post district depletion layer has at the interface also been born part voltage, thus the higher puncture voltage that can bear than traditional LDMOS.
Generally, in order to make the device of identical drift region length and width under maximum breakdown voltage, exhaust as far as possible fully, can dwindle the width in p/n post district; Improve the degree of depth in p/n post district, promptly improve the depth-to-width ratio in post district as far as possible, its essence is the contact area that increases between the p/n post district; That is the area of the p/n knot depletion region of inside, increase drift region, yet limit by process conditions, can't further obtain the less post sector width and the darker post district degree of depth; This be because: at first; In the ultra junction device high energy ion injection process afterwards, need carry out annealing in process, narrow like this post district causes the diffuse pollution each other of dissimilar impurity easily; Cause the imbalance of p/n post district internal charge, can reduce actual breakdown characteristics; Secondly; Cross dark post district and certainly will follow high-octane ion to inject, cause the device inside damage easily, and the inner Impurity Distribution in post district is very inhomogeneous; Still can bring the problem of the interval charge unbalance of adjacent p/n post, thereby performance is worn in the actual resistance that reduces device.
Given this, the present invention proposes a kind of manufacture method with silicon-on-insulator LDMOS device of multi-layer super-junction structure, through the interval contact area of further raising p/n post, improves the device breakdown characteristics.
Summary of the invention
The technical problem that the present invention will solve is to provide a kind of silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure, improves the device breakdown characteristics.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure may further comprise the steps:
(A) adopt the SOI substrate, the part of its top layer silicon is carried out ion inject, form the n type post district and the p type post district of laterally alternately arranging, as the ground floor super-junction structure;
(B) be formed with epitaxial growth monocrystalline silicon on the SOI substrate of one deck super-junction structure at least, the preparation epitaxial loayer; Then; Utilize the process conditions identical to make another layer super-junction structure at epitaxial loayer with making the ground floor super-junction structure; And the n type post district that makes this another layer super-junction structure and p type post district respectively with its under the p type post district and the n type post zone position of super-junction structure corresponding; Thereby the n type post district of levels super-junction structure and p type post district are staggered, obtain the multi-layer super-junction structure of forming by two-layer super-junction structure at least;
(C) utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise multi-layer super-junction structure isolate out;
(D) utilize repeatedly the ion injection mode that the part except that multi-layer super-junction structure in the said part silicon materials is mixed, form the p trap body area;
(E) end near multi-layer super-junction structure is produced the grid region on the p trap body area;
(F) in a side in said grid region, be infused in organizator contact zone and source region on the p trap body area through ion;
(G), be infused in through ion that the end away from the grid region forms the drain region on the multi-layer super-junction structure, thereby obtain the core texture of LDMOS device at the opposite side in said grid region.
As preferred version of the present invention, the method continued growth through repeating step (B) is multi-layer super-junction structure more, thereby forms by three layers or the multi-layer super-junction structure formed of multi-layer super-junction structure more.
As preferred version of the present invention, in the step (A), the n type post district that the ion injection forms and the degree of depth in p type post district are the thickness of SOI top layer silicon, and the width in n type post district and p type post district equates; P type post district forms through implanted dopant boron, and n type post district forms through implanted dopant phosphorus; When manufacturing n type post district and p type post district, make said n type post district consistent with the CONCENTRATION DISTRIBUTION in p type post district.
When step (E) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said multi-layer super-junction structure on said p trap body area then, make said grid region comprise gate dielectric material and grid material.Utilize thermal oxidation method to form said gate dielectric material.Said grid material is a polycrystalline silicon material.
Beneficial effect of the present invention is:
The present invention is under existing process conditions; Under the maximum depth-to-width ratio situation that established technology can satisfy, form multi-layer super-junction structure through extension and ion implantation technique, and staggered the arranging in p/n type post district of two-layer super-junction structure up and down; Can further improve the interval contact area of p/n type post; Be equivalent to the depth-to-width ratio in post district has been enlarged one times, this manufacture method can not brought pronounced side effects simultaneously, can guarantee that like this breakdown characteristics of device is higher than traditional super junction LDMOS.
And this multi-layer super-junction structure also has favorable expansibility; Not only can be used for the SOI substrate, also can be used for other all kinds substrates such as body silicon or sapphire, in addition; This multi-layer super-junction structure not only can be bilayer; Also can expand to three layers and even multilayer more, with the interval contact area of further raising p/n type post, thus the breakdown characteristics of boost device.
Description of drawings
Fig. 1 is the sketch map of step among the embodiment (1);
Fig. 2 is the sketch map of step among the embodiment (2);
Fig. 3 is the generalized section of ground floor super-junction structure among the embodiment;
Fig. 4 is the generalized section of the multi-layer super-junction structure be made up of first and second layers of super-junction structure among the embodiment;
Fig. 5 is the sketch map of the LDMOS device of multi-layer super-junction structure among the embodiment.
Each description of reference numerals is following among Fig. 1:
1, source electrode
2, grid
3, polysilicon gate material layer
4, p type post district
5, n type post district
6, drain electrode
7, groove isolation construction
8, SOI oxygen buried layer
9, SOI bottom silicon
10, body contact zone
11, source region
12, tagma
13, gate oxidation material layer
14, ground floor super-junction structure
15, second layer super-junction structure
16, drain region
Embodiment
Further specify the present invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is not proportionally drawn.
As shown in Figure 5; A kind of LDMOS device of multi-layer super-junction structure; Comprise substrate and be positioned at the active area on the substrate, its active area comprises: grid region, the multi-layer super-junction structure in the source region 11 of both sides, grid region and drain region 16, in the tagma under the grid region 12, between tagma 12 and drain region 16; Said multi-layer super-junction structure comprises the two-layer at least super-junction structure (comprising ground floor super-junction structure 14 and second layer super-junction structure 15) that is arranged in order from the bottom to top; Every layer of super-junction structure is made up of n type post district of laterally alternately arranging 5 and p type post district 4, can share puncture voltage.Wherein, said grid region comprises gate dielectric layer and is positioned at the gate material layer on the gate dielectric layer, for example, and gate oxidation material layer 13 and polysilicon gate material layer 3.
In multi-layer super-junction structure; The n type post district of upper strata super-junction structure is corresponding with the p type post district and the n type post zone position of its lower floor's super-junction structure respectively with p type post district; The n type post district and the p type post district of levels super-junction structure are staggered, can further improve n, the interval contact area of p type post.In addition, this multi-layer super-junction structure not only can be bilayer, also can expand to three layers and even multilayer more.
Preferably, around its active area, be provided with groove isolation construction 7, itself and other device electricity is isolated.Said substrate preferably has the substrate of insulating buried layer, like SOI (Silicon On Insulator) substrate (comprising SOI oxygen buried layer 8 and SOI bottom silicon 9), also can be other various types of substrates such as body silicon substrate or Sapphire Substrate.When choosing (SOI) substrate with insulating buried layer, this device also comprises body contact zone 10, and this body contact zone 10 can be positioned at 11 sides, source region and contact with tagma 12, is used to draw the unnecessary electric charge that assemble in tagma 12, avoids floater effect.
On grid region, source region, drain region, be respectively equipped with grid 2, source electrode 1, drain electrode 6.Wherein, have the device of the substrate of insulating buried layer for employing, source electrode 1 is located on body contact zone 10 and source region 11 intersections.
The technology that realizes this device with the SOI substrate may further comprise the steps:
(1) as shown in Figure 1, adopt the SOI substrate, the part of its top layer silicon is carried out ion inject, form the n type post district and the p type post district of laterally alternately arranging, as the ground floor super-junction structure.Wherein, Ion injects the degree of depth and the width that form n type post district and p type post district and equates respectively; The post district degree of depth is SOI top layer silicon thickness, the minimum widith design that the post sector width can provide with process conditions, (width is about 0.5um-1.5um); P type post district forms through implanted dopant boron, and n type post district forms through implanted dopant phosphorus.The profile of ground floor super-junction structure is as shown in Figure 3, and is identical with the super-junction structure of traditional LDMOS.
(2) as shown in Figure 2, be formed with epitaxial growth monocrystalline silicon on the SOI substrate of ground floor super-junction structure, the preparation epitaxial loayer.The thickness of epitaxial loayer is identical with the thickness of ground floor super-junction structure, also will be as the thickness of second layer super-junction structure.Then; Utilize the process conditions identical to make second layer super-junction structure at epitaxial loayer with making the ground floor super-junction structure; And make the n type post district of second layer super-junction structure corresponding with the p type post district and the n type post zone position of its following ground floor super-junction structure respectively, thereby the n type post district of levels super-junction structure and p type post district are staggered with p type post district.
The profile of the multi-layer super-junction structure of forming by first and second layers of super-junction structure; As shown in Figure 4; It is thus clear that staggered the arranging in p/n type post district can further be improved the interval contact area of p/n type post, be equivalent to the depth-to-width ratio in post district has been enlarged one times, it makes compatible mutually with traditional handicraft simultaneously; Can not bring pronounced side effects, can guarantee that like this breakdown characteristics of device is higher than traditional super junction LDMOS.
In addition, can also pass through the method for repeating step (2), the 3rd layer of continued growth and even multi-layer super-junction structure more further improve the interval contact area of p/n type post.
(3) utilize shallow trench isolation to leave (STI) fabrication techniques groove isolation construction, the part silicon materials that will comprise multi-layer super-junction structure isolate out, and these part silicon materials are used for the active area of fabricate devices.
(4) form one deck gate oxidation material at above-mentioned segregate part silicon materials surface by utilizing thermal oxidation method.
(5) utilize repeatedly the ion injection mode that the part except that multi-layer super-junction structure in the said part silicon materials is mixed, form the p trap body area.
(6) deposit polysilicon, doping form the polysilicon gate material on the gate oxidation material, and produce the grid region through photoetching end near multi-layer super-junction structure on the p trap body area.The grid region is made up of gate oxidation material layer and polysilicon gate material layer.
(7) in a side in said grid region, be infused in organizator contact zone and source region on the p trap body area through ion.
(8) at the opposite side in said grid region, be infused in through ion that the end away from the grid region forms the drain region on the multi-layer super-junction structure, thereby accomplish the making of active area, obtain the core texture of device.
Wherein, make p trap body area, grid region, source region, body contact zone and drain region and adopt conventional semiconductor technologies such as ion injection, etching, present embodiment only is a kind of preferred step method, and other variation also can be arranged when specifically making.Vertically arrange in the grid region and the drain region that make, and multi-layer super-junction structure is made up of the n type post district and the p type post district of laterally alternately arranging.
(9) adopt LT0 (low temperature silicon dioxide) mode growthing silica, cover whole active area.
(10) on said silicon dioxide, etch window, depositing metal then, grid, source electrode, drain electrode are drawn in photoetching.Source electrode is located on body contact zone and the source region intersection.
(11) last deposit silicon nitride generates passivation layer.
The device that obtains at last is as shown in Figure 5.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and repeat no more at this.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (9)
1. the silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure is characterized in that, may further comprise the steps:
(A) adopt the SOI substrate, the part of its top layer silicon is carried out ion inject, form the n type post district and the p type post district of laterally alternately arranging, as the ground floor super-junction structure;
(B) be formed with epitaxial growth monocrystalline silicon on the SOI substrate of one deck super-junction structure at least, the preparation epitaxial loayer; Then; Utilize the process conditions identical to make another layer super-junction structure at epitaxial loayer with making the ground floor super-junction structure; And the n type post district that makes this another layer super-junction structure and p type post district respectively with its under the p type post district and the n type post zone position of super-junction structure corresponding; Thereby the n type post district of levels super-junction structure and p type post district are staggered, obtain the multi-layer super-junction structure of forming by two-layer super-junction structure at least;
(C) utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise multi-layer super-junction structure isolate out;
(D) utilize repeatedly the ion injection mode that the part except that multi-layer super-junction structure in the said part silicon materials is mixed, form the p trap body area;
(E) end near multi-layer super-junction structure is produced the grid region on the p trap body area;
(F) in a side in said grid region, be infused in organizator contact zone and source region on the p trap body area through ion;
(G), be infused in through ion that the end away from the grid region forms the drain region on the multi-layer super-junction structure, thereby obtain the core texture of LDMOS device at the opposite side in said grid region.
2. according to the said silicon-on-insulator LDMOS device manufacture method of claim 1, it is characterized in that with multi-layer super-junction structure: in step (C) before, repeating step (B).
3. according to the said silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure of claim 1, it is characterized in that: in the step (A), the n type post district that the ion injection forms and the degree of depth in p type post district are the thickness of SOI top layer silicon.
4. according to the said silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure of claim 1, it is characterized in that: in the step (A), ion injects the n type post district of formation and the width in p type post district equates.
5. according to the said silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure of claim 1, it is characterized in that: in the step (A), p type post district forms through implanted dopant boron, and n type post district forms through implanted dopant phosphorus.
6. according to the said silicon-on-insulator LDMOS device manufacture method of claim 1, it is characterized in that: in the step (A), when manufacturing n type post district and p type post district, make said n type post district consistent with the CONCENTRATION DISTRIBUTION in p type post district with multi-layer super-junction structure.
7. according to the said silicon-on-insulator LDMOS device manufacture method of claim 1 with multi-layer super-junction structure; It is characterized in that: when step (E) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said multi-layer super-junction structure on said p trap body area then, make said grid region comprise gate dielectric material and grid material.
8. according to the said silicon-on-insulator LDMOS device manufacture method of claim 7, it is characterized in that: utilize thermal oxidation method to form said gate dielectric material with multi-layer super-junction structure.
9. according to the said silicon-on-insulator LDMOS device manufacture method with multi-layer super-junction structure of claim 7, it is characterized in that: said grid material is a polycrystalline silicon material.
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| CN102130012B (en) * | 2010-12-31 | 2012-06-27 | 中国科学院上海微系统与信息技术研究所 | LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device |
| CN102130013B (en) * | 2010-12-31 | 2012-07-11 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer |
| CN102142378B (en) * | 2011-03-04 | 2012-07-11 | 电子科技大学 | Method for manufacturing super-junction semiconductor device with extended groove |
| CN102184859A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Manufacturing method of cold metal oxide semiconductor (MOS) super-junction structure and cold MOS super-junction structure |
| CN102593007B (en) * | 2012-03-21 | 2014-08-20 | 中国科学院上海微系统与信息技术研究所 | Super junction device with multiple embedded P islands and N channels and preparation method thereof |
| CN107623039A (en) * | 2017-09-11 | 2018-01-23 | 西安电子科技大学 | There is one kind transverse and longitudinal electric field to optimize wide band gap semiconducter transverse direction double-diffused transistor simultaneously |
| CN107808902B (en) * | 2017-09-11 | 2021-06-18 | 西安电子科技大学 | Wide band gap semiconductor lateral double-diffused transistor with multi-ring electric field modulation substrate |
| CN107863378B (en) * | 2017-09-14 | 2023-06-02 | 华羿微电子股份有限公司 | Super junction MOS device and manufacturing method thereof |
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| JP2001345376A (en) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | Semiconductor device |
| JP2005045080A (en) * | 2003-07-24 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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