CN102130176A - SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer - Google Patents
SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer Download PDFInfo
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- CN102130176A CN102130176A CN2010106195096A CN201010619509A CN102130176A CN 102130176 A CN102130176 A CN 102130176A CN 2010106195096 A CN2010106195096 A CN 2010106195096A CN 201010619509 A CN201010619509 A CN 201010619509A CN 102130176 A CN102130176 A CN 102130176A
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- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 239000012212 insulator Substances 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000011248 coating agent Substances 0.000 claims description 46
- 238000000576 coating method Methods 0.000 claims description 46
- 239000010410 layer Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 13
- 239000002210 silicon-based material Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 19
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000002347 injection Methods 0.000 abstract description 7
- 239000007924 injection Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000009827 uniform distribution Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention discloses an SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with a buffer layer, which comprises an SOI substrate and an active region positioned on the SOI substrate, wherein the active region comprises a gate region, a source region and a drain region which are respectively positioned at both sides of the gate region, a body region positioned under the gate region and a drift region positioned between the body region and the drain region; and the drift region comprises a lateral super-junction structure and a buffer layer positioned above the lateral super-junction structure. By arranging the buffer layer above the drift region, the invention can relieve the influence of the auxiliary depletion effect of the substrate on the charge balance in the SOI super-junction LDMOS drift region, improve the breakdown voltage of the device and greatly shallow the doping depth in the buffer layer manufacturing process, thereby reducing the impurity injection energy, facilitating the uniform distribution of impurities in the drift region and greatly lowering the process difficulty.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (LDMOS, LateralDouble-diffused MOSFET) device architecture, especially a kind of SOI super junction LDMOS device with resilient coating belongs to microelectronics and solid-state electronic techniques field.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit).Be primarily characterized in that to add one section relatively long light dope drift region between channel region and the drain region, this drift region doping type is consistent with drain terminal, by adding the drift region, can play the effect of sharing puncture voltage.
So-called super junction LDMOS is a kind of modified model LDMOS, and promptly the low-doped N type drift region of traditional LDMOST is replaced by one group of N type post district that alternately arranges and P type post district.In theory, if the electric charge between the P/N post district can perfect compensate, the drift region reaches fully and exhausts, then super junction LDMOS can obtain the puncture voltage higher than traditional LDMOS, highly doped N type post district then can obtain very low conducting resistance, therefore, super junction device can be obtained a good balance between puncture voltage and two key parameters of conducting resistance.But, owing to the existence of substrate-assisted depletion effect (substrate-assisted depletion effects), reduced the puncture voltage of super junction LDMOS device.
So-called substrate-assisted depletion effect is meant horizontal super knot owing to be subjected to the influence of longitudinal electric field, and the P/N post district of symmetry in the super knot can not be exhausted simultaneously fully, and its essence is that the charge balance between the P/N post district is broken.For the SOI substrate, because the back of the body grid effect of substrate, the electric charge of non-uniform Distribution is accumulated in the upper and lower interface place of oxygen buried layer and silicon under the effect of longitudinal electric field, strengthened the charge difference between the P/N post district, causes P/N post district to exhaust fully simultaneously under the puncture voltage that theory is calculated.
In order to solve the unbalance problem of P/N post district electric charge that the laterally super junction device of SOI brings owing to substrate-assisted depletion effect, it is that one deck resilient coating is introduced in the zone near oxygen buried layer below the drift region that a kind of solution is arranged, electric charge difference with between the compensation P/N post district reaches the purpose that exhausts fully between the P/N post district.
Yet,, must use thick film SOI (thickness t if need for design
Si＞1.5um), can alleviate the laterally substrate-assisted depletion effect of super junction device of SOI though then introduce resilient coating, but because resilient coating is positioned on the oxygen buried layer of below, drift region, when carrying out the ion injection, reach the injection degree of depth like this, it is very big not only to inject energy, and will accurately control its Impurity Distribution, and technology realizes very difficulty.
Given this, the present invention proposes a kind of novel SOI super junction LDMOS device and corresponding manufacture method, by the position of change resilient coating, thereby reduces its technology difficulty greatly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of SOI super junction LDMOS device with resilient coating, can alleviate the laterally substrate-assisted depletion effect of super junction device of SOI, and can reduce its technology difficulty greatly.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of SOI super junction LDMOS device with resilient coating comprises SOI substrate and the active area that is positioned on the described SOI substrate; Described active area comprises: grid region, the source region that lays respectively at both sides, described grid region and drain region, the drift region in the tagma under the described grid region, between described tagma and described drain region; It is characterized in that:
Described drift region comprises horizontal super-junction structure and is positioned at the resilient coating of described horizontal super-junction structure top.
As preferred version of the present invention, described horizontal super-junction structure comprises the N type post district and the P type post district of laterally alternately arranging.
As preferred version of the present invention, described resilient coating is the N type resilient coating of shallow doping.
As preferred version of the present invention, described resilient coating is positioned at the top layer of described drift region.
As preferred version of the present invention, this SOI super junction LDMOS device also comprises the body contact zone, and described body contact zone is positioned at side, described source region and contacts with described tagma.
As preferred version of the present invention, around described active area, be provided with groove isolation construction.
Described grid region comprises gate dielectric layer and the gate material layer that is positioned on the gate dielectric layer, and as preferred version of the present invention, described grid material is a polycrystalline silicon material.
As preferred version of the present invention, described surfaces of active regions is provided with protective layer.
Beneficial effect of the present invention is:
The present invention is on the basis of using for reference traditional super junction LDMOS resilient coating, by changing the position of resilient coating, it is shifted in the surface, drift region, can play the effect of the unnecessary electric charge that brings of compensation substrate-assisted depletion effect equally, the electric charge of drift region, top resilient coating is by from top to bottom progressively displacement, can compensate the unnecessary electric charge of oxygen buried layer top accumulation, as shown in Figure 1, and then can alleviate the influence of substrate-assisted depletion effect to SOI super junction LDMOS drift region charge balance, improve the puncture voltage of device.This novel resilient coating is owing to be in the top, drift region, and the degree of depth significantly shoals, and has not only reduced the injection energy of impurity, and the even distribution of easier realization drift region impurity, and technology difficulty reduces greatly.
Description of drawings
Fig. 1 is for having the principle schematic of the SOI super junction LDMOS device of resilient coating among the embodiment;
Fig. 2 is for having the schematic three dimensional views of the SOI super junction LDMOS device of resilient coating among the embodiment;
Fig. 3 is the domain of drift region P/N type post district and resilient coating among the embodiment;
Fig. 4 is for having the final encapsulating structure schematic diagram of the SOI super junction LDMOS device of resilient coating among the embodiment.
Wherein each description of reference numerals is as follows:
10, the bottom semiconductor of SOI substrate
11, the insulating buried layer of SOI substrate
21, gate material layer
22, gate dielectric layer
23, source region
24, drain region
25, tagma
26, horizontal super-junction structure
261, P type post district
262, N type post district
27, resilient coating
28, body contact zone
31, source electrode
32, grid
33, drain electrode
Embodiment
Further specify the present invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is not proportionally drawn.
By the further investigation to the super junction LDMOS device that adopts SOI (Silicon On Insulator) substrate, the present inventor finds to be provided with on the top layer, drift region the effect that resilient coating can play the unnecessary electric charge that the compensation substrate-assisted depletion effect brings.As shown in Figure 1, the electric charge (electronics shown in the figure) of drift region, top resilient coating can be by from top to bottom progressively displacement, thereby the unnecessary electric charge (hole shown in the figure) of compensation insulating buried layer top accumulation, and then can alleviate the influence of substrate-assisted depletion effect to SOI LDMOS drift region charge balance, improve the puncture voltage of device.Therefore, the inventor has proposed this SOI super junction LDMOS device that is provided with resilient coating on the top layer, drift region.
Fig. 2 is the structural representation of a preferred embodiment of this kind SOI super junction LDMOS device.This SOI super junction LDMOS device comprises SOI substrate and the active area that is positioned on the described SOI substrate; The SOI substrate is made up of bottom semiconductor 10, insulating buried layer 11 and top layer silicon; Described active area comprises: grid region, the source region 23 that lays respectively at both sides, described grid region and drain region 24, the drift region in the tagma under the described grid region 25, between described tagma 25 and described drain region 24; Described drift region comprises horizontal super-junction structure 26 and is positioned at the resilient coating 27 of described horizontal super-junction structure 26 tops.Described grid region comprises gate dielectric layer 22 and the gate material layer 21 that is positioned on the gate dielectric layer 22, and described gate dielectric layer 22 can be conventional gate oxide, and described gate material layer 21 is preferably polycrystalline silicon material.
Wherein, described horizontal super-junction structure 26 comprises the P type post district 261 and the N type post district 262 of laterally alternately arranging, and is used to share puncture voltage.The N type resilient coating that described resilient coating 27 is shallow doping.Usually, the super junction LDMOS device is a nmos device, when adopting the SOI substrate, because substrate-assisted depletion effect can accumulate unnecessary electric charge (hole) above insulating buried layer 11, so the N type resilient coating that adopts shallow doping can compensate the unnecessary electric charge that substrate-assisted depletion effect brings as resilient coating 27.
Wherein, the top that resilient coating 27 is positioned at described horizontal super-junction structure 26 gets final product, in the present embodiment preferably, described resilient coating 27 is arranged at the top layer of described drift region, when adopting the method for mixing to make resilient coating 27 like this, doping depth significantly shoals, and has not only reduced the injection energy of impurity, and the even distribution of easier realization drift region impurity.
In addition, because employing is the SOI substrate, this SOI super junction LDMOS device also comprises body contact zone 28, and described body contact zone 28 is positioned at 23 sides, described source region, contacts with described tagma 25, is used to draw the unnecessary electric charge that assemble in tagma 25, avoids floater effect.
Usually around described active area, can also be provided with groove isolation construction, thereby other device electricity in this SOI super junction LDMOS device and the integrated circuit are isolated.Be provided with protective layer in surfaces of active regions, for example silicon dioxide layer and silicon nitride passivation.On grid region, source region, drain region, be respectively equipped with source electrode 31, grid 32, drain electrode 33.Wherein, source electrode 31 is located on body contact zone 28 and source region 23 intersections.
The technology for preparing above-mentioned SOI super junction LDMOS device may further comprise the steps:
(1) adopts the SOI substrate, its top layer silicon is carried out ion inject, form the P type post district 261 and the N type post district 262 of laterally alternately arranging, as horizontal super-junction structure 26.Wherein, ion injects the degree of depth and the width that form N type post district 262 and P type post district 261 and equates that respectively P type post district 261 forms by implanted dopant boron, and N type post district 262 forms by implanted dopant phosphorus.
(2) the shallow Doping Phosphorus of low energy is carried out in whole drift region and inject, form resilient coating 27 on the top layer, drift region, as shown in Figure 3.
(3) utilize shallow trench isolation from (STI) fabrication techniques groove isolation construction, the part silicon materials that will comprise the drift region isolate, and these part silicon materials are used for the active area of fabricate devices.
(4) utilize thermal oxidation method to form one deck gate oxidation material on above-mentioned segregate part silicon materials surface.
(5) utilize repeatedly the ion injection mode that the part except that the drift region in the described part silicon materials is mixed, form the tagma 25 of P trap.
(6) deposit polysilicon, doping form the polysilicon gate material on the gate oxidation material, and produce grid region near an end of horizontal super-junction structure 26 by photoetching on P trap body area 25.The grid region is made of gate dielectric layer 22 (gate oxidation material) and gate material layer 21 (polysilicon gate material).
(7) in a side in described grid region, be infused in organizator contact zone 28 and source region 23 on the P trap body area 25 by ion.
(8) at the opposite side in described grid region, be infused in by ion that the end away from the grid region forms drain region 24 on the horizontal super-junction structure 26, thereby finish the making of active area, obtain the core texture of device.
Wherein, make tagma 25, grid region, source region 23, body contact zone 28 and drain region 24 and adopt conventional semiconductor technologies such as ion injection, etching, present embodiment only is a kind of preferred step method, and other variation also can be arranged when specifically making.Vertically arrange in the grid region and the drain region 24 that make, and laterally super-junction structure 26 is made up of the N type post district 262 and the P type post district 261 of laterally alternately arranging.
(9) adopt LTO (low temperature silicon dioxide) mode growthing silica, cover whole active area.
(10) on described silicon dioxide, etch window, depositing metal then, grid 32, source electrode 31, drain electrode 33 are drawn in photoetching.Source electrode 31 is located on body contact zone 28 and source region 23 intersections.
(11) last deposit silicon nitride generates passivation layer.
The device that obtains at last as shown in Figure 4.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and do not repeat them here.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (9)
1. the SOI super junction LDMOS device with resilient coating comprises SOI substrate and the active area that is positioned on the described SOI substrate; Described active area comprises: grid region, the source region that lays respectively at both sides, described grid region and drain region, the drift region in the tagma under the described grid region, between described tagma and described drain region; It is characterized in that:
Described drift region comprises horizontal super-junction structure and is positioned at the resilient coating of described horizontal super-junction structure top.
2. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: described horizontal super-junction structure comprises the N type post district and the P type post district of laterally alternately arranging.
3. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: described resilient coating is the N type resilient coating of shallow doping.
4. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: described resilient coating is positioned at the top layer of described drift region.
5. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: also comprise the body contact zone, described body contact zone is positioned at side, described source region and contacts with described tagma.
6. according to the described SOI super junction LDMOS device of claim 1, it is characterized in that: around described active area, be provided with groove isolation construction with resilient coating.
7. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: described grid region comprises gate dielectric layer and the gate material layer that is positioned on the gate dielectric layer.
8. according to the described SOI super junction LDMOS device with resilient coating of claim 7, it is characterized in that: described grid material is a polycrystalline silicon material.
9. according to the described SOI super junction LDMOS device with resilient coating of claim 1, it is characterized in that: described surfaces of active regions is provided with protective layer.
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| CN2010106195096A CN102130176B (en) | 2010-12-31 | 2010-12-31 | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832241A (en) * | 2012-09-14 | 2012-12-19 | 电子科技大学 | Gallium-nitride-base heterostructure field effect transistor with transverse p-n junction composite buffering layer structure |
| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN103745995A (en) * | 2013-12-31 | 2014-04-23 | 上海新傲科技股份有限公司 | Transverse power device with super junction structure and manufacturing method thereof |
| CN104733533A (en) * | 2015-03-13 | 2015-06-24 | 西安电子科技大学 | Covering type super-junction transverse double diffusion metal oxide semiconductor field effect transistor with N-type buried layer |
| CN104821335A (en) * | 2015-03-13 | 2015-08-05 | 西安后羿半导体科技有限公司 | N type buried layer cover type semi super junction transverse double diffusion metal oxide semiconductor field effect tube |
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| US20070290262A1 (en) * | 2006-06-16 | 2007-12-20 | Jun Cai | High voltage LDMOS |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
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2010
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6903421B1 (en) * | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
| US20070290262A1 (en) * | 2006-06-16 | 2007-12-20 | Jun Cai | High voltage LDMOS |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN103091533B (en) * | 2011-11-03 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN102832241A (en) * | 2012-09-14 | 2012-12-19 | 电子科技大学 | Gallium-nitride-base heterostructure field effect transistor with transverse p-n junction composite buffering layer structure |
| CN103745995A (en) * | 2013-12-31 | 2014-04-23 | 上海新傲科技股份有限公司 | Transverse power device with super junction structure and manufacturing method thereof |
| CN104733533A (en) * | 2015-03-13 | 2015-06-24 | 西安电子科技大学 | Covering type super-junction transverse double diffusion metal oxide semiconductor field effect transistor with N-type buried layer |
| CN104821335A (en) * | 2015-03-13 | 2015-08-05 | 西安后羿半导体科技有限公司 | N type buried layer cover type semi super junction transverse double diffusion metal oxide semiconductor field effect tube |
| CN104733533B (en) * | 2015-03-13 | 2018-02-27 | 西安电子科技大学 | N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor |
| CN104821335B (en) * | 2015-03-13 | 2018-03-02 | 西安华羿微电子股份有限公司 | The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of n type buried layer cover type half |
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