CN104733533B - N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor - Google Patents
N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor Download PDFInfo
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Abstract
The present invention discloses a kind of new SJ LDMOS devices, belongs to semiconductor power device technology field.The present invention introduces one layer of n type buried layer in traditional SJ LDMOS device structures, and the buried regions is located above super junction layer.Compared with traditional SJ LDMOS, the present invention has passed through the effect of n type buried layer, compensate for the charge unbalance between super junction NeiNXing Zhu areas and PXing Zhu areas, overcomes substrate secondary effects, improve breakdown voltage；Meanwhile n type buried layer additionally increases a new conductive path, conducting resistance is compared in reduction.It can be seen that the characteristics of structure is the balance of high-breakdown-voltage, low on-resistance and super junction layer charge.New SJ LDMOS devices structure provided by the invention also has the characteristics of manufacturing process is relatively easy, and technology difficulty is relatively low.The present invention is more easy to the application requirement for meeting power electronic system.
Description
Technical field
The present invention relates to semiconductor power device technology field, and in particular to is a kind of super-junction laterally double diffused metal oxidation
Thing semiconductor field.
Background technology
Lateral double diffusion metal oxide semiconductor FET (Lateral Double-diffused MOSFET, letter
Claim LDMOS) due to having the advantages that to be easy to integrate with low-voltage device, and turn into smart-power IC and system-on-chip designs
In Primary Component.Be primarily characterized in that between base and drain region add one section it is relatively long drift region is lightly doped, the drift
It is consistent with drain region to move the doping type in area, by adding drift region, can play a part of sharing breakdown voltage, improve
LDMOS breakdown voltage.LDMOS optimization aim is low conducting resistance, minimizes conduction loss.
Superjunction (super junction) structure is the NXing Zhu areas and PXing Zhu areas being alternately arranged, if with super-junction structure come
Substitute LDMOS drift region, be formed super junction LDMOS, abbreviation SJ-LDMOS.In theory, super-junction structure by NXing Zhu areas and
Charge balance between PXing Zhu areas can obtain high breakdown voltage, and can be with by the NXing Zhu areas of heavy doping and PXing Zhu areas
Very low conducting resistance is obtained, therefore, superjunction devices can obtain between two key parameters of breakdown voltage and conducting resistance
One compromise well.
But for SJ-LDMOS, due to substrate-assisted depletion NXing Zhu areas (HuoPXing Zhu areas) so that during device breakdown, P
Xing Zhu areas (HuoNXing Zhu areas) can not be completely depleted, breaks the charge balance between LiaoNXing Zhu areas and PXing Zhu areas, reduces SJ-
The lateral breakdown voltage of LDMOS device.
The content of the invention
The present invention proposes a kind of n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, changes
It has been apt to breakdown voltage and than the contradictory relation between conducting resistance, has realized high breakdown voltage and low ratio conducting resistance.
The present invention program is as follows：
N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, including：
P-type semiconductor substrate；
The adjacent p-type base on N-type epitaxy layer surface and super interface on the P-type semiconductor substrate；It is described
Super interface includes NXing Zhu areas and PXing Zhu areas；
Positioned at the N-type source region of p-type base part surface；
Positioned at the N-type drain region of super interface part surface；
It is characterized in that：
N-type doping buried regions is provided between the p-type base and N-type drain region, is covered in the table of super interface remaining part
Face.
Based on above scheme, the present invention also further makees following optimization：
Above-mentioned super interface is discharged using NXing Zhu areas and PXing Zhu areas transverse direction period distances, the width phase in each NXing Zhu areas
Together, the width in each PXing Zhu areas is identical.Further, each NXing Zhu areas are preferably also identical with the width in each PXing Zhu areas.
The cross section of above-mentioned n-type doping buried regions is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The longitudinal section of above-mentioned n-type doping buried regions is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The concentration of above-mentioned n-type doping buried regions is uniform (it is of course also possible to being heterogeneous).
Certainly, LDMOS of the invention can also be P-channel, then " P ", " N " relation pair of structure and above N-channel scheme
Adjust, that is, it is no longer superfluous herein to be changed to " N-type substrate ", " N-type base ", " p-type source region ", " p-type drain region ", " p-type buried dopant layer " ...
State.
Beneficial effects of the present invention are as follows：
By introducing one layer of n type buried layer in traditional SJ-LDMOS device architectures, the buried regions is located above super junction layer.
Compared with traditional SJ-LDMOS, the present invention by the effect of n type buried layer, compensate for super junction NeiNXing Zhu areas and PXing Zhu areas it
Between charge unbalance, overcome substrate secondary effects, improve breakdown voltage；Meanwhile n type buried layer additionally increase by one it is new
Conducting resistance is compared in conductive path, reduction.Therefore the optimization than in general scheme breakdown voltage and than conducting resistance can be entered
The lifting of one step.
This programme device is simple to manufacture, and operability is stronger.
Brief description of the drawings
Fig. 1 is n type buried layer cover type super-junction laterally double-diffusion metal oxide semiconductor field effect tube structure of the present invention
Schematic three dimensional views.
Fig. 2 is sectional view of the drift region along AOC directions in Fig. 1.
Embodiment
Referring to Fig. 1 and Fig. 2, below with a kind of n type buried layer cover type (N-channel) super-junction laterally bilateral diffusion metal oxide half
Specifically new construction in the embodiment of the present invention is introduced exemplified by conductor FET.Those skilled in the art should be realized that,
The embodiment is not limiting the scope of the invention.
The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of n type buried layer cover type half, it includes：
P-type semiconductor substrate 1；
The adjacent p-type base 2 on N-type epitaxy layer surface and super interface on the P-type semiconductor substrate 1；It is super
Level interface is using NXing Zhu areas 4 and the discharge of 5 horizontal period distances of PXing Zhu areas (simplification illustrates a cycle in figure), each N-type
The width in post area is identical, and the width in each PXing Zhu areas is identical；Further, the width in each NXing Zhu areas and each PXing Zhu areas
It is preferably also identical；
Positioned at the N-type source region 3 of the part surface of p-type base 2；
Positioned at the N-type drain region 6 of super interface part surface；
N-type doping buried regions 7 is provided between the p-type base and N-type drain region, is covered in the table of super interface remaining part
Face, i.e., as all areas in Fig. 1 between p-type base and N-type drain region are covered by n-type doping buried regions completely.
The preparation method of above-mentioned n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, its
Step includes：
P-type base is formed in the P-type semiconductor substrate upper epitaxial layer；
N-type source region is formed in the p-type base；
Super interface, including horizontal period distances are formed in the P-type semiconductor substrate and the adjacent position in p-type base
The NXing Zhu areas and PXing Zhu areas of discharge；
N type buried layer is formed on the super interface；
Heavily doped N-type drain region is formed on the n type buried layer and super interface.
Specific doping process, existing very ripe technology, will not be described in detail herein in the prior art.
Technical scheme, by the effect of n type buried layer, it compensate between super junction NeiNXing Zhu areas and PXing Zhu areas
Charge unbalance, overcome substrate secondary effects, improve breakdown voltage；Meanwhile n type buried layer additionally increases by one and new led
Conducting resistance is compared in power path, reduction.Hence improve LDMOS breakdown voltage and than the contradictory relation between conducting resistance, because
This is realizes that integrated technology provides a kind of new device architecture.
Claims (10)
1.N type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistors, including：
P-type semiconductor substrate；
The adjacent p-type base on N-type epitaxy layer surface and super interface on the P-type semiconductor substrate；It is described super
Interface includes NXing Zhu areas and PXing Zhu areas；
Positioned at the N-type source region of p-type base part surface；
Positioned at the N-type drain region of super interface part surface；
It is characterized in that：
N-type doping buried regions is provided between the p-type base and N-type drain region, is covered in the surface of super interface remaining part.
2. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The super interface is discharged using NXing Zhu areas and PXing Zhu areas transverse direction period distances, the width in each NXing Zhu areas
Identical, the width in each PXing Zhu areas is identical.
3. n type buried layer cover type super-junction laterally double-diffused metal oxide semiconductor field-effect according to claim 1 or 2
Pipe, it is characterised in that：The cross section and/or longitudinal section of the n-type doping buried regions are regular figure.
4. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 3,
It is characterized in that：The regular figure is circular or rectangle.
5. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The concentration of the n-type doping buried regions is uniform.
6.P type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistors, including：
N-type semiconductor substrate；
The adjacent N-type base of p-type epi-layer surface and super interface on the N-type semiconductor substrate；It is described super
Interface includes NXing Zhu areas and PXing Zhu areas；
Positioned at the p-type source region of N-type base part surface；
Positioned at the p-type drain region of super interface part surface；
It is characterized in that：
P-type buried dopant layer is provided between the N-type base and p-type drain region, is covered in the surface of super interface remaining part.
7. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 6,
It is characterized in that：The super interface is discharged using NXing Zhu areas and PXing Zhu areas transverse direction period distances, the width in each NXing Zhu areas
Identical, the width in each PXing Zhu areas is identical.
8. the p type buried layer cover type super-junction laterally double-diffused metal oxide semiconductor field-effect according to claim 6 or 7
Pipe, it is characterised in that：The cross section and/or longitudinal section of the p-type buried dopant layer are regular figure.
9. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 8,
It is characterized in that：The regular figure is circular or rectangle.
10. p type buried layer cover type super-junction laterally double-diffused metal oxide semiconductor field-effect according to claim 6
Pipe, it is characterised in that：The concentration of the p-type buried dopant layer is uniform.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130176A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer |
| CN104009090A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | Transverse double-diffusion metal oxide semiconductor field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7531888B2 (en) * | 2006-11-30 | 2009-05-12 | Fairchild Semiconductor Corporation | Integrated latch-up free insulated gate bipolar transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130176A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer |
| CN104009090A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | Transverse double-diffusion metal oxide semiconductor field effect transistor |
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