CN104124274A - Super junction lateral double diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Super junction lateral double diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN104124274A CN104124274A CN201410016374.2A CN201410016374A CN104124274A CN 104124274 A CN104124274 A CN 104124274A CN 201410016374 A CN201410016374 A CN 201410016374A CN 104124274 A CN104124274 A CN 104124274A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 238000002353 field-effect transistor method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000005669 field effect Effects 0.000 claims abstract description 11
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- 238000005265 energy consumption Methods 0.000 description 4
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention relates to the field of semiconductor devices and discloses a super junction lateral double diffusion metal oxide semiconductor (SJ-LDMOS) field effect transistor and a manufacturing method thereof. An active area of the SJ-LDMOS comprises a lateral super junction structure and a burying area formed below the lateral super junction structure. Due to the fact that the conduction types of the burying area and the semiconductor substrate are different, the semiconductor substrate and the burying area can assist depletion of an N-type column area and a P-type column area of the lateral super junction structure, load unbalance between the N-type column area and the P-type column area caused by the substrate auxiliary effect is supplemented, and high lateral breakdown voltage can be obtained. Meanwhile, a P junction and an N junction between the semiconductor substrate and the burying area lead a high electric field peak towards the surface of the semiconductor substrate and in the vertical direction, even lateral and vertical electric field distribution can be achieved through the electric field modulation effect, and higher lateral and vertical breakdown voltage can be obtained.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof.
Background technology
Lateral double diffusion metal oxide semiconductor field effect transistor (Lateral Double-diffused MOSFET, be called for short LDMOS) be easy to and the advantage such as low-voltage device is integrated owing to having, and become the Primary Component in smart-power IC and system-on-chip designs.Be primarily characterized in that the light dope drift region that adds a section relatively long between base and drain region, the doping type of this drift region is consistent with drain region, by adding drift region, can play the effect of sharing puncture voltage, has improved the puncture voltage of LDMOS.The optimization aim of LDMOS is low conducting resistance, and conduction loss is minimized.
Super knot (super junction) structure is alternative arrangement NXing Zhu district and P Xing Zhu district, if replace the drift region of LDMOS with super-junction structure, has just formed super junction LDMOS, is called for short SJ-LDMOS.In theory, super-junction structure can obtain high puncture voltage by the charge balance between NXing Zhu district and P Xing Zhu district, and can obtain very low conducting resistance by heavily doped NXing Zhu district and P Xing Zhu district, therefore, super junction device can be obtained good trading off between puncture voltage and two key parameters of conducting resistance.
But for SJ-LDMOS, due to substrate-assisted depletion N-type post (or P type post), while making device breakdown, P type post (or N-type post) can not exhaust completely, break the charge balance between LiaoNXing Zhu district and P Xing Zhu district, reduced the lateral breakdown voltage of SJ-LDMOS device.
Summary of the invention
The invention provides a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof, reduce the problem of the lateral breakdown voltage of SJ-LDMOS in order to solve substrate-assisted depletion effect, and further improved the horizontal and vertical puncture voltage of device.
For solving the problems of the technologies described above, the invention provides a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, comprise the Semiconductor substrate and the active area and the grid region that are formed on described semiconductor substrate surface of the first conduction type, described active area comprises:
The base of the first conduction type;
The source region of the second conduction type, is formed in described base;
The drain region of the second conduction type, described source region and drain region are positioned at the both sides in described grid region;
Laterally super-junction structure, comprises horizontal alternative arrangement NXing Zhu district and P Xing Zhu district, between described base and drain region, wherein,
Described active area also comprises the buried district of the second conduction type, is formed in described Semiconductor substrate, and is positioned at the below of described horizontal super-junction structure.
The present invention also provides a kind of manufacture method of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor as above, the surface that is included in the Semiconductor substrate of one first conduction type is formed with the step in source region and grid region, described in be formed with source region step comprise:
In described Semiconductor substrate, form the base of the first conduction type;
In described base, form the source region of the second conduction type;
The drain region that forms the second conduction type in described Semiconductor substrate, described source region and drain region are positioned at the both sides in described grid region;
Between described tagma and drain region, form horizontal super-junction structure, described horizontal super-junction structure comprises horizontal alternative arrangement NXing Zhu district and P Xing Zhu district, wherein,
The described step that is formed with source region also comprises:
The buried district that forms the second conduction type in described Semiconductor substrate, described buried district is positioned at the below of described horizontal super-junction structure.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, by form the buried district different from Semiconductor substrate conduction type below horizontal super-junction structure, thereby Semiconductor substrate and buried district be assisted depletion horizontal super-junction structure NXing Zhu district and P Xing Zhu district simultaneously, compensate substrate secondary effects and caused the charge unbalance between NXing Zhu district and P Xing Zhu district, can obtain higher lateral breakdown voltage.Simultaneously, PN junction between Semiconductor substrate and buried district has respectively been introduced a high electric field peak to surface and the longitudinal direction of Semiconductor substrate, can obtain horizontal and vertical Electric Field Distribution more uniformly by Electric Field Modulation, thereby can obtain higher horizontal and vertical puncture voltage.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 represents the 3-D view of SJ-LDMOS structure in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
Embodiment mono-
As shown in Figure 1, the invention provides a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, be called for short SJ-LDMOS, active area and grid region 2 that it comprises P type semiconductor substrate 7 and is formed on Semiconductor substrate 7 surfaces.Active area comprises N-type source region 1, N-type drain region 5, P type base 8 and horizontal super-junction structure.Wherein, base 8 is as the raceway groove of metal-oxide-semiconductor, and source region 1 is formed in base 8, and source region 1 and drain region 5 are positioned at the both sides in grid region 2.Laterally super-junction structure comprises horizontal alternative arrangement NXing Zhu district 3 and P Xing Zhu district 4, and heavily doped NXing Zhu district 3 and P Xing Zhu district 4 have reduced the conducting resistance of SJ-LDMOS, and conduction loss is minimized.
In the present invention, the active area of SJ-LDMOS also comprises N-type buried district 6, is formed in Semiconductor substrate 7, and is positioned at the below of described horizontal super-junction structure.By the different Semiconductor substrate of conduction type 7 buried districts 6 are set, the horizontal super-junction structure NXing Zhu of assisted depletion district 3 and P Xing Zhu district 4 simultaneously, compensate substrate secondary effects and caused the charge unbalance between NXing Zhu district 3 and P Xing Zhu district 4, can obtain higher lateral breakdown voltage.Simultaneously, PN junction between Semiconductor substrate 7 and buried district 6 has been introduced a high electric field peak to surface and the longitudinal direction of Semiconductor substrate 7, can obtain horizontal and vertical Electric Field Distribution more uniformly by Electric Field Modulation, thereby can obtain higher horizontal and vertical puncture voltage, greatly improve the performance of SJ-LDMOS.
Operation principle of the present invention is:
For traditional SJ-LDMOS, due to super-junction structure NXing Zhu district 3 described in P type semiconductor substrate 7 assisted depletions, while making device reach critical puncturing, P Xing Zhu district 4 can not exhaust completely, thereby its withstand voltage is lower.And when in the present invention, the P type semiconductor substrate 7 above N-type buried district 6 exhausts, majority carrier in N-type buried district 6 is brought into play its effect, auxiliary P Xing Zhu district 4 exhausts, thereby has overcome the substrate secondary effects in SJ-LDMOS device, has obtained higher breakdown voltage value.Secondly, the PN junction between P type semiconductor substrate 7 and N-type buried district 6 has been introduced a high electric field peak to the surface of Semiconductor substrate 7, and it can obtain a more uniform Electric Field Distribution by Electric Field Modulation, thereby can obtain higher lateral voltage.
It should be noted that, for convenience of description, in the present invention, define surperficial bearing of trend that Semiconductor substrate is formed with active area and grid region for laterally.
Wherein, the top of buried district 6 is less than several microns to the distance of described horizontal super-junction structure below.The cross section of buried district 6 and longitudinal section can be regular figure, as square, circular.
Further, buried district 6 in the present embodiment arranges near drain region 5, because the PN junction between Semiconductor substrate 7 and buried district 6 has reduced the high peak electric field of body internal electric field, the new high peak electric field producing is by the distribution of modulation body internal electric field, can reduce the bulk electric field near drain region 5, improve longitudinal puncture voltage of SJ-LDMOS, further improve the performance of SJ-LDMOS.
In actual process process, the Implantation while making buried district 6 is high energy consumption, and structure and the concentration of super knot are exerted an influence.For solving the problems of the technologies described above, the step that forms buried district in the present embodiment comprises:
In described Semiconductor substrate, form N-type region;
Surface in described N-type region forms lightly doped epitaxial loayer.
Can reduce the energy consumption of Implantation by above-mentioned steps, and reduce the super structure of tying and the impact of concentration.Wherein, the conduction type of described epitaxial loayer is P type.
Further, the width that buried district 6 is set is less than the width of horizontal super-junction structure, and the width here refers to buried district 6 and the length of horizontal super-junction structure from the side near source region 1 to the side near drain region 5.
It should be noted that: buried district 6, to the distance of above-mentioned super-junction structure bottom and 5 bottoms, drain region, needs according to the requirement of concrete SJ-LDMOS breakdown characteristics, on state characteristic and intrinsic body diode is specifically set; Doping content, length, thickness and the width of buried district 6, also can be according to the requirement of concrete SJ-LDMOS breakdown characteristics, on state characteristic and intrinsic body diode is specifically set.
Doping content, length, thickness and the width in described super-junction structure NXing Zhu district and P Xing Zhu district, can be according to the requirement of concrete SJ-LDMOS breakdown characteristics, on state characteristic and intrinsic body diode is specifically set; Quantity and the arrangement mode in described super-junction structure NXing Zhu district and P Xing Zhu district, can be according to the requirement of concrete SJ-LDMOS breakdown characteristics, on state characteristic and intrinsic body diode is specifically set.
Technical scheme of the present invention by forming the buried district different from Semiconductor substrate conduction type below horizontal super-junction structure, thereby Semiconductor substrate and buried district be assisted depletion horizontal super-junction structure NXing Zhu district and P Xing Zhu district simultaneously, compensate substrate secondary effects and caused the charge unbalance between NXing Zhu district and P Xing Zhu district, can obtain higher lateral breakdown voltage.Simultaneously, PN junction between Semiconductor substrate and buried district has respectively been introduced a high electric field peak to surface and the longitudinal direction of Semiconductor substrate, can obtain more uniform horizontal and vertical Electric Field Distribution by Electric Field Modulation, thereby can obtain higher horizontal and vertical puncture voltage.
Embodiment bis-
Based on same inventive concept, the present invention also provides the method for the SJ-LDMOS in a kind of embodiment of making mono-, and the surface that is included in the Semiconductor substrate of one first conduction type is formed with the step in source region and grid region, described in be formed with source region step comprise:
In described Semiconductor substrate, form the base of the first conduction type;
In described base, form the source region of the second conduction type;
The drain region that forms the second conduction type in described Semiconductor substrate, described source region and drain region are positioned at the both sides in described grid region;
Between described base and drain region, form, described horizontal super-junction structure comprises horizontal alternative arrangement NXing Zhu district and P Xing Zhu district.
The described step that is formed with source region also comprises:
The buried district that forms the second conduction type in described Semiconductor substrate, described buried district is positioned at the below of described horizontal super-junction structure.
Pass through above-mentioned steps, below horizontal super-junction structure, form the buried district different from Semiconductor substrate conduction type, thereby Semiconductor substrate and buried district be assisted depletion horizontal super-junction structure NXing Zhu district and P Xing Zhu district simultaneously, compensate substrate secondary effects and caused the charge unbalance between NXing Zhu district and P Xing Zhu district, can obtain higher lateral breakdown voltage.Simultaneously, PN junction between Semiconductor substrate and buried district has respectively been introduced a high electric field peak to surface and the longitudinal direction of Semiconductor substrate, it can obtain more uniform horizontal and vertical Electric Field Distribution by Electric Field Modulation, thereby can obtain higher horizontal and vertical puncture voltage.
Preferably, form described buried district in the position near described drain region.Because the PN junction between Semiconductor substrate and buried district has reduced the high peak electric field of body internal electric field, the new high peak electric field producing is by the distribution of modulation body internal electric field, can reduce the bulk electric field near drain region, improve longitudinal puncture voltage of SJ-LDMOS, further improve the performance of SJ-LDMOS.
Further, in order to reduce the energy consumption of making Implantation when buried district, and reduce structure and the concentration of super knot are exerted an influence, the step that forms buried district in the present embodiment comprises:
In described Semiconductor substrate, form the region of the second conduction type;
Surface in the region of described the second conduction type forms lightly doped epitaxial loayer.
The energy consumption when buried district forming by above-mentioned steps can reduce Implantation, and reduce the super structure of tying and the impact of concentration.
Wherein, the type of described epitaxial loayer is the first conduction type.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the technology of the present invention principle; can also make some improvement and replacement, these improvement and replacement also should be considered as protection scope of the present invention.
Claims (8)
1. a super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, comprises the Semiconductor substrate of the first conduction type and is formed on active area and the grid region of described semiconductor substrate surface, and described active area comprises:
The base of the first conduction type;
The source region of the second conduction type, is formed in described base;
The drain region of the second conduction type, described source region and drain region are positioned at the both sides in described grid region;
Laterally super-junction structure, comprises horizontal alternative arrangement NXing Zhu district and P Xing Zhu district, between described base and drain region, it is characterized in that,
Described active area also comprises the buried district of the second conduction type, is formed in described Semiconductor substrate, and is positioned at the below of described horizontal super-junction structure.
2. super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1, is characterized in that, described buried district arranges near described drain region.
3. super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1, is characterized in that, the width of described buried district is less than the width of horizontal super-junction structure.
4. according to the super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor described in claim 1-3 any one, it is characterized in that, the cross section of described buried district is regular figure.
5. according to the super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor described in claim 1-3 any one, it is characterized in that, the longitudinal section of described buried district is regular figure.
6. the manufacture method of the super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor as described in claim 1-5 any one, the surface that is included in the Semiconductor substrate of one first conduction type is formed with the step in source region and grid region, described in be formed with source region step comprise:
In described Semiconductor substrate, form the base of the first conduction type;
In described base, form the source region of the second conduction type;
The drain region that forms the second conduction type in described Semiconductor substrate, described source region and drain region are positioned at the both sides in described grid region;
Between described base and drain region, form horizontal super-junction structure, described horizontal super-junction structure comprises horizontal alternative arrangement NXing Zhu district and P Xing Zhu district, it is characterized in that,
The described step that is formed with source region also comprises:
The buried district that forms the second conduction type in described Semiconductor substrate, described buried district is positioned at the below of described horizontal super-junction structure.
7. manufacture method according to claim 6, is characterized in that, forms described buried district in the position near described drain region.
8. manufacture method according to claim 6, is characterized in that, the step that forms the buried district of the second conduction type in described Semiconductor substrate comprises:
In described Semiconductor substrate, form the region of the second conduction type;
Form the lightly doped epitaxial loayer of the first conduction type on the surface in the region of described the second conduction type.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835836A (en) * | 2015-05-22 | 2015-08-12 | 西安电子科技大学 | Super-junction LDMOS (laterally double-diffused metal-oxide semiconductor) field effect transistor with double-electric-field modulation |
| CN106169503A (en) * | 2015-05-19 | 2016-11-30 | 飞思卡尔半导体公司 | There is semiconductor device and the manufacture method thereof of vertical float ring |
| CN106601785A (en) * | 2015-10-16 | 2017-04-26 | 立锜科技股份有限公司 | High-side power device and manufacturing method thereof |
| CN107359195A (en) * | 2017-07-31 | 2017-11-17 | 电子科技大学 | A kind of high withstand voltage transverse direction superjunction devices |
| CN107768424A (en) * | 2017-09-11 | 2018-03-06 | 西安电子科技大学 | A kind of wide band gap semiconducter transverse direction superjunction double-diffused transistor with polycyclic Electric Field Modulated substrate |
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| CN108767013A (en) * | 2018-06-05 | 2018-11-06 | 电子科技大学 | A kind of SJ-LDMOS devices with part buried layer |
| CN110021655A (en) * | 2019-04-19 | 2019-07-16 | 西安电子科技大学 | A kind of half super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor with ladder N-type heavy doping buried layer |
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