CN203242638U

CN203242638U - Lateral diffusion type low on-resistance metal oxide semiconductor (MOS) device

Info

Publication number: CN203242638U
Application number: CN 201320225402
Authority: CN
Inventors: 陈伟元
Original assignee: Suzhou Vocational University
Current assignee: Suzhou Vocational University
Priority date: 2013-04-28
Filing date: 2013-04-28
Publication date: 2013-10-16
Anticipated expiration: 2023-04-28

Abstract

The utility model discloses a lateral diffusion type low on-resistance MOS device. The lateral diffusion type low on-resistance MOS device comprises a P-type trap layer and an N-type light dope layer which are located in a P-type substrate layer, a grid region is arranged on a gate-oxide layer, and at least two grooves are arranged at the upper part of the P-type trap layer and between a source region and the N-type light dope layer. The etching depth of the groove close to the source region is less than the etching depth the groove close to the N-type light dope layer, and the etching depths of the plurality of grooves are increased orderly from the source region to the N-type light dope layer. A P-type light dope region is arranged in the N-type light dope layer, and is located in the middle regions in the horizontal and vertical directions of the N-type light dope layer. By the above mode, the lateral diffusion type low on-resistance MOS device of the utility model enables the breakdown resistant voltage, the response time and the frequency characteristic to be improved, the on-resistance and the volume to be reduced, and the overall performance to be optimized.

Description

Horizontal proliferation type low on-resistance MOS device

Technical field

The utility model relates to a kind of MOS device, particularly relates to a kind of horizontal proliferation type low on-resistance MOS device.

Background technology

Metal oxide MOS semiconductor device, along with the fast development of semicon industry, the power electronic technology take large power semiconductor device as representative develops rapidly, and application constantly enlarges, such as the control of alternating current machine, printer driver circuit.In various power devices now, it is high that laterally diffused MOS semiconductor device LDMOS has operating voltage, and technique is relatively simple, so LDMOS has vast potential for future development.In the LDMOS designs, puncture voltage and conducting resistance always are the main target of paying close attention to when people design such devices, and the length of the thickness of epitaxial loayer, doping content, drift region is the most important parameter of LDMOS.The length that can pass through to increase the drift region is with the raising puncture voltage, but this can increase chip area and conducting resistance.Withstand voltage and conducting resistance is contradiction for the concentration of epitaxial loayer and the requirement of thickness.High puncture voltage requires thick light dope epitaxial loayer and long drift region, low conducting resistance then requires thin heavy doping epitaxial loayer and short drift region, therefore must select best extension parameter and drift region length, so that under the prerequisite that satisfies certain source drain breakdown voltage, obtain minimum conducting resistance.RESURF(RESURF principle) be widely used in the design of high tension apparatus, this principle requires drift region charge and substrate electric charge to reach charge balance always, can bear when accomplishing that the drift region exhausts fully higher withstand voltage.

Demand for development along with device miniaturization, the chip area that existing LDMOS design occupies is larger, this is unfavorable for itself and other integrated volume that further reduces of function element, thereby expanded application scope, therefore, how to design a kind of surface area that can effectively reduce the shared silicon chip of existing LDMOS, and can further improve performance of devices, become technology barrier.

Summary of the invention

The technical problem that the utility model mainly solves provides a kind of horizontal proliferation type low on-resistance MOS device, can improve breakdown voltage resistant and reduced the device conduction resistance, greatly improved simultaneously response time and the frequency characteristic of device, the optimization and the volume that are beneficial to the device overall performance reduce.

For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of horizontal proliferation type low on-resistance MOS device is provided, comprise: the P type trap layer and the N-type lightly-doped layer that are positioned at the substrate layer of P type, consist of a PN junction thereby described P type trap layer and N-type lightly-doped layer are adjacent in the horizontal direction, the one source pole district is positioned at described P type trap floor, one drain region is positioned at described substrate layer, be provided with grid oxide layer above the P type trap layer in zone between described source area and the N-type lightly-doped layer, this grid oxide layer top is provided with a gate regions; It is characterized in that: between described source area and the N-type lightly-doped layer and be positioned at P type trap layer top and have at least two grooves, the groove etching depth of close source area is less than the groove etching depth near described N-type lightly-doped layer, and the etching depth of several described grooves is increased successively by source area to N-type lightly-doped layer direction; Have a P type light doping section in the described N-type lightly-doped layer, this P type light doping section is positioned at the zone line of N-type lightly-doped layer horizontal direction, and this P type light doping section is positioned at the central region of N-type lightly-doped layer vertical direction;

Preferably, the etching depth of described groove be the source area junction depth 1/3 ~ 1/4 between, groove etching depth near described source area is 1/3 ~ 1/3.5 of source area junction depth, and the groove etching depth of close described N-type lightly-doped layer is 1/3.5 ~ 1/4 of source area junction depth.

The beneficial effects of the utility model are: a kind of horizontal proliferation type of the utility model low on-resistance MOS device, can improve breakdown voltage resistant and reduced the device conduction resistance, greatly improved simultaneously response time and the frequency characteristic of device, the optimization and the volume that are beneficial to the device overall performance reduce.

Description of drawings

Fig. 1 is the structural representation one of the utility model horizontal proliferation type low on-resistance MOS device;

Fig. 2 is the partial enlarged drawing of the utility model horizontal proliferation type low on-resistance MOS device;

Fig. 3 is the structural representation two of the utility model horizontal proliferation type low on-resistance MOS device.

Embodiment

Preferred embodiment is described in detail to the utility model below in conjunction with accompanying drawing, thereby so that the advantage of utility model and feature can be easier to be it will be appreciated by those skilled in the art that protection range of the present utility model is made more explicit defining.

See also Fig. 1 to Fig. 3, the utility model embodiment comprises:

Embodiment 1: a kind of horizontal proliferation type low on-resistance MOS device, comprise: the P type trap layer 2 and the N-type lightly-doped layer 3 that are positioned at the substrate layer 1 of P type, consist of a PN junction thereby described P type trap layer 2 and N-type lightly-doped layer 3 are adjacent in the horizontal direction, one source pole district 4 is positioned at described P type trap floor 2, one drain region 5 is positioned at described substrate layer 1, be provided with grid oxide layer 7 above the P type trap layer 2 in zone between described source area 4 and the N-type lightly-doped layer 3, these grid oxide layer 7 tops are provided with a gate regions 8; Between described source area 4 and the N-type lightly-doped layer 3 and be positioned at P type trap layer 2 top and have at least two grooves 9, groove 9 etching depths of close source area 4 are less than groove 9 etching depths near described N-type lightly-doped layer 3, and the etching depth of several described grooves 9 is increased successively by source area 4 to N-type lightly-doped layer 3 directions;

Has a P type light doping section 6 in the described N-type lightly-doped layer 3, this P type light doping section 6 is positioned at the zone line of N-type lightly-doped layer 3 horizontal directions, this P type light doping section 6 is positioned at the central region of N-type lightly-doped layer 3 vertical direction, and the doping content of N-type lightly-doped layer 3 is greater than the doping content of P type light doping section 6.

The etching depth of above-mentioned groove be source area 4 junction depths 1/3.5 between, be 1/3.2 of source area 4 junction depths near groove 9 etching depths of described source area 4, be 1/3.8 of source area 4 junction depths near groove 9 etching depths of described N-type lightly-doped layer 3.

The side wall district 10 of above-mentioned groove 9 and the doping content in crown wall district 11 equate, and be the bottom zone 12 of groove 9 mix concentration 88 ~ 90% between; Above-mentioned N-type lightly-doped layer 3 with the doping content ratio of P type light doping section 6 is: 1:0.82.

The junction depth ratio of above-mentioned P type trap layer 2 and N-type lightly-doped layer 3 is 2:1; Above-mentioned N-type lightly-doped layer 3 is between described drain region 5 and described P type trap layer 2.

Embodiment 2: a kind of horizontal proliferation type low on-resistance MOS device, comprise: the P type trap layer 2 and the N-type lightly-doped layer 3 that are positioned at the substrate layer 1 of P type, consist of a PN junction thereby described P type trap layer 2 and N-type lightly-doped layer 3 are adjacent in the horizontal direction, one source pole district 4 is positioned at described P type trap floor 2, one drain region 5 is positioned at described substrate layer 1, be provided with grid oxide layer 7 above the P type trap layer 2 in zone between described source area 4 and the N-type lightly-doped layer 3, these grid oxide layer 7 tops are provided with a gate regions 8; Between described source area 4 and the N-type lightly-doped layer 3 and be positioned at P type trap layer 2 top and have at least two grooves 9, groove 9 etching depths of close source area 4 are less than groove 9 etching depths near described N-type lightly-doped layer 3, and the etching depth of several described grooves 9 is increased successively by source area 4 to N-type lightly-doped layer 3 directions;

The etching depth of above-mentioned groove be source area 4 junction depths 1/3.8 between, be 1/3.4 of source area 4 junction depths near groove 9 etching depths of described source area 4, be 1/3.6 of source area 4 junction depths near groove 9 etching depths of described N-type lightly-doped layer 3.

The side wall district 10 of above-mentioned groove 9 and the doping content in crown wall district 11 equate, and be the bottom zone 12 of groove 9 mix concentration 92 ~ 93% between; Above-mentioned N-type lightly-doped layer 3 with the doping content ratio of P type light doping section 6 is: 1:0.88.

The junction depth ratio of above-mentioned P type trap layer 2 and N-type lightly-doped layer 3 is 2:1; Above-mentioned drain region 5 is positioned at described N-type lightly-doped layer 3.

The utility model horizontal proliferation type low on-resistance MOS device, channel region has at least two grooves, gully density is doubled, improved grid width, can improve breakdown voltage resistant and reduced the device conduction resistance, greatly improved simultaneously response time and the frequency characteristic of device, the optimization and the volume that are beneficial to the device overall performance reduce.

In several grooves of its channel region between source area and the N-type lightly-doped layer and be positioned at P type trap layer top and have at least two grooves, the groove etching depth of close source area is less than the groove etching depth near described N-type lightly-doped layer, and the etching depth of several described grooves is increased successively by source area to N-type lightly-doped layer direction, response time and the frequency characteristic of device had both been improved, also can improve simultaneously the concentration of channel region P type trap layer, reduce conducting resistance and device power consumption in off position.

The side wall district of its groove and the doping content in crown wall district equate, can effectively avoid the diffusion of side wall district, crown wall district doping ion, have realized the long parametric stability of device performance; Secondly, the doping content in side wall district and crown wall district has overcome the impact of grid width less than the doping content of the bottom zone of groove, has guaranteed the little opening time of device, the conducting resistance when having reduced high frequency and switching loss.

Have a P type light doping section in the described N-type lightly-doped layer, the doping content of N-type lightly-doped layer has reduced gate leakage capacitance Cgd greater than the doping content of P type light doping section through emulation testing, has improved cut-off frequency, has further reduced conduction resistance.

The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model specification and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.

Claims

1. horizontal proliferation type low on-resistance MOS device, comprise: the P type trap layer and the N-type lightly-doped layer that are positioned at the substrate layer of P type, consist of a PN junction thereby described P type trap layer and N-type lightly-doped layer are adjacent in the horizontal direction, the one source pole district is positioned at described P type trap floor, one drain region is positioned at described substrate layer, be provided with grid oxide layer above the P type trap layer in zone between described source area and the N-type lightly-doped layer, this grid oxide layer top is provided with a gate regions; It is characterized in that: between described source area and the N-type lightly-doped layer and be positioned at P type trap layer top and have at least two grooves, the groove etching depth of close source area is less than the groove etching depth near described N-type lightly-doped layer, and the etching depth of several described grooves is increased successively by source area to N-type lightly-doped layer direction; Have a P type light doping section in the described N-type lightly-doped layer, this P type light doping section is positioned at the zone line of N-type lightly-doped layer horizontal direction, and this P type light doping section is positioned at the central region of N-type lightly-doped layer vertical direction.

2. horizontal proliferation type low on-resistance MOS device according to claim 1, it is characterized in that: the etching depth of described groove be the source area junction depth 1/3 ~ 1/4 between, groove etching depth near described source area is 1/3 ~ 1/3.5 of source area junction depth, and the groove etching depth of close described N-type lightly-doped layer is 1/3.5 ~ 1/4 of source area junction depth.