CN202454560U - Trench MOSFET device - Google Patents
Trench MOSFET device Download PDFInfo
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- CN202454560U CN202454560U CN2011205357642U CN201120535764U CN202454560U CN 202454560 U CN202454560 U CN 202454560U CN 2011205357642 U CN2011205357642 U CN 2011205357642U CN 201120535764 U CN201120535764 U CN 201120535764U CN 202454560 U CN202454560 U CN 202454560U
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- Prior art keywords
- groove
- epitaxial loayer
- insulating barrier
- tagma
- covered
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 230000005669 field effect Effects 0.000 claims abstract description 16
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims description 41
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 210000000746 body region Anatomy 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
A trench mosfet device is disclosed. The device includes: a substrate; an epitaxial layer; a trench; a first insulating layer covering an inner surface of a lower portion of the trench; a second insulating layer covering an upper portion of an inner surface of the trench and the first insulating layer, wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer; the polycrystalline silicon region is positioned in the groove, the lower surface of the polycrystalline silicon region is covered by the first insulating layer, and the side wall of the polycrystalline silicon region is covered by the first insulating layer or the second insulating layer; a gate electrode whose sidewall and lower surface are covered with the second insulating layer; the at least one columnar structure is positioned in the epitaxial layer, and the side wall and the lower surface of the columnar structure are covered by the epitaxial layer, wherein the at least one columnar structure is longitudinally arranged along the epitaxial layer; a body region; a heavily doped region and a source. The utility model provides a slot metal oxide semiconductor field effect transistor device can improve breakdown voltage and reduce on-resistance.
Description
Technical field
The embodiment of the utility model relates to semiconductor device, and more specifically, the embodiment of the utility model relates to the groove metal oxide semiconductor field effect transistor device.
Background technology
At present, power device is widely used in fields such as Switching Power Supply, automotive electronics, Industry Control.Groove metal oxide semiconductor field effect transistor (Trench-gate MOSFET) has been owing to improved the raceway groove overall width in the unit are chip, thereby reduced drain-source conducting resistance Rds (on) and be used widely.Yet; In traditional groove MOSFET device; The problem that has mutual restriction between puncture voltage BV and the conducting resistance Rds (on); Improve puncture voltage BV and often can not realize simultaneously with reduction conducting resistance Rds (on), this has very big energy loss when just causing device under big voltage, to be worked.
The utility model content
To one or more problems of the prior art, the purpose of the utility model provides a kind of groove metal oxide semiconductor field effect transistor device, comprising: the substrate of first conduction type; The epitaxial loayer of first conduction type is positioned on the said substrate, and its doping content is less than the doping content of said substrate; Groove vertically extend to the lower surface of said epitaxial loayer from the upper surface of said epitaxial loayer, and it does not contact the surface of said substrate; First insulating barrier is positioned at said groove, and covers the lower part inner surface of said groove; Second insulating barrier is positioned at said groove, and covers the top inner surface and said first insulating barrier of said groove, and wherein, the thickness of said second insulating barrier is less than the thickness of said first insulating barrier; Polysilicon region is positioned at said groove, and lower surface covered by said first insulating barrier, and its sidewall is covered by said first insulating barrier or second insulating barrier; Grid is positioned at said groove, vertically extend to the lower surface of said epitaxial loayer from the upper surface of said epitaxial loayer, and its sidewall and lower surface is covered by said second insulating barrier; The column structure of at least one second conduction type is positioned at said epitaxial loayer, and its sidewall and lower surface covered by said epitaxial loayer, and wherein, the column structure of said at least one second conduction type is vertically arranged along epitaxial loayer; The tagma of second conduction type; The adjacent wall of its sidewall and said groove contacts; And less than the distance of grid lower surface apart from the epitaxial loayer upper surface, wherein, the doping content in said tagma is greater than the doping content of said column structure apart from the distance of epitaxial loayer upper surface for the lower surface in tagma; The heavily doped region of first conduction type, it is positioned at said tagma and adjacent with the adjacent wall of said groove, and its doping content is greater than the doping content of said epitaxial loayer; And source electrode, it is positioned at said tagma, vertically extends to said tagma from the upper surface of said epitaxial loayer, and contacts with the heavily doped region of first conduction type.
According to the groove metal oxide semiconductor field effect transistor device that the utility model proposes, can improve puncture voltage and reduce conducting resistance.
Description of drawings
Following accompanying drawing has shown the execution mode of the utility model.These accompanying drawings and execution mode provide some embodiment of the utility model with the mode of non-limiting, non exhaustive property, wherein:
Fig. 1 schematically shows the N raceway groove groove MOSFET device according to the utility model one embodiment;
Fig. 2 schematically shows the N raceway groove groove MOSFET device according to the utility model one preferred embodiment;
Fig. 3 schematically shows the N raceway groove groove MOSFET device according to another embodiment of the utility model;
Fig. 4 schematically shows the N raceway groove groove MOSFET device according to another embodiment of the utility model;
Fig. 5 schematically shows the N raceway groove groove MOSFET device according to another embodiment of the utility model; And
Fig. 6 schematically shows in the manufacturing, according to the N raceway groove groove MOSFET device with a plurality of repetitives of the utility model embodiment.
Embodiment
Below will the utility model be described in more detail with reference to accompanying drawing.In each accompanying drawing, components identical adopts similar Reference numeral to represent.For the sake of clarity, the various piece in the accompanying drawing is not drawn in proportion.
Specify the novel groove MOSFET device of the utility model embodiment below.In ensuing explanation, some concrete details, for example the concrete doping type among the embodiment all is used for to the embodiment of the utility model better understanding being provided.Even the technical staff in present technique field is appreciated that the embodiment of the utility model also can be implemented under the situation that lacks combinations such as some details or additive method, material.
For reducing the contradiction between puncture voltage BV and the conducting resistance Rds (on); The utility model provides a kind of novel groove metal oxide semiconductor field effect transistor (MOSFET) device, it comprises that ultra knot (super junction) structure and capacitive exhaust (capacitively depleted) structure.Utilize this to comprise that super-junction structure and capacitive exhaust the groove MOSFET device of structure, can effectively reduce the contradiction between puncture voltage BV and the conducting resistance Rds (on), improve device performance.
In ensuing description, be example with N raceway groove groove MOSFET device, its structure and performance are described in detail.Yet, it will be appreciated by those skilled in the art that said structure and performance are equally applicable to P raceway groove groove MOSFET device, to state for avoiding tired, the utility model is not described in detail.
Fig. 1 illustrates the N raceway groove groove MOSFET device according to the utility model one embodiment.As shown in Figure 1, said N raceway groove groove MOSFET device comprises N
+Substrate 100 and be formed at N
+N on the substrate 100
-Epitaxial loayer 101.This N raceway groove groove MOSFET device also comprises groove 102, and it is from said N
-The upper surface of epitaxial loayer 101 extends to said N vertically downward
+ Substrate 100 tops, and it does not contact said N
+The surface of substrate 100.Comprise first insulating barrier 103 and second insulating barrier 109 in the groove 102, it covers the lower part inner surface and the top inner surface of said groove respectively, and wherein, the thickness of said first insulating barrier 103 is greater than the thickness of second insulating barrier 109.Also comprise polysilicon region 104 in the groove 102, said polysilicon region 104 is covered by said first insulating barrier 103 fully.Also comprise grid G in the groove 102, its upper surface from said groove 102 extends to said polysilicon region 104 tops vertically downward, and its sidewall and lower surface are covered by said second insulating barrier 109 and said first insulating barrier 103 respectively.Said N raceway groove groove MOSFET device also comprises P type column structure 105, and it is formed at said N
-In the epitaxial loayer 101, and its sidewall and lower surface are by said N
- Epitaxial loayer 101 covers.Said N raceway groove groove MOSFET device also comprises P type tagma 106; Lower surface covers the upper surface of said column structure and contacts with said epitaxial loayer; The adjacent wall of its sidewall and said groove contacts; And less than the distance of grid lower surface apart from the epitaxial loayer upper surface, wherein, the concentration in said P type tagma 106 is greater than the concentration of said P type column structure 105 apart from the distance of epitaxial loayer upper surface for the lower surface in tagma.Said N raceway groove groove MOSFET device also comprises the P type heavily doped region 107 that is positioned at said P type tagma 106, and it does not contact the surface in P type tagma 106, and the doping content of said P type heavily doped region 107 is greater than said P type tagma 106.Also comprise N type heavily doped region 108 in the P type tagma 106; It is positioned at the top of said P type heavily doped region 107 and is extended vertically downward by the upper surface of said N raceway groove groove MOSFET device; Said N type heavily doped region 108 contacts with the adjacent wall of groove 102; Wherein, the doping content of said N type heavily doped region 108 is greater than said N
-The concentration of epitaxial loayer 101.Said N raceway groove groove MOSFET device also comprises the source metal contact S that is positioned at said P type tagma 106, and it is from said N
-The upper surface of epitaxial loayer 101 extends to vertically downward with said P type heavily doped region 107 and N type heavily doped region 108 and contacts.
For traditional N raceway groove groove MOSFET, under cut-off state, source S ground connection, drain D adds forward voltage, institute's making alive is mainly born by P type tagma and the formed PN junction of N type epitaxial loayer.As shown in Figure 1, have the super-junction structure that forms by P type column structure 105 according to the N raceway groove groove MOSFET device of this embodiment.Since be provided with the lower P type column structure 105 of relative P type tagma 106 concentration, therefore, P type column structure 105 and N
-The PN junction that epitaxial loayer 101 forms can bear bigger voltage, thereby the puncture voltage BV that forms is than the puncture voltage BV increase of traditional N raceway groove groove MOSFET.On the other hand, MOSFET compares with conventional groove, and the outer layer doping concentration of ultra knot groove MOSFET can be higher, thereby in conducting state, the conducting resistance Rds when conduction current flows through epitaxial loayer (on) will be littler.
As shown in Figure 1, have by polysilicon region 104, first insulating barrier 103 and the N according to the N raceway groove groove MOSFET device of this embodiment
-The capacitive that epitaxial loayer 101 constitutes exhausts structure.Can know polysilicon region 104, first insulating barrier 103 and the N by mos capacitance device principle
- Epitaxial loayer 101 constitutes capacitor, wherein, and polysilicon region 104 and N
- Epitaxial loayer 101 is pole plates of this capacitor, and first insulating barrier 103 is dielectrics of this capacitor.In the embodiment shown in fig. 1, polysilicon region 104 is connected to source electrode, then works as drain D and add positive voltage, when source S is connected to ground, N
-To occur in the epitaxial loayer 101 by polysilicon region 104, first insulating barrier 103 and the N
- Epitaxial loayer 101 acts on and the capacitive depleted region of formation.This capacitive depleted region and P type tagma 106 and N
- Epitaxial loayer 101 and P type column structure 105 and N
-The PN junction one that epitaxial loayer 101 forms works, and makes to add under the drain voltage identical, and is wideer than the depleted region of traditional structure device according to the depleted region in the device of present embodiment, thereby improved puncture voltage BV.In addition, the device that utilizes the utility model to propose, N
-The doping content of epitaxial loayer 101 can be higher, thereby reduce conducting resistance, and it is especially obvious that this acts on the high voltage applications occasion.In addition, owing in groove, increase polysilicon region, the parasitic capacitance that is then formed by grid, drain electrode and N type epitaxial loayer is very little.
Preferably, P type tagma 106, P type column structure 105 and N
- Epitaxial loayer 101 is selected suitable concentration and width, then adds under the drain voltage N between P type column structure 105 and the polysilicon region 104 a certain
- Epitaxial loayer 101 is exhausted fully, thereby makes device obtain bigger puncture voltage BV.
In the embodiment shown in fig. 1, polysilicon region 104 is connected to source electrode, and is connected to ground.But in other embodiments, polysilicon region 104 also can be connected to one separately less than the voltage that adds the drain voltage value.And for P raceway groove groove MOSFET device, polysilicon region also can be connected to one separately greater than the voltage that adds the drain voltage value.
A kind of structure of describing the active area that constitutes by P type tagma 106, P type heavily doped region 107, N type heavily doped region 108 and metal source S in detail embodiment illustrated in fig. 1; Those skilled in the art is to be understood that; Even change shape, structure or the relative position of P type tagma 106, P type heavily doped region 107, N type heavily doped region 108 and metal source S; Even under the situation that lacks P type heavily doped region 107, active area still can be realized by the structure with identical function.
Fig. 2 illustrates the N raceway groove groove MOSFET device according to the utility model one preferred embodiment.Compare with the N raceway groove groove MOSFET device in embodiment illustrated in fig. 1, P type column structure 105, groove 102 and polysilicon region 104 in the N raceway groove groove MOSFET device of the preferred embodiment go deep into N
- Epitaxial loayer 101 is near N
- Epitaxial loayer 101 surfaces so that depleted region is vertically bigger, thereby obtain bigger puncture voltage BV.
Fig. 3 illustrates the N raceway groove groove MOSFET device according to another embodiment of the utility model.Compare with embodiment illustrated in fig. 1, the polysilicon region 104 in embodiment illustrated in fig. 3 and the position of grid G are different.Particularly; As shown in Figure 3, in groove 102, fill first insulating barrier 103 and second insulating barrier 109, it covers the lower part inner surface and the top inner surface of said groove respectively; Wherein, the thickness of said first insulating barrier 103 is greater than the thickness of second insulating barrier 109.Comprise polysilicon region 104 in the groove 102, it is from said N
-The upper surface of epitaxial loayer 101 extends vertically downward, and its underpart sidewall and lower surface are covered by said first insulating barrier 103, and its top sidewall is covered by said second insulating barrier 109.Also comprise grid G in the groove 102, it is from said N
-The upper surface of epitaxial loayer 101 extends vertically downward, and its sidewall is covered by said first insulating barrier 103, and its lower surface is covered by said second insulating barrier 109.
It will be appreciated by those skilled in the art that Fig. 1 ~ 3 illustrate according to two kinds of the utility model embodiment ultra knot groove MOSFET device structures, these two kinds of structures show the polysilicon region that comprises in the groove and the difformity or the structure of grid.Yet; These two kinds of structures are not limited to the utility model; The technical staff in present technique field should be appreciated that the utility model also can adopt any other distressed structure to be achieved under the situation of the shape, structure or the relative position that change polysilicon region and grid.
Fig. 4 illustrates the N raceway groove groove MOSFET device according to another embodiment of the utility model.As shown in Figure 4; Compare with embodiment illustrated in fig. 1, comprise a plurality of polysilicon regions 104 according in the N raceway groove groove MOSFET device embodiment illustrated in fig. 4, it is positioned at groove 102; And covered by first insulating barrier 103, a plurality of polysilicon region 104 is vertically arranged along groove.Identical with aforementioned principles, a plurality of polysilicon regions 104 and first insulating barrier 103 and the N
-Form capacitor between the epitaxial loayer 101, thereby produce the capacitive depleted region.Said capacitive depleted region and P type tagma 106 and N
- Epitaxial loayer 101 and P type column structure 105 and N
-The PN junction one that epitaxial loayer 101 forms works, and makes to add under the drain voltage identical, and is wideer than the depleted region of traditional structure device according to the depleted region in the device of present embodiment, thereby improved puncture voltage BV.
Fig. 5 illustrates the N raceway groove groove MOSFET device according to another embodiment of the utility model.As shown in Figure 5, compare with embodiment illustrated in fig. 1, comprise a plurality of P type column structures 105 according in the N raceway groove groove MOSFET device embodiment illustrated in fig. 5, it is positioned at N
-In the epitaxial loayer 101, and all P type column structures 105 are by N
- Epitaxial loayer 101 covers, and a plurality of P type column structure 105 is vertically arranged along groove.A plurality of column structures 105 and N
- Epitaxial loayer 101 forms a plurality of PN junctions, bears voltage, thereby compares with traditional N raceway groove groove MOSFET device, and it has improved puncture voltage BV.
Above embodiment is an example with unit N raceway groove groove MOSFET device, and its structure and performance are described.Fig. 6 shows in the manufacturing, and according to the N raceway groove groove MOSFET device with a plurality of repetitives of the utility model embodiment, the structure and the performance of unit N raceway groove groove MOSFET device are suitable equally to it.
Specification of above-mentioned the utility model and execution mode only are illustrated MOSFET device of the utility model embodiment and preparation method thereof in an exemplary fashion, and are not used in the scope that limits the utility model.It all is possible changing and revise for disclosed embodiment, other feasible selection property embodiment and can be understood by those skilled in the art the equivalent variations of element among the embodiment.Other variations of embodiment disclosed in the utility model and modification do not exceed the spirit and the protection range of the utility model.
Claims (8)
1. groove metal oxide semiconductor field effect transistor device comprises:
The substrate of first conduction type;
The epitaxial loayer of first conduction type is positioned on the said substrate, and its doping content is less than the doping content of said substrate;
Groove vertically extend to the lower surface of said epitaxial loayer from the upper surface of said epitaxial loayer, and it does not contact the surface of said substrate;
First insulating barrier is positioned at said groove, and covers the lower part inner surface of said groove;
Second insulating barrier is positioned at said groove, and covers the top inner surface and said first insulating barrier of said groove, and wherein, the thickness of said second insulating barrier is less than the thickness of said first insulating barrier;
Polysilicon region is positioned at said groove, and lower surface covered by said first insulating barrier, and its sidewall is covered by said first insulating barrier or second insulating barrier;
Grid is positioned at said groove, vertically extend to the lower surface of said epitaxial loayer from the upper surface of said epitaxial loayer, and its sidewall and lower surface is covered by said second insulating barrier;
The column structure of at least one second conduction type is positioned at said epitaxial loayer, and its sidewall and lower surface covered by said epitaxial loayer, and wherein, the column structure of said at least one second conduction type is vertically arranged along epitaxial loayer;
The tagma of second conduction type; The adjacent wall of its sidewall and said groove contacts; And less than the distance of grid lower surface apart from the epitaxial loayer upper surface, wherein, the doping content in said tagma is greater than the doping content of said column structure apart from the distance of epitaxial loayer upper surface for the lower surface in tagma;
The heavily doped region of first conduction type, its be positioned at said tagma and with the adjacent wall of said groove mutually, and its doping content is greater than the doping content of said epitaxial loayer; With
Source electrode, it is positioned at said tagma, vertically extends to said tagma from the upper surface of said epitaxial loayer, and contacts with the heavily doped region of first conduction type.
2. groove metal oxide semiconductor field effect transistor device as claimed in claim 1, wherein, the upper surface of said polysilicon region and the upper surface of said groove overlap.
3. groove metal oxide semiconductor field effect transistor device as claimed in claim 1, wherein, said polysilicon region is positioned at said grid below, and its upper surface is covered by said first insulating barrier.
4. groove metal oxide semiconductor field effect transistor device as claimed in claim 1, wherein, the upper surface of said polysilicon region is covered by said second insulating barrier.
5. groove metal oxide semiconductor field effect transistor device as claimed in claim 1, wherein, said polysilicon region is connected to said source electrode.
6. groove metal oxide semiconductor field effect transistor device as claimed in claim 1; Wherein, When said first conduction type is the N type; Said polysilicon region is connected to the electronegative potential that is lower than current potential that drain electrode adds, and when said first conduction type was the P type, said polysilicon region was connected to the high potential that is higher than current potential that drain electrode adds.
7. groove metal oxide semiconductor field effect transistor device as claimed in claim 1, wherein, the zone of said first conduction type extends in the said tagma from the upper surface of said epitaxial loayer, and contacts with the adjacent wall of said groove.
8. groove metal oxide semiconductor field effect transistor device as claimed in claim 1; Wherein, Said groove metal oxide semiconductor field effect transistor device also comprises the heavily doped region of second conduction type; It is positioned at said tagma, and its concentration is greater than the concentration in said tagma, and contacts with said source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205357642U CN202454560U (en) | 2011-12-20 | 2011-12-20 | Trench MOSFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205357642U CN202454560U (en) | 2011-12-20 | 2011-12-20 | Trench MOSFET device |
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| Publication Number | Publication Date |
|---|---|
| CN202454560U true CN202454560U (en) | 2012-09-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205357642U Expired - Fee Related CN202454560U (en) | 2011-12-20 | 2011-12-20 | Trench MOSFET device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610643A (en) * | 2011-12-20 | 2012-07-25 | 成都芯源系统有限公司 | Trench MOSFET device |
| WO2022111484A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Power semiconductor device and electronic device |
-
2011
- 2011-12-20 CN CN2011205357642U patent/CN202454560U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610643A (en) * | 2011-12-20 | 2012-07-25 | 成都芯源系统有限公司 | Trench MOSFET device |
| CN102610643B (en) * | 2011-12-20 | 2015-01-28 | 成都芯源系统有限公司 | Trench MOSFET device |
| WO2022111484A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Power semiconductor device and electronic device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120926 Termination date: 20161220 |
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| CF01 | Termination of patent right due to non-payment of annual fee |