CN102522428A - High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure - Google Patents
High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure Download PDFInfo
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- CN102522428A CN102522428A CN2011104321544A CN201110432154A CN102522428A CN 102522428 A CN102522428 A CN 102522428A CN 2011104321544 A CN2011104321544 A CN 2011104321544A CN 201110432154 A CN201110432154 A CN 201110432154A CN 102522428 A CN102522428 A CN 102522428A
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- buried layer
- drift region
- voltage ldmos
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 150000001875 compounds Chemical class 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 3
- 239000002131 composite material Substances 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A high-voltage LDMOS (laterally diffused metal oxide semiconductor) structure relates to the integrated circuit technique. The high-voltage LDMOS structure comprises an N-type drift region and a P-type substrate, and is characterized in that a composite buried layer region is arranged in a P-type substrate region below the N-type drift region and comprises a P-type buried layer region and an N-type buried layer region. A P-type field reducing layer is omitted, so that a surface high-doped electronic passage of the N-type drift region can be spared, and reduction of specific on-resistance is facilitated.
Description
Technical field
The present invention relates to integrated circuit technique.
Background technology
The high-voltage LDMOS structure is a transversary because of it, can be integrated with the mesolow device, for the integrated level of raising chip and the stability of raising chip significant advantage is arranged.Can reduce simultaneously the packaging cost of chip.The high-voltage LDMOS structure is used widely in power management chip now, has much the trend that replaces the VDMOS device, especially in the application scenario greater than 700v.
The index of judging the LDMOS structural behaviour is mainly two of conduction resistance and puncture voltages.The development trend of LDMOS is to reach under the situation of withstand voltage index, reducing the conduction resistance of device as far as possible now.
The conduction resistance of LDMOS is directly proportional with drift region length, is inversely proportional to the drift region doping content.The method that reduces conduction resistance is exactly to reduce the drift region length of device and increase the doping content of drift region.
Fig. 1 falls a layer LDMOS structure for no P type of the prior art; This structure with have the P type to fall a layer LDMOS to compare; Technology simply can be economized a P type and fall a layer version, but this structure is difficult to longitudinal electric field leveling in the body of drift region, and is indifferent for the optimization of electric field; Be difficult to improve the doping content of drift region (N type drift region and n type buried layer), be difficult to obtain very low conduction resistance.
Fig. 2 falls a layer LDMOS structure for the P of having type of the prior art, and this structure is fallen a layer LDMOS with no P type and compared, and needs to increase a P type and fall a layer version, and this structure helps optimizing the interior longitudinal electric field of drift region body.Help improving the doping content of drift region (N type drift region and n type buried layer).This structure is fallen a layer owing to introduce the p type, will be compound fall surface, drift region N type impurity, and the resistivity in this N type zone is minimum, is the main thoroughfare of electron stream, so be unfavorable for reducing conduction resistance.
Summary of the invention
Technical problem to be solved by this invention is that a kind of high-voltage LDMOS structure that can reduce conduction resistance is provided.
The technical scheme that the present invention solve the technical problem employing is that the high-voltage LDMOS structure comprises N drift region and P type substrate; It is characterized in that; P type area below the N drift region is provided with compound buried regions district, and said compound buried regions district comprises p type buried layer district and n type buried layer district.
Said compound buried regions district is made up of the p type buried layer district in n type buried layer district and the embedding n type buried layer district.
Perhaps, said compound buried regions district is made up of the n type buried layer district and the p type buried layer district of staggered vertical arrangement.
The invention has the beneficial effects as follows,
1, do not adopt the P type to fall a layer, can abdicate the surperficial highly doped electron channel of N type drift region, help reducing conduction resistance.
2, adopt rational N, P buried regions implantation dosage can effectively regulate drift region body internal electric field, make under the highly doped situation in drift region body in the longitudinal electric field leveling of trying one's best, near breakdown electric field.
The present invention can significantly improve the doping content of drift region, thereby reduces the conduction resistance of device.
Description of drawings
Fig. 1 is that a layer LDMOS structural representation falls in no P type of the prior art.
Fig. 2 is that a layer LDMOS structural representation falls in the P of having type of the prior art.
Fig. 3 is a structural representation of the present invention.
Fig. 4 is the structural representation (A-A of Fig. 3 to) of embodiments of the invention 1.
Fig. 5 is the structural representation (A-A of Fig. 3 to) of embodiments of the invention 2.
Embodiment
High-voltage LDMOS structure of the present invention comprises N drift region and P type substrate, and the P type area below the N drift region is provided with compound buried regions district, and said compound buried regions district comprises p type buried layer district and n type buried layer district.P type buried layer of the present invention district and n type buried layer district are all vertically runs through compound buried regions district.
Embodiment 1, referring to Fig. 3, Fig. 4.
The compound buried regions district of present embodiment is made up of the n type buried layer district and the p type buried layer district of staggered vertical arrangement.N type buried layer district and p type buried layer district are all perpendicular to the N drift region and are provided with.
Embodiment 2, referring to Fig. 3, Fig. 5.
The compound buried regions district of present embodiment is made up of a plurality of p type buried layers district in n type buried layer district and the embedding n type buried layer district.The p type buried layer district is perpendicular to the N drift region.
Claims (3)
1. the high-voltage LDMOS structure comprises N drift region and P type substrate, it is characterized in that, the P type area below the N drift region is provided with compound buried regions district, and said compound buried regions district comprises p type buried layer district and n type buried layer district.
2. high-voltage LDMOS structure as claimed in claim 1 is characterized in that, said compound buried regions district is made up of the p type buried layer district in n type buried layer district and the embedding n type buried layer district.
3. high-voltage LDMOS structure as claimed in claim 1 is characterized in that, said compound buried regions district is made up of the n type buried layer district and the p type buried layer district of staggered vertical arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110432154.4A CN102522428B (en) | 2011-12-21 | 2011-12-21 | High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110432154.4A CN102522428B (en) | 2011-12-21 | 2011-12-21 | High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102522428A true CN102522428A (en) | 2012-06-27 |
| CN102522428B CN102522428B (en) | 2014-12-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110432154.4A Expired - Fee Related CN102522428B (en) | 2011-12-21 | 2011-12-21 | High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure |
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| Country | Link |
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| CN (1) | CN102522428B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015043543A1 (en) * | 2013-09-30 | 2015-04-02 | 无锡华润上华半导体有限公司 | High-voltage ldmos device |
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
| CN106158963A (en) * | 2015-02-18 | 2016-11-23 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of buried layer |
| CN106252406A (en) * | 2015-06-12 | 2016-12-21 | 旺宏电子股份有限公司 | There is the semiconductor device of buried regions |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540339A (en) * | 2009-05-05 | 2009-09-23 | 浙江大学 | High-side NLDMOS structure |
| US7960222B1 (en) * | 2007-11-21 | 2011-06-14 | National Semiconductor Corporation | System and method for manufacturing double EPI N-type lateral diffusion metal oxide semiconductor transistors |
| CN202434526U (en) * | 2011-12-21 | 2012-09-12 | 成都成电硅海科技股份有限公司 | High-voltage transverse diffusion metal-oxide semiconductor structure |
-
2011
- 2011-12-21 CN CN201110432154.4A patent/CN102522428B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7960222B1 (en) * | 2007-11-21 | 2011-06-14 | National Semiconductor Corporation | System and method for manufacturing double EPI N-type lateral diffusion metal oxide semiconductor transistors |
| CN101540339A (en) * | 2009-05-05 | 2009-09-23 | 浙江大学 | High-side NLDMOS structure |
| CN202434526U (en) * | 2011-12-21 | 2012-09-12 | 成都成电硅海科技股份有限公司 | High-voltage transverse diffusion metal-oxide semiconductor structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015043543A1 (en) * | 2013-09-30 | 2015-04-02 | 无锡华润上华半导体有限公司 | High-voltage ldmos device |
| CN106158963A (en) * | 2015-02-18 | 2016-11-23 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of buried layer |
| CN106252406A (en) * | 2015-06-12 | 2016-12-21 | 旺宏电子股份有限公司 | There is the semiconductor device of buried regions |
| CN106252406B (en) * | 2015-06-12 | 2019-03-15 | 旺宏电子股份有限公司 | Semiconductor device with buried layer |
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
| CN106057904B (en) * | 2016-07-29 | 2018-11-30 | 东莞华南设计创新院 | A kind of germanium base SiGe drop field layer LDMOS device structure |
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| Publication number | Publication date |
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| CN102522428B (en) | 2014-12-17 |
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