CN103474466B - A kind of high tension apparatus and manufacture method thereof - Google Patents
A kind of high tension apparatus and manufacture method thereof Download PDFInfo
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- CN103474466B CN103474466B CN201310418088.4A CN201310418088A CN103474466B CN 103474466 B CN103474466 B CN 103474466B CN 201310418088 A CN201310418088 A CN 201310418088A CN 103474466 B CN103474466 B CN 103474466B
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 360
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005516 engineering process Methods 0.000 abstract description 26
- 238000002360 preparation method Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
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- 229910052710 silicon Inorganic materials 0.000 description 6
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract
The present invention relates to semiconductor technology, relate to specifically a kind of high tension apparatus and manufacture method thereof. high tension apparatus of the present invention is integrated on the first conductive type semiconductor substrate, comprise the second conductive type semiconductor drift region, the second conductive type semiconductor source region, the second conductive type semiconductor drain region, the second conductive type semiconductor heavily doped layer, the first conductive type semiconductor tagma, the first conductive type semiconductor body contact zone, a layer falls in the first conductive type semiconductor, gate oxide, field oxide, medium before metal, polygate electrodes, source metal, drain metal, the second conductive type semiconductor heavily doped layer is arranged on field oxide and the first conductive type semiconductor falls between a layer. beneficial effect of the present invention is, in the case of identical ducting capacity, has less chip area, the surface field of optimised devices, and preparation method is simple, and technology difficulty is lower. the present invention is particularly useful for high tension apparatus.
Description
Technical field
The present invention relates to semiconductor technology, relate to specifically a kind of high tension apparatus and manufacture method thereof.
Background technology
High tension apparatus is that high-voltage power integrated circuit develops requisite part, and high voltage power device requires to have high breakdown potentialPress low conducting resistance and low switching loss. At power LDMOS(LatralDouble-diffusedMOSFET) deviceIn design, have contradictory relation than conducting resistance and breakdown voltage, along with the raising of breakdown voltage, the ratio conducting resistance of device is anxiousAcute rising, thus limit the application of high-voltage LDMOS device in high-voltage power integrated circuit, especially requiring low conducting to damageIn the circuit of consumption and little chip area. In order to overcome the problem of high conducting resistance, the people such as J.A.APPLES have proposed RESURF(ReducedSURfaceField) reduce surface field technology, be widely used in the design of high tension apparatus, wherein, tripleRESURF is up to now, for the good structure of the near optimal of the products such as actual AC/DC, further improves on this basisThe ratio conducting resistance of high tension apparatus and withstand voltage be the demand of industry, simultaneously the source electric field of tripleRESURF structure is too high, shadowRing device reliability.
Summary of the invention
Technical problem to be solved by this invention, is exactly for the problems referred to above, proposes a kind of novel high-pressure device and preparation method thereof.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of high tension apparatus, its structure cell comprises the firstConductive type semiconductor substrate 1, the second conductive type semiconductor drift region 21, the second conductive type semiconductor source region 22,The second conductive type semiconductor drain region 23, the first conductive type semiconductor tagma 31, the first conductive type semiconductor body connectA layer 34, gate oxide fall in contact area 32, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor41, medium 43, polygate electrodes 51, source metal 52 and drain metal 53 before field oxide 42, metal, described secondPlant conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31 and the first conductive type semiconductor tagmaBuried regions 33 is arranged in the first conductive type semiconductor substrate 1, and described the first conductive type semiconductor tagma buried regions 33 is establishedPut the lower surface in the first conductive type semiconductor tagma 31, a layer 34 and second falls in described the first conductive type semiconductorPlant conductive type semiconductor drain region 23 and be arranged in the second conductive type semiconductor drift region 21, described the second conduction typeSemiconductor source region 22 and the first conductive type semiconductor body contact zone 32 are arranged in the first conductive type semiconductor tagma 31And separate, described field oxide 42 is arranged on the upper surface of the second conductive type semiconductor drift region 21, described grid oxygenChange upper surface, the first conductive type semiconductor tagma 31 that layer 41 is arranged on part the second conductive type semiconductor source region 22Upper surface be connected with the upper surface of the second conductive type semiconductor drift region 21 and with field oxide 42, described polysilicon gateElectrode 51 is arranged on the upper surface of gate oxide 41 and the upper surface of part field oxide 42, and described source metal 52 is arranged onThe upper surface of the first conductive type semiconductor body contact zone 32, the upper surface in part the second conductive type semiconductor source region 22,Described drain metal 53 is arranged on the upper surface in part the second conductive type semiconductor drain region 23, and before described metal, medium 43 is filled outFill between source metal 52 and drain metal 53, source metal 52 and drain metal 53 medium 43 upper surfaces before metal prolongStretch formation field plate, it is characterized in that, also comprise the second conductive type semiconductor heavily doped layer, described the second conduction type halfConductor heavily doped layer is made up of the second conductiving type semiconductor area that is divided into multistage and is arranged on the first conductive type semiconductorFall between a layer 34 and field oxide 42.
Wherein, the second conductive type semiconductor heavily doped layer is divided into 61～6iMultistage, multiple the second conductive type semiconductors are heavily dopedDiamicton 61～6iSectional area size can be identical or different, interregional distance is along with to the second conductive type semiconductor drain region 23Near and reduce gradually, the spacing of sectional area can be identical or not identical, area size is along with partly leading to the second conduction typeBody drain district 23 near and increase gradually.
Concrete, also comprising the second conductive type semiconductor buried regions 24, described the second conductive type semiconductor buried regions 24 is establishedPut in the second conductive type semiconductor drift region 21 and be positioned at the first conductive type semiconductor and fall a lower surface for layer 34.
The advantage of this programme is to provide for device the conductive channel of another low-resistance.
Concrete, described the first conductive type semiconductor tagma 31 and the first conductive type semiconductor tagma buried regions 33 arrangeIn the second conductive type semiconductor drift region 21.
Concrete, described the second conductive type semiconductor drift region 21 is arranged on the upper of the first conductive type semiconductor substrate 1Surface.
Concrete, also comprise SOI substrate 2, described SOI substrate 2 is arranged on the first conductive type semiconductor substrate 1 and theBetween two kinds of conductive type semiconductor drift regions 21 and respectively with the first conductive type semiconductor substrate 1 and the second conduction typeDrift semiconductor district 21 connects.
A manufacture method for high tension apparatus, is characterized in that, comprises the following steps:
The first step: adopt photoetching and ion implantation technology, inject the second conduction in the first conductive type semiconductor substrate 1Type semiconductor impurity, annealing diffuses to form the second conductive type semiconductor drift region 21, and described the first conduction type is partly ledThe resistivity of body substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 21 is1E12cm-2～2E13cm-2；
Second step: adopt photoetching and ion implantation technology, inject the first conduction in the first conductive type semiconductor substrate 1Type semiconductor impurity, annealing diffuses to form the first conductive type semiconductor tagma 31, described the first conductive type semiconductorThe implantation dosage in tagma 31 is 1E12cm-2～5E13cm-2；
The 3rd step: 21 upper surfaces form field oxide 42 in the second conductive type semiconductor drift region;
The 4th step: adopt photoetching and ion implantation technology, inject the first and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor impurity, forms the first conductive type semiconductor tagma buried regions 33 and the first conductive type semiconductor and falls a layer34, the implantation dosage of described the first conductive type semiconductor impurity is 1E11cm-2～2E13cm-2；
The 5th step: adopt photoetching and ion implantation technology, inject the second and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor impurity, rapid thermal annealing forms the second conductive type semiconductor heavily doped layer of segmentation, and described the second is ledThe implantation dosage of electricity type semiconductor heavily doped layer is 1E11cm-2～2E13cm-2；
The 6th step: in upper surface, the first conductive type semiconductor tagma 31 in part the second conductive type semiconductor source region 22Upper surface and the upper surface of the second conductive type semiconductor drift region 21 form gate oxide 41, described gate oxide 41Thickness is 7nm～100nm;
The 7th step: form polygate electrodes 51, institute at the upper surface of gate oxide 41 and the upper surface of part field oxide 42The square resistance of stating polysilicon gate 51 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form the second and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor drain region 23 forms separate the second conduction type half in the first conductive type semiconductor tagma 31Conductor source region 22, the first conductive type semiconductor body contact zone 32, described the second conductive type semiconductor drain region 23, secondThe implantation dosage of planting conductive type semiconductor source 22, the first conductive type semiconductor body contact zone 32 is 1E13cm-2～2E16cm-2；
The 9th step: in upper surface, the upper surface of polysilicon gate 51, the oxidation in part the second conductive type semiconductor source 22The upper surface of layer 42 and the upper surface deposit in part the second conductive type semiconductor drain region 23 form the front medium 43 of metal;
The tenth step: in upper surface and the second conductive type semiconductor source 22 of the first conductive type semiconductor body contact zone 32Upper surface form source metal 52, form drain metal 53, source at the upper surface in the second conductive type semiconductor drain region 23Before utmost point metal 52 and drain metal 53 and metal medium 43 be connected and before metal the upper surface of medium 43 extend to form field plate.
Concrete, described the first conductive type semiconductor tagma buried regions 33 can prevent parasitic triode conducting, raising devicePerformance, the 4th step also can not form the first conductive type semiconductor tagma buried regions 33.
Concrete, in described the 5th step, the second conductive type semiconductor heavily doped layer 6 of segmentation1～6iBy rapid thermal annealing workSkill forms, and it is identical or different that it injects window size, window pitch along with to the second conductive type semiconductor drain region 23 near andReduce gradually, the spacing of injecting window is identical or not identical, and window size is along with leaning on to the second conductive type semiconductor drain region 23Closely and gradually increase.
Further, can also form the second conductive type semiconductor drift region 21 by epitaxy technique, or at SOI substrate materialOn material, form the second conductive type semiconductor drift region 21, the second conductive type semiconductor heavily doped layer 61～6iEmploying segmentation is mixedAssorted, when withstand voltage, introduce multiple surface field spikes, optimised devices surface field avoids source electric field excessive simultaneously, prevents high field effectShould.
Beneficial effect of the present invention is, in the case of keep high puncture withstand voltage, can reduce greatly device than conducting resistance,Reduce the peak electric field of high tension apparatus source simultaneously, avoid high-field effect, improve the breakdown voltage of device, with conventional high-tension deviceCompare, high tension apparatus provided by the invention has less conducting resistance in the situation that of identical chips area, in identical conductingIn the situation of ability, there is less chip area, and the surface field of optimised devices well, meanwhile, system provided by the inventionPreparation Method is simple, and technology difficulty is lower.
Brief description of the drawings
Fig. 1 is the generalized section of conventional high-tension device;
Fig. 2 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iSpacing reduces gradually, and the second conduction type is partly ledBody drift region 21 forms by Implantation and knot technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 3 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iWidth increases gradually, and the second conduction type is partly ledBody drift region 2 is to form by Implantation and knot technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 4 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iSpacing reduces gradually, and the second conduction type is partly ledBody drift region 21 forms by epitaxy technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 5 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iWidth increases gradually, and the second conduction type is partly ledBody drift region 21, for to form by epitaxy technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 6 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iSpacing reduces gradually, and the second conduction type is partly ledBody drift region 21 forms by epitaxy technique, is integrated on SOI substrate;
Fig. 7 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iWidth increases gradually, and the second conduction type is partly ledBody drift region 21 forms by epitaxy technique, is integrated on SOI substrate;
Fig. 8 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iSpacing reduces gradually, and the second conduction type is partly ledBody buried regions 24 is arranged in the second conductive type semiconductor drift region 21, is positioned at the first conductive type semiconductor and falls a layer 34Below;
Fig. 9 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iWidth increases gradually, and the second conduction type is partly ledBody buried regions 24 is arranged in the second conductive type semiconductor drift region 21, is positioned at the first conductive type semiconductor and falls a layer 34Below;
Figure 10 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iSpacing reduces gradually, and all high-voltage device structures allBe arranged in the second conductive type semiconductor drift region 21;
Figure 11 is the generalized section of a kind of high tension apparatus of the present invention, along with the heavy doping that drains to the second conductive type semiconductorDistrict 23 is close, the second conductive type semiconductor heavily doped region 6 of segmentation1～6iWidth increases gradually,, all high-voltage device structuresAll be arranged in the second conductive type semiconductor drift region 21;
Figure 12 is the second conductive type semiconductor heavily doped layer 6 in embodiment 11～6iMultiple injection window structure schematic diagrames;
Figure 13 is that embodiment 1 injects the second conductive type semiconductor heavily doped layer 6 that forms segmentation1～6iSchematic diagram;
Figure 14 is the second conductive type semiconductor heavily doped layer 6 in embodiment 21～6iMultiple injection window structure schematic diagrames;
Figure 15 is that embodiment 2 injects the second conductive type semiconductor heavily doped layer 6 that forms segmentation1～6iSchematic diagram.
Detailed description of the invention
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
As shown in Figure 1, be traditional high-voltage device structure profile, high tension apparatus is integrated in the first conductive type semiconductor lining, comprise the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conduction at the end 1A layer 34, field oxide 42, gate oxide 41, fall in type semiconductor tagma buried regions 33, the first conductive type semiconductor moreCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionType semiconductor body contact zone 32; The first conductive type semiconductor fall layer 34 by ion implantation technology realize, by the secondConductive type semiconductor drift region 21 surrounds; The first conductive type semiconductor tagma buried regions 33 is positioned at the first conduction type bodyBetween district 31 and the first conductive type semiconductor substrate 1; Source metal 52 is positioned at the first conductive type semiconductor tagma 31Upside, be connected with the first conductive type semiconductor body contact zone 32 with the second conductive type semiconductor source region 22, drain electrode goldBelonging to 53 is connected with the second conductive type semiconductor drain region 23; Polygate electrodes 51 is positioned at gate oxide 41 tops, an oxygenChange layer 43 and be positioned at 21 tops, the second conductive type semiconductor drift region; Polygate electrodes 51, source metal 52 and drain electrode goldBetween belonging to 53, mutually isolate by medium 43 before metal.
As shown in Figure 2, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor fall in type semiconductorMedium before drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal43, source metal 52, drain metal 53; It is characterized in that, described high-voltage semi-conductor device also comprises the first conduction type halfLayer 34 and the second conductive type semiconductor heavily doped layer 6 fall in conductor1～6i, described the second conductive type semiconductor heavily doped layer61～6iFall between a layer 34 at field oxide 42 and the first conductive type semiconductor. Wherein, the first conduction type is partly ledA layer 34 falls in body to be realized by Implantation and knot technique, the second conductive type semiconductor heavily doped layer 61～6iPass through implantationEnter with rapid thermal anneal process and realize, along with close to the first conductive type semiconductor drain region 23, the second conduction class of segmentationType semiconductor heavily doped region 61～6iSpacing reduces gradually, and this structure not only reduces the ratio conducting resistance of device, also reduces device sourceElectric Field Distribution, avoids high-field effect, optimised devices surface field, thus improve device electric breakdown strength, alleviate withstand voltage and compare conductingThe contradictory relation of resistance.
As shown in Figure 3, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, field oxide 42, gate oxide 41, manyCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionMedium 43, source metal 52, drain metal 53 before type semiconductor body contact zone 32, metal. Wherein, the first conduction classA layer 34 falls in type semiconductor to be realized by Implantation and knot technique, the second conductive type semiconductor heavily doped layer 61～6iPass throughImplantation and rapid thermal anneal process are realized, along with close to the first conductive type semiconductor drain region 23, and the second of segmentationConductive type semiconductor heavily doped region 61～6iWidth increases gradually, and its operation principle is similar to Fig. 2, reduces device source electric field and dividesCloth, avoids high-field effect, improves device electric breakdown strength, simultaneously for electric current provides low impedance path, reduces device than conducting resistance,Alleviate than conducting resistance and withstand voltage contradictory relation.
As shown in Figure 4, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, field oxide 42, gate oxide 41, manyCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionMedium 43, source metal 52, drain metal 53 before type semiconductor body contact zone 32, metal. Wherein, device is integrated inOn a kind of conductive type semiconductor substrate 1, realize by epitaxy technique the second conductive type semiconductor drift region 21, other worksSkill process and operation principle are referring to the explanation to Fig. 2.
As shown in Figure 5, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, field oxide 42, gate oxide 41, manyCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionMedium 43, source metal 52, drain metal 53 before type semiconductor body contact zone 32, metal. Wherein, device is integrated inOn a kind of conductive type semiconductor substrate 1, realize by epitaxy technique the second conductive type semiconductor drift region 21, other worksSkill process and operation principle are referring to the explanation to Fig. 3.
As shown in Figure 6, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, field oxide 42, gate oxide 41, manyCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionMedium 43, source metal 52, drain metal 53 before type semiconductor body contact zone 32, metal. Wherein, device is integrated in SOIOn backing material, realize by epitaxy technique the second conductive type semiconductor drift region 21, other technical process and operation principleReferring to the explanation to Fig. 2.
As shown in Figure 7, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, field oxide 42, gate oxide 41, manyCrystal silicon gate electrode 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductionMedium 43, source metal 52, drain metal 53 before type semiconductor body contact zone 32, metal. Wherein, device is integrated in SOIOn backing material, realize by epitaxy technique the second conductive type semiconductor drift region 21, other technical process and operation principleReferring to the explanation to Fig. 3.
As shown in Figure 8, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, the second conductive type semiconductor buried regions 24,Field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductionMedium 43, source metal 52, leakage before type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metalUtmost point metal 53. The second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, on itSurface falls layer 34 with the first conductive type semiconductor and is connected, and the second conductive type semiconductor buried regions 24 is carried for high tension apparatusHigh another low impedance path, further reduces and compares conducting resistance. Other technical process and operation principle are referring to the explanation to Fig. 2.
As shown in Figure 9, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, the second conductive type semiconductor buried regions 24,Field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductionMedium 43, source metal 52, leakage before type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metalUtmost point metal 53. The second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, on itSurface falls layer 34 with the first conductive type semiconductor and is connected, and the second conductive type semiconductor buried regions 24 is carried for high tension apparatusHigh another low impedance path, further reduces and compares conducting resistance. Other technical process and operation principle are referring to the explanation to Fig. 3.
As shown in figure 10, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, the second conductive type semiconductor buried regions 24,Field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductionMedium 43, source metal 52, leakage before type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metalUtmost point metal 53. The all structures of high tension apparatus are all arranged in the second conductive type semiconductor drift region 21, the first conduction typeSelf-isolation is realized in semiconductor body and the second conductive type semiconductor drift region 21. Other technical process and operation principle are referring to rightThe explanation of Fig. 2.
As shown in figure 11, be a kind of high-voltage device structure profile provided by the invention, comprise that the second conductive type semiconductor floatsMove district 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conduction classA layer 34, the second conductive type semiconductor heavily doped layer 6 fall in type semiconductor1～6i, the second conductive type semiconductor buried regions 24,Field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductionMedium 43, source metal 52, leakage before type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metalUtmost point metal 53. The all structures of high tension apparatus are all arranged in the second conductive type semiconductor drift region 21, the first conduction typeSelf-isolation is realized in semiconductor body and the second conductive type semiconductor drift region 21. Other technical process and operation principle are referring to rightThe explanation of Fig. 3.
Operation principle of the present invention is:
Operation principle of the present invention and traditional high tension apparatus are similar, are all the breakdown potentials that application charge balance concept improves devicePress, but lateral high-voltage device conduction loss provided by the invention is lower than traditional lateral high-voltage device. Fig. 1 is traditional high tension apparatus,Comprise that the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 21, the first conduction type partly leadBody tagma 31, the first conductive type semiconductor fall layer 34, field oxide 42, gate oxide 41, polysilicon gate 51,Medium 43, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conduction before metalType semiconductor body contact zone 32. When break-over of device, electric current conducts electricity through the second from 23rd district, the second conductive type semiconductor drain regionType semiconductor drift region 21 flows to the second conductive type semiconductor source region 22, due to the second conductive type semiconductor drift region21 concentration is lower, and the conducting resistance of device is very large, and conduction loss increases. As shown in Figure 2, be high-voltage device provided by the inventionPart, compared with traditional lateral high-voltage device, high tension apparatus provided by the invention by ion implantation technology at the second conduction typeIn drift semiconductor district 21, form the first conductive type semiconductor and fall floor 34, and by Implantation and knot technique secondPlant the second conductive type semiconductor heavily doped layer 6 of conductive type semiconductor drift region 21 surface formation segmentations1～6i. When ON state,The heavily doped layer 6 of high concentration1～6iFor high tension apparatus provides a large amount of majority carriers, form leading of a low-resistance at device surfaceElectric channel, can greatly reduce break-over of device resistance, thereby reduces greatly process costs. When OFF state, drain metal 53 addsHigh pressure, a layer 34 and the first conductive type semiconductor substrate 1 assisted depletion the second conduction fall in the first conductive type semiconductorType semiconductor drift region 21 and the second conductive type semiconductor heavily doped layer 61～6i, make device obtain larger breakdown voltage.Meanwhile, the second conductive type semiconductor heavy doping 6 of segmentation1～6iReduce the source electric field of device, avoid high-field effect, at tableFace is introduced multiple electric field spikes, and the surface field of modulation drift region 21, improves the withstand voltage of device, thereby alleviated horizontal high pressure meritIn rate device than conducting resistance and withstand voltage contradictory relation. Therefore, in power integrated circuit application, same output current abilityCondition under, the area of high-voltage semi-conductor device is minimized.
Preparation method's step of a kind of high tension apparatus provided by the invention is as follows:
The first step: adopt photoetching and ion implantation technology, inject the second conduction in the first conductive type semiconductor substrate 1Type semiconductor impurity, annealing diffuses to form the second conductive type semiconductor drift region 21, and described the first conduction type is partly ledThe resistivity of body substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 21 is1E12cm-2～2E13cm-2；
Second step: adopt photoetching and ion implantation technology, inject the first conduction in the first conductive type semiconductor substrate 1Type semiconductor impurity, annealing diffuses to form the first conductive type semiconductor tagma 31, described the first conductive type semiconductorThe implantation dosage in tagma 31 is 1E12cm-2～5E13cm-2；
The 3rd step: 21 upper surfaces form field oxide 42 in the second conductive type semiconductor drift region;
The 4th step: adopt photoetching and ion implantation technology, inject the first and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor impurity, forms the first conductive type semiconductor tagma buried regions 33 and the first conductive type semiconductor and falls a layer34, the implantation dosage of described the first conductive type semiconductor impurity is 1E11cm-2～2E13cm-2；
The 5th step: adopt photoetching and ion implantation technology, inject the second and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor impurity, rapid thermal annealing forms the second conductive type semiconductor heavily doped layer of segmentation, and described the second is ledThe implantation dosage of electricity type semiconductor heavily doped layer is 1E11cm-2～2E13cm-2；
The 6th step: in upper surface, the first conductive type semiconductor tagma 31 in part the second conductive type semiconductor source region 22Upper surface and the upper surface of the second conductive type semiconductor drift region 21 form gate oxide 41, described gate oxide 41Thickness is 7nm～100nm;
The 7th step: form polygate electrodes 51, institute at the upper surface of gate oxide 41 and the upper surface of part field oxide 42The square resistance of stating polysilicon gate 51 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form the second and lead in the second conductive type semiconductor drift region 21Electricity type semiconductor drain region 23 forms separate the second conduction type half in the first conductive type semiconductor tagma 31Conductor source region 22, the first conductive type semiconductor body contact zone 32, described the second conductive type semiconductor drain region 23, secondThe implantation dosage of planting conductive type semiconductor source 22, the first conductive type semiconductor body contact zone 32 is 1E13cm-2～2E16cm-2；
The 9th step: in upper surface, the upper surface of polysilicon gate 51, the oxidation in part the second conductive type semiconductor source 22The upper surface of layer 42 and the upper surface deposit in part the second conductive type semiconductor drain region 23 form the front medium 43 of metal;
The tenth step: in upper surface and the second conductive type semiconductor source 22 of the first conductive type semiconductor body contact zone 32Upper surface form source metal 52, form drain metal 53, source at the upper surface in the second conductive type semiconductor drain region 23Before utmost point metal 52 and drain metal 53 and metal medium 43 be connected and before metal the upper surface of medium 43 extend to form field plate.
Wherein, the second conductive type semiconductor drift region 21 can also form by epitaxy technique; Field oxide 42 is all rightAfter a layer 34 falls in the first conductive type semiconductor, form, can utilize the annealing process of field oxide 42, to the firstConductive type semiconductor falls a layer 34 and carries out annealing in process, and device can be integrated on SOI substrate simultaneously.
The present invention forms the first conductive type semiconductor by ion implantation technology in the second conductive type semiconductor drift regionFall layer, and above a layer falls in the first conductive type semiconductor, form the second conduction type by ion implantation technology and partly leadBody weight doped layer. When ON state, the second conductive type semiconductor heavily doped layer provides the surface conductance passage of a low-resistance for device,Conducting resistance and the power consumption of device are reduced. Meanwhile, the second conductive type semiconductor heavily doped layer of segmentation reduces device sourceElectric field, avoids high-field effect, introduces multiple electric field spikes at device surface, optimised devices surface field, thereby raising deviceBreakdown voltage. Compared with the horizontal high voltage power device of tradition, high tension apparatus provided by the invention is the in the situation that of identical chips areaThere is less conducting resistance (or thering is less chip area in the case of identical ducting capacity). And the present invention alsoA kind of manufacturing technology of high tension apparatus is provided, and its technique is comparatively simple, and cost is lower.
In method provided by the invention, the 4th step and the 5th step are key feature step.
Embodiment 1:
This routine adopting process is, the second conductive type semiconductor heavily doped layer 61～6iThere are multiple Implantation windows, windowSize identical, and the spacing difference of window, along with close to the second conductive type semiconductor drain region 23, injects window pitchReduce gradually, as shown in figure 12. Figure 13 is the device architecture profile after the second conductive type semiconductor Impurity injection, figureAfter middle the second conductive type semiconductor Impurity injection, form the second conductive type semiconductor heavily doped layer 6 of segmentation1～6i. Meanwhile,Field oxide 42 formed before an ion implantation technology of layer 34 falls in the first conductive type semiconductor, first formed field oxide42, the annealing process of field oxide 42 can not affect Implantation below. The second conductive type semiconductor heavy doping of segmentationLayer 61～6i, the surface of a low-resistance is provided for high tension apparatus when ON state, reduce the ratio conducting resistance of device, when OFF state, reduce deviceSource electric field, avoid device to puncture in advance, improve the breakdown voltage of device.
Embodiment 2:
This routine adopting process is, the second conductive type semiconductor heavily doped layer 61～6iThere are multiple Implantation windows, windowVary in size, and the spacing of window is identical, along with close to the second conductive type semiconductor drain region 23, injects window sizeIncrease gradually, as shown in figure 14. Figure 15 is the device architecture profile after the second conductive type semiconductor Impurity injection, figureAfter middle the second conductive type semiconductor Impurity injection, form the second conductive type semiconductor heavily doped layer 6 of segmentation1～6i. Meanwhile,Field oxide 42 formed before an ion implantation technology of layer 34 falls in the first conductive type semiconductor, first formed field oxide42, the annealing process of field oxide 42 can not affect Implantation below. The second conductive type semiconductor heavy doping of segmentationLayer 61～6i, the surface of a low-resistance is provided for high tension apparatus when ON state, reduce the ratio conducting resistance of device, when OFF state, reduce deviceSource electric field, avoid device to puncture in advance, improve the breakdown voltage of device. The high tension apparatus that this routine technological process forms,Its operation principle is identical with embodiment 1.
Can be obtained by above-mentioned explanation, the present invention by photoetching and ion implantation technology in the second conductive type semiconductor drift region 21Form the first conductive type semiconductor and fall a layer 34, by photoetching and ion implantation technology, at the second conductive type semiconductorThe second conductive type semiconductor heavily doped layer 6 that the surface of drift region 21 forms1～6i. When ON state, the second conduction type is partly ledBody weight doped layer 61～6iFor device provides a surperficial low-resistance conductive channel, reduce the resistivity of device surface, thereby greatlyReduce the conducting resistance of device. When OFF state, the second conductive type semiconductor heavily doped layer 6 of linear doping1～6iOptimised devicesSurface field, avoid source electric field excessive, prevent that high-field effect from causing device to puncture in advance, novel high-pressure device is hadHigher breakdown voltage. Therefore,, compared with conventional high-tension device, high tension apparatus provided by the invention is in the feelings of identical chips areaUnder condition, there is less conducting resistance (or thering is less chip area in the case of identical ducting capacity).
Claims (3)
1. a high tension apparatus, its structure cell comprises the first conductive type semiconductor substrate (1), the second conduction type halfConductor drift region (21), the second conductive type semiconductor source region (22), the second conductive type semiconductor drain region (23),One conductive type semiconductor tagma (31), the first conductive type semiconductor body contact zone (32), the first conduction type halfConductor tagma buried regions (33), the first conductive type semiconductor fall layer (34), a gate oxide (41), field oxide (42),Medium (43), polygate electrodes (51), source metal (52) and drain metal (53) before metal, described the second conductionType semiconductor drift region (21), described the first conductive type semiconductor tagma buried regions (33) is arranged on the first conduction typeThe lower surface of semiconductor body (31), a layer (34) and the second conduction type half fall in described the first conductive type semiconductorConductor drain region (23) is arranged in the second conductive type semiconductor drift region (21), described the second conductive type semiconductorSource region (22) and the first conductive type semiconductor body contact zone (32) are arranged on the first conductive type semiconductor tagma (31)In and separate, described field oxide (42) is arranged on the upper surface of the second conductive type semiconductor drift region (21),Described gate oxide (41) is arranged on upper surface, the first conduction class in part the second conductive type semiconductor source region (22)The upper surface of the upper surface of type semiconductor body (31) and the second conductive type semiconductor drift region (21) and field oxide(42) connect, described polygate electrodes (51) is arranged on upper surface and the part field oxide (42) of gate oxide (41)Upper surface, described source metal (52) is arranged on upper surface, the portion of the first conductive type semiconductor body contact zone (32)Divide the upper surface in the second conductive type semiconductor source region (22), described drain metal (53) is arranged on part the second conductionThe upper surface in type semiconductor drain region (23), before described metal, medium (43) is filled in source metal (52) and drain metal(53), between, source metal (52) and drain metal (53) medium (43) upper surface before metal extends to form field plate,It is characterized in that, also comprise the second conductive type semiconductor heavily doped layer, described the second conductive type semiconductor heavily doped layerForm and be arranged on the first conductive type semiconductor by the second conductiving type semiconductor area that is divided into multistage and fall a layer (34)And between field oxide (42); Also comprise the second conductive type semiconductor buried regions (24), described the second conduction type is partly ledBody buried regions (24) is arranged in the second conductive type semiconductor drift region (21) and is positioned at the first conductive type semiconductor and fallsThe lower surface of field layer (34); Described the first conductive type semiconductor tagma (31) and the first conductive type semiconductor tagmaBuried regions (33) is arranged in the second conductive type semiconductor drift region (21).
2. a kind of high tension apparatus according to claim 1, is characterized in that, described the second conductive type semiconductor driftDistrict (21) is arranged on the upper surface of the first conductive type semiconductor substrate (1).
3. a kind of high tension apparatus according to claim 2, is characterized in that, also comprises SOI substrate (2), described SOISubstrate (2) be arranged on the first conductive type semiconductor substrate (1) and the second conductive type semiconductor drift region (21) itBetween and be connected with the first conductive type semiconductor substrate (1) and the second conductive type semiconductor drift region (21) respectively.
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| CN108550628B (en) * | 2018-04-28 | 2021-10-22 | 桂林电子科技大学 | Power device with surface charge area structure |
| CN109166920B (en) * | 2018-07-26 | 2020-08-07 | 上海华虹宏力半导体制造有限公司 | N L DMOS device and process method |
| CN109148304A (en) * | 2018-09-04 | 2019-01-04 | 盛世瑶兰（深圳）科技有限公司 | A kind of transistor and preparation method thereof |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
| CN112349764A (en) * | 2019-08-08 | 2021-02-09 | 天津大学 | RESURF LDMOS device with field limiting ring structure |
| CN112002759A (en) * | 2020-08-20 | 2020-11-27 | 杰华特微电子（杭州）有限公司 | Lateral diffusion transistor and manufacturing method thereof |
| CN114695516B (en) * | 2022-03-02 | 2023-04-25 | 电子科技大学 | Semiconductor voltage-resistant layer structure |
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