CN107452794A - A kind of high pressure LDMOS LDMOS - Google Patents
A kind of high pressure LDMOS LDMOS Download PDFInfo
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- CN107452794A CN107452794A CN201610383800.5A CN201610383800A CN107452794A CN 107452794 A CN107452794 A CN 107452794A CN 201610383800 A CN201610383800 A CN 201610383800A CN 107452794 A CN107452794 A CN 107452794A
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- 238000005452 bending Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000012141 concentrate Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The invention provides a kind of high pressure LDMOS LDMOS, it is related to technical field of semiconductors, solves the problems, such as existing high-voltage LDMOS because electric field is concentrated and point discharge causes component failure.The high-voltage LDMOS includes：P type substrate；The high pressure N well regions being formed in P type substrate；At least two straight way regions that high pressure N well regions include being arranged in order in the first direction connect the transitional region in two straight way regions with the one end in straight way region；Formed with an interval region between two neighboring straight way region, interval region includes the first compartment formed along straight way zone boundary and the second compartment formed close to one end of transitional region, and the width of the second compartment in the first direction is more than the width of the first compartment in the first direction；Region in P type substrate in addition to high pressure N well regions is formed with p-well region.The solution of the present invention weakens electric field concentration effect, improves product reliability, improves the market competitiveness.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of high pressure lateral diffused metal oxide is partly led
Body LDMOS.
Background technology
LDMOS (Laterally Diffused Metal Oxide Semiconductor, horizontal proliferation metal oxygen
Compound semiconductor) it is the indispensable elemental device of Power IC (Integrated Circuit, integrated circuit), press
According to the pressure-resistant high pressure that can be divided into two kinds of low pressure, wherein espespecially the design of high-voltage LDMOS is more complicated.
High-voltage LDMOS chip is frequently used for power management chip, and input is usually 220Vac civil powers,
Therefore need device can be with high pressure resistant, silicon semiconductor device expects that high withstand voltage just needs long depletion region, consumption
The length in area to the greatest extent directly affects the conducting resistance of device again, and conducting resistance is bigger, and power consumption is bigger.Preferable device
Part is can be high pressure resistant and have low conducting resistance, common in the BCD techniques containing high-voltage LDMOS
Solution is to increase the channel width W of device, can thus obtain the conducting resistance Rdson that design needs.
It is generally necessary to W it is all bigger, will typically be more than 5000um, but for the resistance to voltage devices of 700V
For depletion region typically in 65um, so big ratio gap is typically the layout using finger-shaped on domain.
Pressure-resistant 700V LDMOS often appears in AC-DC AC-DC, LED driver LED
In the power management chip Power such as Driver IC, resistance to pressing depletion region length determines, if expecting low lead
The resistance that is powered just needs sufficiently long channel width to reduce conducting resistance Rdson, overlength channel width W's
High-voltage LDMOS generally use finger-shaped domain, but will be run into the place of finger electric field concentrate with
And the problem of point discharge and frequently result in component failure.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of high pressure LDMOS
LDMOS, solve in the prior art high-voltage LDMOS due to electric field concentrate and point discharge frequently result in
The problem of component failure.
In order to solve the above technical problems, embodiments of the invention provide a kind of high pressure lateral diffused metal oxide
Semiconductor LDMOS, including：
P type substrate；
The high pressure N well regions being formed in the P type substrate；
The high pressure N well regions include at least two straight way regions being arranged in order in the first direction and described
The one end in straight way region connects the transitional region in two straight way regions；
Include between the two neighboring straight way region formed with an interval region, the interval region along described
Between the first compartment and the second of one end formation of the close transitional region that straight way zone boundary is formed
Every part, wherein width of second compartment along the first direction is more than first compartment
Along the width of the first direction；
Region in the P type substrate in addition to the high pressure N well regions is formed with p-well region.
Wherein, the high-voltage LDMOS also includes：
The drain electrode being formed on the high pressure N well regions, the drain electrode include being respectively arranged at the straight way area
At least two first drain electrode parts in domain and the second drain electrode part for being arranged at the transitional region, it is two neighboring
The first drain electrode part is connected in the same side by the described second drain electrode part.
Wherein, the high-voltage LDMOS also includes：
It is formed on the high pressure N well regions, the depletion region set around the drain electrode.
Wherein, the transitional region, second compartment and the second drain electrode part include circular arc
Region, and the transitional region, second compartment and the circular arc bending side of the described second drain electrode part
To identical；
The depletion region forms two circular arc sectors around the described second drain electrode part, and the depletion region is close to institute
The arc radius for stating the second compartment is more than the arc radius of second compartment.
Wherein, the circular arc center of circle of second compartment is on the extended line on the depletion region border, and institute
State the first drain electrode portion boundary and the depletion region close to the point of contact of the circular arc of second compartment with
And the circular arc center of circle of second compartment is on the same line.
Wherein, the high-voltage LDMOS also includes：
It is formed at the grid of the high pressure N well regions and the contact area of the p-well region.
Wherein, the high-voltage LDMOS also includes：
It is formed on the p-well region, the source electrode closed on the grid.
Wherein, the high pressure N well regions and the p-well region inject the method shape that trap is pushed away with boiler tube by photoetching
Into.
Wherein, the depletion region is formed using selective oxidation LOCOS techniques；
The drain electrode injects to be formed using N+.
Wherein, the grid is formed using polycrystalline poly deposits, photoetching and etching technics；
The source electrode injects to be formed using N+.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
The high-voltage LDMOS of the embodiment of the present invention, including：P type substrate；The height being formed in P type substrate
Press N well regions；High pressure N well regions include at least two straight way regions being arranged in order in the first direction and straight
The one end in road region connects the transitional region in two straight way regions；Formed with one between two neighboring straight way region
Interval region, interval region include the first compartment formed along straight way zone boundary and close to transitional regions
One end formed the second compartment, wherein the width of the second compartment in the first direction be more than first between
Every width partly in the first direction；Region in P type substrate in addition to high pressure N well regions is formed with p-well region.
So, by optimizing the domains of high pressure N well regions so that the second compartment newly increased is p-well region,
The position of original P/N knot is changed with area, electric field concentration effect is weakened, improves product reliability,
Improve the market competitiveness.Solve in the prior art high-voltage LDMOS due to electric field concentrate and tip put
Electricity frequently results in the problem of component failure.
Brief description of the drawings
Fig. 1 is the structural representation of existing high-voltage LDMOS；
Fig. 2 is the electric field effect schematic diagram of existing high-voltage LDMOS；
Fig. 3 is the structural representation of high-voltage LDMOS of the present invention；
Fig. 4 is the electric field effect schematic diagram of high-voltage LDMOS of the present invention；
Fig. 5 is the structural representation of one second compartment of high-voltage LDMOS of the present invention；
Fig. 6 is the structural representation of another second compartment of high-voltage LDMOS of the present invention；
Fig. 7 is the structural representation of another second compartment of high-voltage LDMOS of the present invention；
Fig. 8 is the first pass stage profile of high-voltage LDMOS of the present invention；
Fig. 9 is the second procedure stage profile of high-voltage LDMOS of the present invention；
Figure 10 is the 3rd flow stages profile of high-voltage LDMOS of the present invention；
Figure 11 is the 4th flow stages profile of high-voltage LDMOS of the present invention.
Description of reference numerals：
1- high pressure N well regions, 11- straight ways region, 12- transitional regions, the compartments of 13- first, 14- second
Compartment, the drain electrodes of 21- first part, the drain electrodes of 22- second part, 3- depletion regions.
Embodiment
To make the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with attached
Figure and specific embodiment are described in detail.
The high-voltage LDMOS of the embodiment of the present invention, by optimize HVNW (High Voltage N Well,
High pressure N well regions) domain, the effect of electric field concentration is improved, improves product reliability.
As shown in fig. 3 to 7, the high pressure LDMOS LDMOS of the embodiment of the present invention,
Including：
P type substrate；
The high pressure N well regions 1 being formed in the P type substrate；
The high pressure N well regions 1 include at least two straight way regions 11 that are arranged in order in the first direction and
The one end in the straight way region 11 connects the transitional region 12 in two straight way regions 11；
Include edge formed with an interval region, the interval region between the two neighboring straight way region 11
The first compartment 13 and one end of the close transitional region 12 that the border of straight way region 11 is formed
The second compartment 14 formed, wherein width of second compartment 14 along the first direction is big
In width of first compartment 13 along the first direction；
Region in the P type substrate in addition to the high pressure N well regions is formed with p-well region.
As shown in Figure 1, 2, the high pressure N well regions HVNW of existing high-voltage LDMOS uses finger-shaped cloth
During office, occur that electric field is concentrated and the problem of point discharge in the place of finger.
And the high-voltage LDMOS of the embodiment of the present invention, by the domain for optimizing high pressure N well regions 1 so that new
Increased second compartment 14 is PW (P Well, p-well region), that is, changes original P/N knots
Position with area, silicon device breakdown is exactly to occur at PN junction, and except the second compartment 14 changed
Other electric fields keep original effect outside region.The high-voltage LDMOS of the embodiment of the present invention, by optimizing electric field
The HVNW domains of concentrated area, weaken electric field concentrated area on the premise of chip area is not changed
Electric field concentration effect, improves product reliability, improves the market competitiveness.Solve high in the prior art
LDMOS is pressed due to the problem of electric field is concentrated and point discharge frequently results in component failure.
Preferably, as shown in figure 3, the high-voltage LDMOS of the embodiment of the present invention can also include：It is formed at
Drain electrode on the high pressure N well regions 1, the drain electrode include being respectively arranged at the straight way region 11 extremely
Few two first drain electrode parts 21 and the second drain electrode part 22 for being arranged at the transitional region 12, it is adjacent
Two first drain electrode parts 21 are connected in the same side by the described second drain electrode part 22.
Now, drain D rain is similar to high pressure N well regions 1, including at least two first drain electrode parts 21 and
Connect the second drain electrode part 22 of two neighboring first drain electrode part 21.Drain can access high pressure.
Preferably, the high-voltage LDMOS of the embodiment of the present invention can also include：It is formed at the high pressure N
On well region 1, around the depletion region 3 of the drain electrode setting.
Now, by the layout of similar finger-shaped, the length of depletion region 3 is effectively increased, is meeting resistance to height
There is low conducting resistance on the basis of pressure.And as shown in figure 4, after Drain access high pressures, by the
The acting on of two compartments 14 weakens the electric field of electric field concentrated area on the premise of not changing chip area
Concentration effect so that the electric-field intensity in source region finger Source FG regions weakens, and improve device can
By property.
Wherein, Fig. 3, the structure shown in 4 be by taking two straight way regions 11 as an example, and high pressure resistant in order to meet
Demand, the W of actual chips product will typically exceed 5000um, therefore, the high pressure of the embodiment of the present invention
The settable longer straight way regions 11 of LDMOS, may also comprise multiple straight way regions 11, that is, occur multiple
Finger.
Preferably, the transitional region 12, second compartment 14 and the second drain electrode part 22
Include circular arc sector, and the transitional region 12, second compartment 14 and the described second drain electrode
The circular arc bending direction of part 22 is identical；
The depletion region 3 forms two circular arc sectors, the depletion region around the described second drain electrode part 22
3 close to second compartment 14 arc radius be more than second compartment 14 arc radius.
Now, arc structure realizes the rounding off of device each several part, ensure that being uniformly distributed for electric field,
Improve the stability of device architecture.
Further, extension of the circular arc center of circle of second compartment 14 on the border of depletion region 3
On line, and the border of the first drain electrode part 21 and the depletion region 3 are close to second compartment
The point of contact of 14 circular arc and the circular arc center of circle of second compartment 14 are on the same line.
As shown in figure 5, the circular arc center of circle of the second compartment 14 includes c1, c2, the first drain electrode part 21
Border L3 and depletion region 3 close to the point of contact of the circular arc of the second compartment 14 be m1, the first drain portion
Points 21 border L4 is m2 close to the point of contact of the circular arc of the second compartment 14 with depletion region 3.
Here, c1 is on the extended line L1 on the border of depletion region 3, extended lines of the c2 on the border of depletion region 3
On L2, and m1, m2, c1 and c2 are on the same line.
Now, by the position constraint relation between device each several part, the convenience and device of production are improved
Regularity, improve the market competitiveness.
Wherein, the distance between whole depletion region AA is A=La+Lb, and Lb is the second compartment 14
Arc radius, the Lb that can preferably make La be equal to 2~4 times.
It should be noted that the structure of the second compartment 14 shown in Fig. 5 is only a kind of preferable realization
Mode, the structure of the second compartment 14 of the embodiment of the present invention can also use its other party as shown in Figure 6,7
Formula is realized, is not illustrated one by one herein.
Preferably, the high-voltage LDMOS of the embodiment of the present invention can also include：It is formed at the high pressure N
The grid of well region 1 and the contact area of the p-well region.It is formed on the p-well region, with the grid
The source electrode closed on.
Further, the high pressure N well regions 1 and the p-well region can be injected by photoetching pushes away trap with boiler tube
Method formed.The depletion region 3 can be formed using selective oxidation LOCOS techniques；The drain electrode can
Inject to be formed using N+.The grid can use polycrystalline poly deposits, photoetching and etching technics to be formed；Institute
Stating source electrode can inject to be formed using N+.
The technological process to the high-voltage LDMOS of the embodiment of the present invention is illustrated below below：
1) on the substrate Psub of the crystal orientation 80ohm.cm resistivity of p-type 100, first pass through photoetching injection with
The method that boiler tube pushes away trap forms HVNW regions and PW regions.Device profile structure such as Fig. 8 institutes of formation
Show.
2) FOX is formed on HVNW by LOCOS technique, as depletion region 3.The device of formation
Part cross-section structure is as shown in Figure 9.
3) polycrystalline poly deposits, photoetching, etching are carried out in the region that HVNW and PW is contacted, is formed
Grid G ate regions.The device profile structure of formation is as shown in Figure 10.
4) Drain contacts N+ injection is carried out on HVNW, forms drain D rain；It is enterprising in PW
Row source S ource N+ inject, and form source S ource.The device profile structure of formation is as shown in figure 11,
Wherein A is depletion region 3, and B is Drain contact areas, and S＆G is source electrode and grid.Here A, B with
A, B are corresponding relation in Fig. 5.
To sum up, the high-voltage LDMOS of the embodiment of the present invention, by optimizing HVNW domains, releive
HVNW improves electric field concentration effect, improving product can with PW PN junction Interface electric field intensity
By property, product competitiveness in the market is improved.Solve in the prior art high-voltage LDMOS due to electric field concentrate
And point discharge frequently results in the problem of component failure.
Described above is the preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
- A kind of 1. high pressure LDMOS LDMOS, it is characterised in that including：P type substrate；The high pressure N well regions being formed in the P type substrate；The high pressure N well regions include at least two straight way regions being arranged in order in the first direction and described The one end in straight way region connects the transitional region in two straight way regions；Include between the two neighboring straight way region formed with an interval region, the interval region along described Between the first compartment and the second of one end formation of the close transitional region that straight way zone boundary is formed Every part, wherein width of second compartment along the first direction is more than first compartment Along the width of the first direction；Region in the P type substrate in addition to the high pressure N well regions is formed with p-well region.
- 2. high-voltage LDMOS according to claim 1, it is characterised in that the high-voltage LDMOS Also include：The drain electrode being formed on the high pressure N well regions, the drain electrode include being respectively arranged at the straight way area At least two first drain electrode parts in domain and the second drain electrode part for being arranged at the transitional region, it is two neighboring The first drain electrode part is connected in the same side by the described second drain electrode part.
- 3. high-voltage LDMOS according to claim 2, it is characterised in that the high-voltage LDMOS Also include：It is formed on the high pressure N well regions, the depletion region set around the drain electrode.
- 4. high-voltage LDMOS according to claim 3, it is characterised in that the transitional region, Second compartment and the second drain electrode part include circular arc sector, and the transitional region, institute It is identical with the circular arc bending direction of the described second drain electrode part to state the second compartment；The depletion region forms two circular arc sectors around the described second drain electrode part, and the depletion region is close to institute The arc radius for stating the second compartment is more than the arc radius of second compartment.
- 5. high-voltage LDMOS according to claim 4, it is characterised in that second spacer portion The circular arc center of circle divided is on the extended line on the depletion region border, and the first drain electrode portion boundary and institute Depletion region is stated close to the point of contact of the circular arc of second compartment and the circular arc of second compartment The center of circle is on the same line.
- 6. high-voltage LDMOS according to claim 1, it is characterised in that the high-voltage LDMOS Also include：It is formed at the grid of the high pressure N well regions and the contact area of the p-well region.
- 7. high-voltage LDMOS according to claim 6, it is characterised in that the high-voltage LDMOS Also include：It is formed on the p-well region, the source electrode closed on the grid.
- 8. high-voltage LDMOS according to claim 1, it is characterised in that the high pressure N well regions The method for pushing away trap with boiler tube by photoetching injection with the p-well region is formed.
- 9. high-voltage LDMOS according to claim 3, it is characterised in that the depletion region uses Selective oxidation LOCOS techniques are formed；The drain electrode injects to be formed using N+.
- 10. high-voltage LDMOS according to claim 7, it is characterised in that the grid uses more Brilliant poly deposits, photoetching and etching technics are formed；The source electrode injects to be formed using N+.
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Application publication date: 20171208 |