CN110459599A - Longitudinal floating field plate device and manufacturing method with buried layer - Google Patents

Longitudinal floating field plate device and manufacturing method with buried layer Download PDF

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Publication number
CN110459599A
CN110459599A CN201910819950.XA CN201910819950A CN110459599A CN 110459599 A CN110459599 A CN 110459599A CN 201910819950 A CN201910819950 A CN 201910819950A CN 110459599 A CN110459599 A CN 110459599A
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field plate
floating field
buried layer
conduction type
type semiconductor
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CN110459599B (en
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章文通
何俊卿
杨昆
王睿
张森
乔明
张波
李肇基
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Abstract

The present invention provides a kind of longitudinal floating field plate device and manufacturing method with buried layer, it include: buried layer, first conductive type semiconductor substrate, the first conduction type well region, the first conductive type semiconductor contact zone, the second conduction type drift region, the second conduction type well region, the second conductive type semiconductor contact zone, first medium oxide layer, second medium oxide layer, third dielectric oxide, floating field plate polysilicon electrode, control gate polysilicon electrode, metal strip；First medium oxide layer and floating field plate polysilicon electrode constitute longitudinal floating field plate, the present invention is according to the structure and process characteristic of longitudinal floating field plate, the buried layer that depth reaches 3-20 μm is introduced in the second conduction type drift region of device or the first conductive type semiconductor substrate, and the buried layer RESURF technology can be fully compliant with existing RESURF technology, drift region electric field is further modulated, the ratio conducting resistance of device is reduced.

Description

Longitudinal floating field plate device and manufacturing method with buried layer
Technical field
The invention belongs to power semiconductor fields, mainly propose a kind of longitudinal floating field plate device with buried layer and Its manufacturing method.
Background technique
Power semiconductor is due to the spies such as input impedance is high, loss is low, switching speed is fast, safety operation area is wide Property, it has been widely used in consumer electronics, computer and peripheral hardware, network communication, Electronic Special Equipment and instrument and meter, automobile electricity The many aspects such as son, LED display and electrical lighting.Device is easy to logical since source electrode, grid, drain electrode are all in chip surface Internal connection and other devices and circuit integration are crossed, is widely used in power integrated circuit.In order to overcome high conducting resistance The problem of, J.A.APPLES et al., which proposes RESURF (Reduced Surface Field), reduces surface field technology, extensive Applied in the design of device.It is introducing the opposite buried layer of doping type in drift region is the most commonly used RUSURF skill One of art.But the buried layer depth of existing device is both less than greatly 3 μm, limits and further uses to RUSURF technology.
Summary of the invention
The present invention is directed to the problem of background technique, proposes that a kind of longitudinal floating field plate device with buried layer is new Structure and its manufacturing method.
For achieving the above object, technical solution of the present invention is as follows:
A kind of longitudinal floating field plate device with buried layer, comprising: buried layer 01, the first conductive type semiconductor substrate 11, the first conduction type well region 12, the first conductive type semiconductor contact zone 13, the second conduction type drift region 21, second are led Electric type well region 22, the second conductive type semiconductor contact zone 23, first medium oxide layer 31, second medium oxide layer 32, Three dielectric oxides 33, floating field plate polysilicon electrode 41, control gate polysilicon electrode 42, metal strip 51；
Wherein, the second conduction type drift region 21 is located at 11 top of the first conductive type semiconductor substrate, the first conductive-type Type well region 12 is located at the left side of the second conduction type drift region 21, and the second conduction type well region 22 is located at the drift of the second conduction type The right side in area 21, the first conduction type contact zone 13 and the second conduction type contact zone 23 are located at the first conduction type well region 12 In, and heavy doping is all made of to reduce resistance；Second medium oxide layer 32 and third dielectric oxide 33 are located at device surface, control 42 left margin of gate polysilicon electrode processed is located on the left of the right margin of the second conductive type semiconductor contact zone 23, controls gate polysilicon 42 right margin of electrode is located on the right side of the left margin of the second conduction type drift region 21；First medium oxide layer 31 and floating field plate are more Crystal silicon electrode 41 constitutes longitudinal floating field plate, and first medium oxide layer 31 surrounds floating field plate polysilicon electrode 41, Zong Xiangfu Barnyard plate is distributed in entire second conduction type drift region 21, forms longitudinal floating field plate array；
Buried layer 01 is to carry out injection knot using slot after cutting to obtain, and longitudinal floating field plate is evenly distributed in In entire second conduction type drift region 21, buried layer 01 is evenly distributed in entire second conduction type drift region 21.
It is preferred that the depth of buried layer 01 is 3-20 μm.
It is preferred that longitudinal floating field plate is inserted into the first conductive type semiconductor substrate 11, buried layer 01 is second Conductive type semiconductor material.
It is preferred that longitudinal floating field plate is not inserted into the first conductive type semiconductor substrate 11, buried layer 01 is the One conductive type semiconductor material.
It is preferred that buried layer 01 is injection and the connection buried layer that knot is formed, or knot is not formed for injection The independent buried layer for being only enclosed in each longitudinal floating field plate bottom.
It is preferred that changing the Implantation Energy of buried layer 01, so that buried layer 01 is tightly attached to longitudinal floating field plate bottom Portion, or have apart from longitudinal floating field plate bottom 0-3 μm of distance.
It is preferred that the longitudinal direction floating field plate is obtained by once etching, a buried layer note is carried out after etching Enter, obtains single buried structure.
It is preferred that the longitudinal direction floating field plate is obtained by multiple etching, all carried out after etching every time primary Buried layer injection, obtains more buried structures.
It is preferred that passing through metal strip between the equidistant floating field plate polysilicon electrode 41 of source electrode and drain electrode 51 are connected.
The present invention also provides a kind of manufacturing methods of device, include the following steps:
Step 1: selection first kind conductive type semiconductor substrate 11；
Step 2: carrying out energetic ion and inject the second conductive type impurity, and high temperature promotes to form the drift of the second conduction type Area 21, or the second conduction type drift region 21 is obtained by extension；
Step 3: deep trouth is formed by photoetching and etching；
Step 4: buried layer impurity is injected by slot energetic ion；
Step 5: high temperature knot forms the buried layer 01 of connection；
Step 6: first medium oxide layer 31 is formed in deep trouth；
Step 7: deposit polycrystalline is simultaneously etched to silicon plane, forms floating field plate polysilicon electrode 41；
Step 8: energetic ion injects the first conductive type impurity and knot, forms the first conduction type well region 12, then lead to Energetic ion injects the second conductive type impurity and knot, forms the second conduction type well region 22；
Step 9: forming second medium oxide layer 32, re-form third dielectric oxide 33；
Step 10: depositing polysilicon simultaneously etches, and forms control gate polysilicon electrode 42；
Step 11: high energy ion implantation forms the first conductive type semiconductor contact zone 13 and contacts with the second conductive type semiconductor Area 23；
Step 12: etching third dielectric oxide 33 forms contact hole, then deposits and etch metal strip 51, forms surface Metal strip.
Further, the Cross Section Morphology of first medium oxide layer 31 and floating field plate polysilicon electrode 41 can be rectangle, It is also possible to other patterns such as circle, ellipse, hexagon；
Further, the longitudinal floating field plate array proposed can be applied to body silicon device, SOI device and IGBT etc. In the drift region of common devices.
The invention has the benefit that structure and process characteristic of the present invention according to longitudinal floating field plate, the of device The buried layer 01 that depth reaches 3-20 μm is introduced in two conduction type drift regions 21 or the first conductive type semiconductor substrate 11, and The buried layer RESURF technology can be fully compliant with existing RESURF technology, further modulates drift region electric field, reduces device Ratio conducting resistance.
Detailed description of the invention
Fig. 1 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 1；
Fig. 2 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 1；Wherein (a) device architecture Front view (b) drift region structure side view；
Fig. 3 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 2；Wherein (a) device architecture Front view (b) drift region structure side view；
Fig. 4 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 3；Wherein (a) device architecture Front view (b) drift region structure side view；
Fig. 5 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 4；Wherein (a) device architecture Front view (b) drift region structure side view；
Fig. 6 is longitudinal floating field plate device architecture schematic diagram with buried layer of embodiment 5；Wherein (a) device architecture Front view (b) drift region structure side view；
Fig. 7 (a) -7 (l) is the process flow diagram of device described in embodiment 1；
01 is buried layer, and 11 be the first conductive type semiconductor substrate, 12 be the first conduction type well region, 13 is first to lead Electric type semiconductor contact zone, 21 be the second conduction type drift region, 22 be the second conduction type well region, 23 is the second conductive-type Type semiconductor contact regions 31 are first medium oxide layer, 32 be second medium oxide layer, 33 be third dielectric oxide, 41 are Floating field plate polysilicon electrode, 42 are control gate polysilicon electrode, and 51 be metal strip.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
A kind of longitudinal floating field plate device with buried layer described in embodiment 1, it is as depicted in figs. 1 and 2, specific to wrap It includes:
It include: buried layer 01, the first conductive type semiconductor substrate 11, the first conduction type well region 12, the first conductive-type Type semiconductor contact regions 13, the second conduction type drift region 21, the second conduction type well region 22, the second conductive type semiconductor connect Touch area 23, first medium oxide layer 31, second medium oxide layer 32, third dielectric oxide 33, floating field plate polysilicon electrode 41, control gate polysilicon electrode 42, metal strip 51；
Wherein, the second conduction type drift region 21 is located at 11 top of the first conductive type semiconductor substrate, the first conductive-type Type well region 12 is located at the left side of the second conduction type drift region 21, and the second conduction type well region 22 is located at the drift of the second conduction type The right side in area 21, the first conduction type contact zone 13 and the second conduction type contact zone 23 are located at the first conduction type well region 12 In, and heavy doping is all made of to reduce resistance；Second medium oxide layer 32 and third dielectric oxide 33 are located at device surface, control 42 left margin of gate polysilicon electrode processed is located on the left of the right margin of the second conductive type semiconductor contact zone 23, controls gate polysilicon 42 right margin of electrode is located on the right side of the left margin of the second conduction type drift region 21；First medium oxide layer 31 and floating field plate are more Crystal silicon electrode 41 constitutes longitudinal floating field plate, and first medium oxide layer 31 surrounds floating field plate polysilicon electrode 41, Zong Xiangfu Barnyard plate is distributed in entire second conduction type drift region 21, forms longitudinal floating field plate array；
Buried layer 01 is to carry out injection knot using slot after cutting to obtain, and longitudinal floating field plate is evenly distributed in In entire second conduction type drift region 21, buried layer 01 is evenly distributed in entire second conduction type drift region 21.
In the present embodiment, longitudinal floating field plate is not inserted into the first conductive type semiconductor substrate 11, so buried layer 01 is First conductive type semiconductor material.
Its basic functional principle is as follows: by taking the first conductive type semiconductor material is p-type as an example, as gate bias voltage Vg When greater than threshold voltage, there is inversion-layer electrons, In close to the surface of second medium oxide layer 32 in the first conduction type well region 12 Under the action of drain terminal bias voltage Vd, electronics is moved along the gap of longitudinal floating field plate from source to drain terminal.Due to floating The current potential of field plate polysilicon electrode 41 be higher than the second conduction type of left side drift region 21, the second of longitudinal floating field plate left-hand face Inversion layer will occur in conduction type drift region, increase electron concentration.When gate bias voltage Vg is 0, the drift of the second conduction type The PN junction of area 21 and the first conduction type well region 12 and the first conductive type semiconductor substrate 11 composition is moved in backward voltage Vd Start to exhaust under effect.The current potential of floating field plate polysilicon electrode 41 is higher than lower than its second conduction type drift region 21 of right side First conductive type semiconductor substrate 11, while depletion region is introduced in N-type drift region and P type substrate.Present invention introduces depth Buried layer 01 can advanced optimize charge balance, and modulated electric fields distribution can improve drift under conditions of keeping pressure resistance constant Conducting resistance is compared in area's doping concentration, reduction.
As shown in fig. 7, be the process flow diagram of the embodiment of the present invention 1, specifically includes the following steps:
Step 1: selection first kind conductive type semiconductor substrate 11, as shown in Fig. 7 (a)；
Step 2: carrying out energetic ion and inject the second conductive type impurity, and high temperature promotes to form the drift of the second conduction type Area 21, or the second conduction type drift region 21 is obtained by extension, as shown in Fig. 7 (b)；
Step 3: deep trouth being formed by photoetching and etching, as shown in Fig. 7 (c)；
Step 4: through-hole slot energetic ion injects buried layer impurity, as shown in Fig. 7 (d)；
Step 5: high temperature knot forms the buried layer 01 of connection, as shown in Fig. 7 (e)；
Step 6: first medium oxide layer 31 is formed in deep trouth, as shown in Fig. 7 (f)；
Step 7: deposit polycrystalline is simultaneously etched to silicon plane, floating field plate polysilicon electrode 41 is formed, as shown in Fig. 7 (g)；
Step 8: energetic ion injects the first conductive type impurity and knot, forms the first conduction type well region 12, then lead to Energetic ion injects the second conductive type impurity and knot, the second conduction type well region 22 is formed, shown in Fig. 7 (h)；
Step 9: forming second medium oxide layer 32, third dielectric oxide 33 is re-formed, such as Fig. 7 (i)；
Step 10: depositing polysilicon simultaneously etches, and control gate polysilicon electrode 42 is formed, such as Fig. 7 (j)；
Step 11: high energy ion implantation forms the first conductive type semiconductor contact zone 13 and contacts with the second conductive type semiconductor Area 23, as shown in Fig. 7 (k)；
Step 12: etching third dielectric oxide 33 forms contact hole, then deposits and etch metal strip 51, forms surface Metal strip, as shown in Fig. 7 (l).
It is to be noted that
A kind of manufacturing method, the second conduction type drift region formed by high energy ion implantation and knot in step 2 21 can also be obtained by the method for extension；
A kind of manufacturing method, the first conduction type well region as obtained from high energy ion implantation and knot in step 6 12 and the second conduction type well region 22, it can also be formed by the high energy ion implantation and activation of multiple different-energy；
A kind of manufacturing method, thermally grown obtained second medium oxide layer 32 and third are medium oxidizing in step 7 Layer 33 can also be obtained by depositing and etching.
Preferably, the depth of buried layer 01 is 3-20 μm.
Preferably, change the Implantation Energy of buried layer 01, so that buried layer 01 is tightly attached to longitudinal floating field plate bottom；
Preferably, longitudinal floating field plate is obtained by once etching, and a buried layer injection is carried out after etching, is obtained Single buried structure.
Preferably, longitudinal floating field plate is obtained by multiple etching, all carries out a buried layer note after etching every time Enter, obtains more buried structures.
Preferably, pass through 51 phase of metal strip between the equidistant floating field plate polysilicon electrode 41 of source electrode and drain electrode Even.
Embodiment 2
As shown in figure 3, be embodiment 2 a kind of longitudinal floating field plate device structure schematic diagram with buried layer, this example with Embodiment 1 the difference is that, it is described longitudinal direction floating field plate depth increase, be inserted into the first conductive type semiconductor substrate 11 In, buried layer 01 is the second conductive type semiconductor material, and working principle is substantially the same manner as Example 1.
Embodiment 3
As shown in figure 4, be embodiment 3 a kind of longitudinal floating field plate device structure schematic diagram with buried layer, this example with Embodiment 1 the difference is that, the buried layer 01 is to be injected after cutting using slot, is not carried out Knot, being formed by is the independent buried layer for being enclosed in floating field plate bottom longitudinally in each, working principle and the basic phase of embodiment 1 Together.
Embodiment 4
As shown in figure 5, be embodiment 4 a kind of longitudinal floating field plate device structure schematic diagram with buried layer, this example with Embodiment 1 the difference is that, the Implantation Energy of the buried layer 01 increases, so that being formed by buried layer 01 apart from longitudinal direction 0-3 μm of distance is arranged at floating field plate bottom, and working principle is substantially the same manner as Example 1.
Embodiment 5
As shown in fig. 6, be embodiment 5 a kind of longitudinal floating field plate device structure schematic diagram with buried layer, this example with Embodiment 1 the difference is that, the longitudinal direction floating field plate is obtained by twice etching, is all carried out after etching every time primary Buried layer injection, then carries out a knot again, obtains double-buried structure, further enhance the effect of RESURF technology, work Principle is substantially the same manner as Example 1.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention All equivalent modifications or change, should be covered by the claims of the present invention.

Claims (10)

1. a kind of longitudinal floating field plate device with buried layer, characterized by comprising: buried layer (01), the first conduction type Semiconductor substrate (11), the first conduction type well region (12), the first conductive type semiconductor contact zone (13), the second conduction type Drift region (21), the second conduction type well region (22), the second conductive type semiconductor contact zone (23), first medium oxide layer (31), second medium oxide layer (32), third dielectric oxide (33), floating field plate polysilicon electrode (41), control gate polycrystalline Silicon electrode (42), metal strip (51)；
Wherein, the second conduction type drift region (21) is located above the first conductive type semiconductor substrate (11), the first conductive-type Type well region (12) is located at the left side of the second conduction type drift region (21), and the second conduction type well region (22) is located at the second conductive-type It is conductive that the right side of type drift region (21), the first conduction type contact zone (13) and the second conduction type contact zone (23) are located at first In type well region (12), and heavy doping is all made of to reduce resistance；Second medium oxide layer (32) and third dielectric oxide (33) it is located at device surface, control gate polysilicon electrode (42) left margin is located at the second conductive type semiconductor contact zone (23) On the left of right margin, control gate polysilicon electrode (42) right margin is located on the right side of the left margin of the second conduction type drift region (21)； First medium oxide layer (31) and floating field plate polysilicon electrode (41) constitute longitudinal floating field plate, and first medium oxide layer (31) floating field plate polysilicon electrode (41) are surrounded, longitudinal floating field plate is distributed in entire second conduction type drift region (21) In, form longitudinal floating field plate array；
Buried layer (01) is to carry out injection knot using slot after cutting to obtain, and longitudinal floating field plate is evenly distributed in whole In a second conduction type drift region (21), buried layer (01) is evenly distributed in entire second conduction type drift region (21).
2. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: buried layer (01) Depth is 3-20 μm.
3. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: longitudinal floating field plate It is inserted into the first conductive type semiconductor substrate (11), buried layer (01) is the second conductive type semiconductor material.
4. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: longitudinal floating field plate It is not inserted into the first conductive type semiconductor substrate (11), buried layer (01) is the first conductive type semiconductor material.
5. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: buried layer (01) is Inject and connection buried layer that knot is formed, or injection not knot formed be only enclosed in each longitudinal floating field plate bottom Independent buried layer.
6. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: change buried layer (01) Implantation Energy, so that buried layer (01) is tightly attached to longitudinal floating field plate bottom, or apart from longitudinal floating field plate bottom There is 0-3 μm of distance.
7. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: the longitudinal direction floating Field plate is obtained by once etching, and a buried layer injection is carried out after etching, obtains single buried structure.
8. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: the longitudinal direction floating Field plate is obtained by multiple etching, is all carried out a buried layer injection after etching every time, is obtained more buried structures.
9. longitudinal floating field plate device according to claim 1 with buried layer, it is characterised in that: apart from source electrode and leakage It is connected between extremely equidistant floating field plate polysilicon electrode (41) by metal strip (51).
10. the manufacturing method of device described in claim 1 to 9 any one, it is characterised in that include the following steps:
Step 1: selection first kind conductive type semiconductor substrate (11)；
Step 2: carrying out energetic ion and inject the second conductive type impurity, and high temperature promotes to form the second conduction type drift region (21), or by extension the second conduction type drift region (21) is obtained；
Step 3: deep trouth is formed by photoetching and etching；
Step 4: buried layer impurity is injected by slot energetic ion；
Step 5: high temperature knot forms the buried layer (01) of connection；
Step 6: forming first medium oxide layer (31) in deep trouth；
Step 7: deposit polycrystalline is simultaneously etched to silicon plane, is formed floating field plate polysilicon electrode (41)；
Step 8: energetic ion injects the first conductive type impurity and knot, forms the first conduction type well region (12), then logical height Energy the second conductive type impurity of ion implanting and knot form the second conduction type well region (22)；
Step 9: being formed second medium oxide layer (32), re-form third dielectric oxide (33)；
Step 10: depositing polysilicon simultaneously etches, and is formed control gate polysilicon electrode (42)；
Step 11: high energy ion implantation forms the first conductive type semiconductor contact zone (13) and the second conductive type semiconductor contact zone (23)；
Step 12: etching third dielectric oxide (33) forms contact hole, then deposits and etches metal strip (51), forms surface Metal strip.
CN201910819950.XA 2019-08-31 2019-08-31 Longitudinal floating field plate device with deep buried layer and manufacturing method Expired - Fee Related CN110459599B (en)

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