CN111969042A - Lateral high-voltage device with high-aspect-ratio internal super junction and manufacturing method thereof - Google Patents

Lateral high-voltage device with high-aspect-ratio internal super junction and manufacturing method thereof Download PDF

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CN111969042A
CN111969042A CN202010887963.3A CN202010887963A CN111969042A CN 111969042 A CN111969042 A CN 111969042A CN 202010887963 A CN202010887963 A CN 202010887963A CN 111969042 A CN111969042 A CN 111969042A
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conductive type
region
oxide layer
dielectric oxide
drift region
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章文通
祖健
朱旭晗
何乃龙
乔明
李肇基
张波
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University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
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University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
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Abstract

The invention provides a transverse high-voltage device with a high-aspect-ratio internal super junction and a manufacturing method thereof, wherein the transverse high-voltage device comprises: the first conductive type drift region and the deep groove region are injected from the bottom of the deep groove to form a second conductive type region connected with a second conductive type substrate, a first conductive type well region, a second conductive type well region, a heavily doped region, a control gate polycrystalline silicon electrode, a first dielectric oxide layer and a second dielectric oxide layer, wherein the first conductive type well region and the second conductive type well region are positioned on two sides of the drift region, and the control gate polycrystalline silicon electrode, the first dielectric oxide layer and the second dielectric oxide layer are. The deep groove is obtained by Hard Mask layer Hard Mask protection etching, then a second conduction type region obtained by groove bottom injection and a drift region at two sides of the groove bottom form an internal super junction together, charge balance is maintained, the internal field of the device is optimized, and an internal low-resistance path is provided; the width and the depth of the super junction strip are determined by the etching width and the depth of the deep groove, and the in-vivo super junction structure with high depth-to-width ratio can be obtained. The structure provided by the invention optimizes the internal field, improves the voltage resistance of the device, provides an internal low-resistance path and further reduces the specific on resistance.

Description

Lateral high-voltage device with high-aspect-ratio internal super junction and manufacturing method thereof
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a transverse high-voltage device with a high-aspect-ratio internal super junction and a manufacturing method thereof.
Background
Lateral power semiconductors have an extremely wide range of applications as the core of power integrated circuits, and various technologies such as RESURF and super junction and their improvements are being proposed to improve their performance, wherein super junction is widely applied to lateral devices as an invention having revolutionary significance in the field of power semiconductors. However, the conventional transverse super junction is limited by the limits of injection energy and photoresist thickness, and can only be formed on the surface of the device, so that the functions of optimizing the surface field of the device, improving voltage resistance and providing a surface low-resistance path are achieved, the electric field and the conductive capacity in the deep part of the drift region of the device cannot be optimized, and the super junction on the surface of the device is inevitably introduced into the surface high field to reduce the reliability of the device. Meanwhile, the traditional super junction is formed by surface thick resist blocking and high-energy injection, and when the super junction strip width is close to a submicron level, the minimum strip width is limited by the preparation of high aspect ratio photoresist.
Disclosure of Invention
The invention provides a transverse high-voltage device with a high-aspect-ratio internal super junction and a manufacturing method thereof aiming at the problems in the background technology, the width of a super junction strip is determined by the width of a groove blocked and etched by Hard Mask, the strip width is narrower compared with the traditional super junction, meanwhile, the super junction is introduced into the deep part of a drift region of the device through high-energy injection in the groove, the optimization of the electric field and the conductive capability in the deep part of the drift region of the device is realized, the surface field of the device is reduced, and the width of the super junction strip is not limited by the preparation of photoresist with the high-aspect-ratio.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a lateral high-voltage device having a high aspect ratio internal superjunction, comprising:
a second conductive type substrate 21, a first conductive type drift region 11, a first conductive type well region 12 and a second conductive type well region 22, a first dielectric oxide layer 31, a groove bottom second conductive type region 23, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a control gate polysilicon 41, a heavily doped second conductive type region 25 and a heavily doped first conductive type region 13;
wherein the first conductive type drift region 11 is located above the second conductive type substrate 21, the second conductive type well region 22 is located on the left side in the first conductive type drift region 11 and connected to the second conductive type substrate 21, the first conductive type well region 12 is located on the right side in the first conductive type drift region 11, the first dielectric oxide layer 31 is located in the first conductive type drift region 11 and filled with deep trenches, the second dielectric oxide layer 32 is located above the first conductive type drift region 11, the trench bottom second conductive type region 23 is located below the first dielectric oxide layer 31 in the first conductive type drift region 11 and connected to the second conductive type substrate 21, the third dielectric oxide layer 33 covers part of the upper portion of the second conductive type well region 22 and extends to the upper portion of the first conductive type drift region 11, the control gate polysilicon 41 is located above the third dielectric oxide layer 33 and covers part of the second dielectric oxide layer 32, the heavily doped first conductivity type region 13 is located in the first conductivity type well region 12 and the second conductivity type well region 22, and the heavily doped second conductivity type region 25 is tangent to the heavily doped first conductivity type region 13 in the second conductivity type well region 22;
the second conductivity type region 23 at the bottom of the trench and the first conductivity type drift region 11 at the bottom of the trench form a super junction structure and maintain charge balance.
Preferably, the first conductivity type drift region 11 is formed by epitaxy or by implantation of a push junction.
Preferably, the method comprises the following steps: the drift region deep grooves are periodically distributed along the width direction of the device and are obtained by using a Hard Mask layer Hard Mask to block etching.
Preferably, the second conductivity type region 23 is formed by a plurality of different energy implantations of the groove bottom and finally connected to the second conductivity type substrate 21.
Preferably, the second conductive type substrate 21 is an SOI substrate or a sapphire substrate.
Preferably, the semiconductor material is Si or SiC material, and/or the first dielectric oxide layer 31 filling the deep trench is a high-K or low-K dielectric material.
The invention also provides a manufacturing method of the transverse high-voltage device with the high-aspect-ratio internal super junction, which comprises the following steps:
step 1: epitaxially growing or implanting a push junction above the second conductive type substrate 21 to obtain a first conductive type drift region 11;
step 2: implanting the first conductivity type well region 12 and the second conductivity type well region 22;
and step 3: etching the deep groove by using a Hard Mask layer Hard Mask to block;
and 4, step 4: the groove bottom is implanted with the groove bottom second conductive type region 23 for multiple times and connected with the second conductive type substrate 21;
and 5: depositing a first dielectric oxide layer 31 to fill the deep groove;
step 6: growing a second dielectric oxide layer 32 by thermal oxidation;
and 7: growing a third dielectric oxide layer 33 by thermal oxidation, and depositing and etching the control gate polysilicon 41;
and 8: the heavily doped first conductivity type region 13 and the heavily doped second conductivity type region 25 are implant activated.
Preferably, the Hard Mask layer Hard Mask in step 3 is replaced by a photoresist barrier etch.
Preferably, the distance between the two ends of the second conductive type region 23 of the trench bottom and the first and second conductive type well regions 12 and 22 can be reduced or increased according to the performance requirement of the device, so as to adjust the surface field and the on-resistance.
Preferably, the first conductive type is N-type doping, and the second conductive type is P-type doping; or the first conductive type is P-type doping, and the second conductive type is N-type doping.
The invention has the beneficial effects that: by introducing the deep groove injection mode, the super junction is introduced into the internal field of the optimized device deep in the drift region, the surface field of the device is reduced, the reliability of the device is improved, and an internal low-resistance path is provided to further reduce the specific on-resistance of the device. Meanwhile, the width of the super-junction strip depends on the width of a deep groove obtained by Hard Mask layer Hard Mask blocking etching, the super-junction with high depth-to-width ratio can be obtained, and the width-to-reduction ratio of the super-junction P strip is reduced as much as possible.
Drawings
Fig. 1 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction in embodiment 1;
fig. 2 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction in embodiment 2;
fig. 3 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction according to embodiment 3;
fig. 4 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction according to embodiment 4;
fig. 5 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction according to embodiment 5;
fig. 6 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction according to embodiment 6;
fig. 7 is a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction according to embodiment 7;
FIGS. 8(a) -8(h) are schematic process flow diagrams of the device described in example 1;
11 is a drift region of a first conductivity type, 12 is a well region of the first conductivity type, 13 is a heavily doped region of the first conductivity type, 21 is a substrate of a second conductivity type, 22 is a well region of the second conductivity type, 23 is a region of the second conductivity type at the bottom of the trench, 24 is a region of the second conductivity type at the sidewall, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, 41 is a control gate polysilicon, and 25 is a heavily doped region of the second conductivity type.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
Embodiment 1 provides a lateral high-voltage device having a high aspect ratio internal super junction, as shown in fig. 1, specifically including:
a second conductive type substrate 21, a first conductive type drift region 11, a first conductive type well region 12 and a second conductive type well region 22, a first dielectric oxide layer 31, a groove bottom second conductive type region 23, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a control gate polysilicon 41, a heavily doped second conductive type region 25 and a heavily doped first conductive type region 13;
wherein the first conductive type drift region 11 is located above the second conductive type substrate 21, the second conductive type well region 22 is located on the left side in the first conductive type drift region 11 and connected to the second conductive type substrate 21, the first conductive type well region 12 is located on the right side in the first conductive type drift region 11, the first dielectric oxide layer 31 is located in the first conductive type drift region 11 and filled with deep trenches, the second dielectric oxide layer 32 is located above the first conductive type drift region 11, the trench bottom second conductive type region 23 is located below the first dielectric oxide layer 31 in the first conductive type drift region 11 and connected to the second conductive type substrate 21, the third dielectric oxide layer 33 covers part of the upper portion of the second conductive type well region 22 and extends to the upper portion of the first conductive type drift region 11, the control gate polysilicon 41 is located above the third dielectric oxide layer 33 and covers part of the second dielectric oxide layer 32, the heavily doped first conductivity type region 13 is located in the first conductivity type well region 12 and the second conductivity type well region 22, and the heavily doped second conductivity type region 25 is tangent to the heavily doped first conductivity type region 13 in the second conductivity type well region 22;
the second conductivity type region 23 at the bottom of the trench and the first conductivity type drift region 11 at the bottom of the trench form a super junction structure and maintain charge balance.
As shown in fig. 8, a schematic process flow diagram of embodiment 1 of the present invention specifically includes the following steps:
step 1: epitaxially growing or implanting a push junction above the second conductive type substrate 21 to obtain a first conductive type drift region 11; as shown in fig. 8 (a);
step 2: implanting the first conductivity type well region 12 and the second conductivity type well region 22; as shown in fig. 8 (b);
and step 3: etching the deep groove by using a Hard Mask layer Hard Mask to block; as shown in fig. 8 (c);
and 4, step 4: bottom multiple implantation of a bottom second conductivity type region 23 and connection to the second conductivity type substrate 21; as shown in fig. 8 (d);
and 5: depositing a first dielectric oxide layer 31 to fill the deep groove; as shown in fig. 8 (e);
step 6: growing a second dielectric oxide layer 32 by thermal oxidation; as shown in fig. 8 (f);
and 7: growing a third dielectric oxide layer 33 by thermal oxidation, and depositing and etching the control gate polysilicon 41, as shown in fig. 8 (g);
and 8: the heavily doped first conductive type region 13 and the heavily doped second conductive type region 25 are implant activated as shown in fig. 8 (h).
Preferably, the first conductivity type drift region 11 is formed by epitaxy or implantation of a push junction, and the doping concentration and resistivity thereof are increased or decreased according to the size requirement of the on-resistance of the device.
Preferably, the deep grooves of the drift region are distributed periodically along the width direction of the device and staggered with the silicon layer, and the deep grooves are obtained by using a Hard Mask layer Hard Mask to block etching.
Preferably, the second conductivity type region 23 is formed by a plurality of different energy implantations of the groove bottom and finally connected to the second conductivity type substrate 21.
Preferably, the second conductive type substrate 21 is an SOI substrate or a sapphire substrate.
The same technology can be used in other lateral high-voltage devices such as LIGBT, and the semiconductor material can be used in new-generation semiconductor materials such as Si or SiC.
Preferably, in step 3, the Hard Mask layer Hard Mask may also be replaced by a thick photoresist to block etching, and the first dielectric oxide layer 31 filling the deep trench may also be other high-K or low-K dielectrics.
Example 2
As shown in fig. 2, which is a schematic structural view of the lateral high-voltage device with a high aspect ratio internal super junction in embodiment 2, on the basis of embodiment 1, after deep trench etching, two times of trench wall implantation are added to form trench wall second conductivity type regions 24 on both sides of the trench, and the doping concentration thereof maintains charge balance with the first conductivity type drift regions 11 on both sides of the trench, so that the surface electric field of the device can be further optimized, and the remaining operation principle and process steps are the same as those in embodiment 1.
Example 3
As shown in fig. 3, a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction in embodiment 3 is shown, and this example is different from embodiment 1 in that: the deep trench is etched and injected and then filled in a mode of depositing a trench wall second conductive type region 24, the charge balance is maintained with the first conductive type drift region on the two sides of the trench, the other process steps are completely consistent, and the working principle is basically the same as that of the embodiment 1.
Example 4
As shown in fig. 4, a schematic structural diagram of a lateral high-voltage device with a high aspect ratio internal super junction in embodiment 4 is different from embodiment 1 in that: the width of the deep groove is linearly reduced from the drain end to the source end, more first conduction type charges are introduced into the drain end, the substrate-assisted depletion effect is further restrained, and the electric field of the device is optimized. The rest of the manufacturing process and the working principle are consistent with the embodiment example 1.
Example 5
As shown in fig. 5, a schematic diagram of an epitaxial high-voltage lateral device with deep buried super junction in embodiment 5 is shown, and this example is different from embodiment 1 in that: the deep trenches are arranged separately, equidistantly and periodically, the trench bottom second conductive type region 23 implanted by the deep trenches is finally connected with the second conductive type substrate 21, and the filling medium 32 can be a dielectric oxide layer or other high-K or low-K medium, and the working principle of the deep trenches is basically the same as that of the embodiment 1.
Example 6
As shown in fig. 6, which is a schematic structural view of an epitaxial high-voltage lateral device with deep buried super junction in embodiment 6, a trench wall implantation is added on the basis of embodiment 5 to form a trench wall second conductivity type region 24 surrounding the deep trench, and the charge balance is maintained with the surrounding drift region of the first conductivity type, and the operation principle is basically the same as that of embodiments 1 and 5.
Example 7
As shown in fig. 7, which is a schematic structural diagram of an epitaxial high-voltage lateral device with a deep buried super junction in embodiment 7, on the basis of embodiment 1, when a deep trench is introduced at the source end, and a trench bottom second conductive type region 23 is implanted at the trench bottom, a trench bottom second conductive type region 23 is also introduced below the source end second conductive type region 22, which plays a role in optimizing the electric field and isolation below the source end well region, and the rest of the operation principle is the same as that in embodiment 1.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A lateral high-voltage device having a high aspect ratio internal superjunction, comprising:
the transistor comprises a second conductive type substrate (21), a first conductive type drift region (11), a first conductive type well region (12), a second conductive type well region (22), a first dielectric oxide layer (31), a groove bottom second conductive type region (23), a second dielectric oxide layer (32), a third dielectric oxide layer (33), control gate polysilicon (41), a heavily doped second conductive type region (25) and a heavily doped first conductive type region (13);
wherein the first conductive type drift region (11) is positioned above the second conductive type substrate (21), the second conductive type well region (22) is positioned on the left side in the first conductive type drift region (11) and connected with the second conductive type substrate (21), the first conductive type well region (12) is positioned on the right side in the first conductive type drift region (11), the first dielectric oxide layer (31) is positioned in the first conductive type drift region (11) to fill deep grooves, the second dielectric oxide layer (32) is positioned above the first conductive type drift region (11), the second conductive type region (23) is positioned below the first dielectric oxide layer (31) in the first conductive type drift region (11) and connected with the second conductive type substrate (21), the third dielectric oxide layer (33) covers part of the upper part of the second conductive type well region (22) and extends to the upper part of the first conductive type drift region (11), the control gate polysilicon (41) is positioned above the third dielectric oxide layer (33) and covers a part of the second dielectric oxide layer (32), the heavily doped first conductive type region (13) is positioned in the first conductive type well region (12) and the second conductive type well region (22), and the heavily doped second conductive type region (25) is tangent to the heavily doped first conductive type region (13) in the second conductive type well region (22);
the second conduction type region (23) at the bottom of the groove and the first conduction type drift region (11) at the bottom of the groove form a super junction structure and maintain charge balance.
2. The lateral high-voltage device with a high aspect ratio internal superjunction of claim 1, wherein: the drift region (11) of the first conductivity type is formed by means of epitaxy or implantation of a push junction.
3. The lateral high-voltage device with a high aspect ratio internal superjunction of claim 1, wherein: the drift region deep grooves are periodically distributed along the width direction of the device and are obtained by using a Hard Mask layer Hard Mask to block etching.
4. The lateral high-voltage device with a high aspect ratio internal superjunction of claim 1, wherein: the second conductivity type region (23) is formed by multiple different energy implantations of the trench bottom and is finally connected to the second conductivity type substrate (21).
5. The lateral high-voltage device with a high aspect ratio internal superjunction of claim 1, wherein: the second conductivity type substrate (21) is an SOI substrate or a sapphire substrate.
6. The lateral high-voltage device with a high aspect ratio internal superjunction of claim 1, wherein: the semiconductor material is Si or SiC material, and/or the first dielectric oxide layer (31) filling the deep trench is a high-K or low-K dielectric material.
7. The method of fabricating a lateral high-voltage device having a high aspect ratio internal superjunction according to any of claims 1 to 6, comprising the steps of:
step 1: epitaxially growing or injecting a push junction above a second conductive type substrate (21) to obtain a first conductive type drift region (11);
step 2: implanting a first conductivity type well region (12) and a second conductivity type well region (22);
and step 3: etching the deep groove by using a Hard Mask layer Hard Mask to block;
and 4, step 4: the groove bottom is implanted with a plurality of times into the groove bottom second conduction type region (23) and is connected with the second conduction type substrate (21);
and 5: depositing a first dielectric oxide layer (31) to fill the deep groove;
step 6: growing a second dielectric oxide layer (32) by thermal oxidation;
and 7: growing a third dielectric oxide layer (33) by thermal oxidation, and depositing and etching the control gate polysilicon (41);
and 8: the heavily doped first conductivity type region (13) and the heavily doped second conductivity type region (25) are implant activated.
8. The method of fabricating a lateral high-voltage device with a high aspect ratio internal superjunction according to claim 7, wherein: and in the step 3, the Hard Mask layer Hard Mask is replaced by photoresist to resist etching.
9. The high-aspect-ratio internal superjunction high-voltage lateral device of claim 1, wherein: the first conductive type is N-type doping, and the second conductive type is P-type doping; or the first conductive type is P-type doping, and the second conductive type is N-type doping.
CN202010887963.3A 2020-08-28 2020-08-28 Lateral high-voltage device with high-aspect-ratio internal super junction and manufacturing method thereof Pending CN111969042A (en)

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CN102769037A (en) * 2011-05-06 2012-11-07 汉磊科技股份有限公司 Structure for reducing surface electric field and LDMOS device
CN107768421A (en) * 2016-08-23 2018-03-06 新唐科技股份有限公司 Lateral double diffused metal oxide semiconductor element
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Publication number Priority date Publication date Assignee Title
US20070120187A1 (en) * 2003-05-13 2007-05-31 Cambridge Semiconductor Limited Lateral soi semiconductor device
CN102097480A (en) * 2010-12-22 2011-06-15 东南大学 N-type super-junction transverse double-diffusion metal oxide semiconductor tube
US20120273882A1 (en) * 2011-04-27 2012-11-01 Perumal Ratnam Shallow-trench cmos-compatible super junction device structure for low and medium voltage power management applications
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