CN111969043A - High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof - Google Patents

High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof Download PDF

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CN111969043A
CN111969043A CN202010888999.3A CN202010888999A CN111969043A CN 111969043 A CN111969043 A CN 111969043A CN 202010888999 A CN202010888999 A CN 202010888999A CN 111969043 A CN111969043 A CN 111969043A
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region
conduction type
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张波
朱旭晗
祖健
章文通
乔明
李肇基
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University of Electronic Science and Technology of China
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Abstract

The invention provides a high-voltage three-dimensional depletion super junction LDMOS and a manufacturing method thereof, and the high-voltage three-dimensional depletion super junction LDMOS comprises a second conduction type substrate, a first conduction type drift region, a first conduction type well region, a second conduction type well region, a first medium oxidation layer, a second conduction type buried layer, a second medium oxidation layer, and a first conduction type region and a second conduction type region which are periodically arranged to form a super junction; the second conduction type buried layer and the super junction structure are both located in the first conduction type drift region, wherein the super junction is located above the second conduction type buried layer and connected with the second conduction type buried layer; the second conduction type buried layer optimizes the surface electric field of the device in an off state, the second conduction type buried layer and the super-junction second conduction type region surround the super-junction first conduction type region on three sides to form a three-dimensional depletion super-junction structure Fin-SJ structure, the doping concentration of the first conduction type drift region and the super-junction first conduction type region is allowed to be improved, the super-junction structure provides a surface low-resistance path, and the specific on-resistance of the device is reduced.

Description

High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor process manufacturing, and particularly relates to a novel high-voltage three-dimensional depletion super-junction LDMOS device (Fin-SJ LDMOS device) and a manufacturing method thereof.
Background
The high-voltage LDMOS has been used as a core device in a power integrated circuit due to the characteristics of high input impedance, low loss, high switching speed, wide safe working area and easy integration, and is widely applied to various fields of mobile communication, automotive electronics, LED illumination and the like. In order to achieve the purpose, the existing commonly used technologies include a transverse super junction technology and a surface field reduction (RESURF) technology, and the transverse super junction technology and the RESURF technology are mutually depleted with a drift region in an off state to achieve the purposes of optimizing an electric field and increasing the doping concentration of the drift region, so that the specific on-resistance in an on state is reduced. However, the drift regions of the conventional super junction and RESURF technologies only have auxiliary depletion from the charge compensation layers on both sides, the improvement of the device performance is approaching the limit, how to further increase the compensation capability of the charge compensation layers, improve the doping concentration of the drift region, and further reduce the specific on-resistance while ensuring the withstand voltage is the core problem of device improvement.
Disclosure of Invention
Aiming at the defects of the background technology, the invention provides a novel high-voltage three-dimensional depletion super-junction LDMOS device (Fin-SJ LDMOS device) and a manufacturing method thereof, wherein the third-dimensional depletion is introduced on the basis of the traditional super-junction two-dimensional auxiliary depletion, the doping concentration of a surface conductive path is improved by forming a three-dimensional depletion Fin-SJ structure, and the specific on-resistance is further reduced.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a high-voltage three-dimensional depleted super junction LDMOS device, comprising:
a second conductive type substrate 21, a first conductive type drift region 11, a first conductive type well region 12 and a second conductive type well region 22, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a second conductive type buried layer 23, first conductive type regions 13 and second conductive type regions 24 which are periodically arranged, a heavily doped first conductive type region 14 and a heavily doped second conductive type region 25, and a control gate polysilicon 41;
wherein, the first conductive type well region 12 is located at the right side in the first conductive type drift region 11, the second conductive type well region 22 is located at the left side of the first conductive type drift region 11 and is tangent to the first conductive type drift region, and the second conductive type well region 22 is connected to the second conductive type substrate 21; a heavily doped first conductive type region 14 and a heavily doped second conductive type region 25 are arranged in the second conductive type well region 22, and a heavily doped first conductive type region 14 is arranged in the first conductive type well region 12; the first dielectric oxide layer 31 is located above the first conductive type drift region 11, and the second dielectric oxide layer 32 is located above the second conductive type well region 22 and partially extends above the first conductive type drift region 11;
the second conduction type buried layer 23 is located in the first conduction type drift region 11, the super junction structure formed by the first conduction type region 13 and the second conduction type region 24 is located above the second conduction type buried layer 23 and connected with the second conduction type buried layer 23, and the second conduction type buried layer 23 and the second conduction type region 24 surround the first conduction type region 13 in three directions to form a three-dimensional depleted super junction structure Fin-SJ structure.
Preferably, the first conductive type regions 13 and the second conductive type regions 24 alternately arranged periodically are formed by multiple implantations or a single implantation.
Preferably, the second-conductivity-type buried layer 23 and the first-conductivity-type region 13 and the second-conductivity-type region 24 forming the super junction structure are each implemented using photoresist blocking ion implantation.
Preferably, the first conductivity type region 13 and the second conductivity type region 24 forming the super junction structure are aligned with the second conductivity type buried layer 23 in the first conductivity type drift region 11, or are shorter than or longer than the second conductivity type buried layer 23.
Preferably, the second conductive-type buried layer 23 and the left ends of the first conductive-type region 13 and the second conductive-type region 24 are located below the gate polysilicon 41.
Preferably, first conductivity-type well region 12 and second conductivity-type well region 22 are obtained by one or more different energy implants.
Preferably, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
Preferably, the second conductivity type substrate 21 is a SOI or sapphire dielectric or semiconductor material substrate.
Preferably, the same drift region structure manufacturing method can be used for other high-voltage lateral devices such as LIGBT, and the semiconductor material used can be a novel material such as Si or SiC.
The invention also provides a manufacturing method of the high-voltage three-dimensional depletion super junction LDMOS device, which comprises the following steps:
step 1: injecting a push junction above the second conductive type substrate 21 to obtain a first conductive type drift region 11;
step 2: performing field oxidation on the basis of the structure in the step 1 to form a first dielectric oxide layer 31;
and step 3: a first conductive type well region 12 and a second conductive type well region 22 are respectively formed at the left end and the right end of the first conductive type drift region 11 by injection;
and 4, step 4: forming a second conductive type buried layer 23 by implanting a push junction using a resist barrier;
and 5: forming a second dielectric oxide layer 32 by thermal oxidation, and depositing and etching to form a control gate polysilicon 41;
step 6: forming the first conductive type region 13 and the second conductive type region 24 by implantation using a resist barrier;
and 7: the implant activates the heavily doped first conductivity type region 14 and the heavily doped second conductivity type region 25.
Preferably, the first conductivity type drift region 11 is obtained by epitaxy; or the step 4 and step 6 implantations precede step 2; or the super junction implantation of step 6 follows step 4 before step 5.
The invention has the beneficial effects that: according to the invention, the buried layer which is positioned below the super junction and connected with the super junction is introduced on the basis of the conventional super junction, the surface field distribution of the device is optimized before the super junction is added, the voltage resistance of the device is ensured, the second conductive type buried layer and the second conductive type region surround the first conductive type region on three sides to form a three-dimensional depletion Fin-SJ structure, the first conductive type region is subjected to auxiliary depletion from three directions, the doping concentration of the first conductive type region 13 is greatly improved, and the purpose of reducing the low specific on-resistance under the condition of ensuring that the voltage resistance is not reduced is realized.
Drawings
Fig. 1 is a schematic structural diagram of a high-voltage three-dimensional depletion super junction LDMOS device of embodiment 1 and a cross-sectional view thereof;
fig. 2 is a schematic structural diagram of a high-voltage three-dimensional depletion super junction LDMOS device of embodiment 2 and a cross-sectional view thereof;
fig. 3(a) and 3(b) are schematic structural diagrams of the high-voltage three-dimensional depletion super junction LDMOS device of embodiment 3;
fig. 4 is a schematic structural diagram of the high-voltage three-dimensional depletion super junction LDMOS device of embodiment 4;
fig. 5 is a schematic structural diagram of the high-voltage three-dimensional depletion super junction LDMOS device of embodiment 5;
fig. 6 is a top view of the high-voltage three-dimensional depleted superjunction LDMOS device of embodiment 6;
fig. 7(a) and 7(b) are top views of the high-voltage three-dimensional depleted superjunction LDMOS device structure of example 7;
fig. 8 is a top view of the high-voltage three-dimensional depletion super junction LDMOS device structure of embodiment 8;
FIG. 9 is a flow chart of the device fabrication process described in example 1;
FIG. 10(a) -FIG. 10(g) are schematic diagrams illustrating the fabrication of the device according to example 1;
wherein 11 is a drift region of a first conductivity type, 12 is a well region of the first conductivity type, 13 is a region of the first conductivity type, 14 is a heavily doped region of the first conductivity type, 15 is a buried layer of the first conductivity type, 21 is a substrate of a second conductivity type, 22 is a well region of the second conductivity type, 23 is a buried layer of the second conductivity type, 24 is a region of the second conductivity type, 25 is a heavily doped region of the second conductivity type, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, and 41 is a control gate polysilicon.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
Fig. 1 shows a schematic structural diagram of a high-voltage three-dimensional depletion super junction LDMOS device and a cross-sectional view thereof in embodiment 1 of the present invention, which specifically includes: a second conductive type substrate 21, a first conductive type drift region 11, a first conductive type well region 12 and a second conductive type well region 22, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a second conductive type buried layer 23, first conductive type regions 13 and second conductive type regions 24 which are periodically arranged, a heavily doped first conductive type region 14 and a heavily doped second conductive type region 25, and a control gate polysilicon 41;
wherein, the first conductive type well region 12 is located at the right side in the first conductive type drift region 11, the second conductive type well region 22 is located at the left side of the first conductive type drift region 11 and is tangent to the first conductive type drift region, and the second conductive type well region 22 is connected to the second conductive type substrate 21; a heavily doped first conductive type region 14 and a heavily doped second conductive type region 25 are arranged in the second conductive type well region 22, and a heavily doped first conductive type region 14 is arranged in the first conductive type well region 12; the first dielectric oxide layer 31 is located above the first conductive type drift region 11, and the second dielectric oxide layer 32 is located above the second conductive type well region 22 and partially extends above the first conductive type drift region 11;
the second conductive type buried layer 23 is located in the first conductive type drift region 11, the surface electric field of the device is optimized, the substrate auxiliary depletion effect existing in the transverse super junction is eliminated, and the voltage resistance of the device is guaranteed. The super junction structure formed by the first conductivity type region 13 and the second conductivity type region 24 is located above the second conductivity type buried layer 23 and connected with the second conductivity type buried layer 23, and the second conductivity type buried layer 23 and the second conductivity type region 24 surround the first conductivity type region 13 in three directions to form a three-dimensional depleted Fin-SJ structure. The doping concentration of the first conductive type region 13 is greatly increased, and the specific on-resistance of the device is reduced.
The specific process flow of the high-voltage three-dimensional depletion super junction LDMOS device of this embodiment is as shown in fig. 9, and specifically includes the following steps, as shown in fig. 10(a) -10 (g):
step 1: implanting a push junction over the second conductivity type substrate 21 to form a first conductivity type drift region 11, as shown in fig. 10 (a);
step 2: performing field oxidation on the basis of the structure of the step 1 to form a first dielectric oxide layer 31, as shown in fig. 10 (b);
and step 3: a first conductive type well region 12 and a second conductive type well region 22 are respectively formed at the left end and the right end of the first conductive type drift region 11 by injection; as shown in fig. 10 (c);
and 4, step 4: forming the second conductive type buried layer 23 by implanting a push junction using a resist barrier, as shown in fig. 10 (d);
and 5: forming a second dielectric oxide layer 32 by thermal oxidation, and depositing and etching to form a control gate polysilicon 41, as shown in fig. 10 (e);
step 6: forming the first conductive type region 13 and the second conductive type region 24 by implantation using a resist barrier; as shown in fig. 10 (f);
and 7: the implantation activates the heavily doped first conductive type region 14 and the heavily doped second conductive type region 25 as shown in fig. 10 (g).
Further, first conductivity type drift region 11 in step 1 may be obtained by epitaxy, the implantation of steps 4 and 6 being before step 2, and the superjunction implantation of step 6 being after step 4 before step 5.
Further, the first and second conductive type regions 13 and 24 arranged periodically may be formed by multiple implantations or a single implantation;
further, the second conductivity type buried layer 23 and the first conductivity type region 13 and the second conductivity type region 24 forming the super junction are both realized using photoresist barrier implantation;
further, the first conductivity type region 13 forming the super junction and the second conductivity type region 24 are aligned with the second conductivity type buried layer 23 in the drift region, or are shorter than, longer than the second conductivity type buried layer 23;
further, the second conductivity type buried layer 23 and the left ends of the first and second conductivity type regions 13 and 24 are located below the gate polysilicon electrode 41;
further, the first conductivity type well region 12 and the second conductivity type well region 22 are obtained by one or more different energy implantations.
Further, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type;
furthermore, the second conductive type substrate 21 may also be a substrate made of other dielectric or semiconductor materials, such as SOI or sapphire, and the same drift region structure manufacturing method may also be used in other high-voltage lateral devices, such as LIGBT, and the used semiconductor material may be a new material, such as Si or SiC.
Example 2
Fig. 2 is a schematic structural diagram and a cross-sectional view of a high-voltage three-dimensional depleted super-junction LDMOS device according to embodiment 2 of the present invention, which is manufactured in step 4 of embodiment 1, the first conductive type buried layer 15 is implanted after the second conductive type buried layer 23 is implanted, and at the same time, a push junction is formed, and the first conductive type region 13 and the second conductive type region 24 are subsequently implanted and then connected to the first conductive type buried layer 15. The first-conductivity-type buried layer 15 and the first-conductivity-type region 13 surround the second-conductivity-type region 23 in three directions to form a three-dimensional depleted super-junction structure Fin-SJ structure. Compared with the embodiment 1, the super junction injection of the embodiment has lower energy and injection times, is easier to realize, and has basically the same working principle as the embodiment 1.
Example 3
Fig. 3(a) is a schematic structural diagram of a high-voltage three-dimensional depletion superjunction LDMOS device according to embodiment 3 of the present invention, in this embodiment, a superjunction source terminal is injected into the second conductivity type well region 22 based on embodiment 1 to implement grounding of the second conductivity type region 24, and improve the dynamic characteristics of the device, and fig. 3(b) is a schematic structural diagram of another variation of embodiment 3 of the present invention, in this embodiment, the superjunction second conductivity type region 24 is introduced into the source terminal heavily doped first conductivity type region 14 and the heavily doped second conductivity type region 25 along the first conductivity type drift region 11 and the second conductivity type well region 22 on the basis of fig. 3(a), the superjunction first conductivity type region 13 remains unchanged, and superjunction grounding is implemented, and the rest operating principles are substantially consistent with embodiment 1.
Example 4
Fig. 4 is a schematic structural diagram of a high-voltage three-dimensional depleted super junction LDMOS device according to embodiment 4 of the present invention, and the present embodiment is different from embodiment 1 in that: the second conductivity type region 24 is formed by grooving and then depositing so as to realize more uniform surface doping and reduce the influence of the superjunction JFET effect on the device, and the rest of the working principles are basically consistent with those of embodiment 1.
The process flow of the embodiment comprises the following steps:
step 1: forming a first conductivity type drift region 11 by implanting a push junction in the second conductivity type substrate 21;
step 2: a first conductive type well region 12 and a second conductive type well region 22 are respectively formed at the left end and the right end of the first conductive type drift region 11 by injection;
and step 3: forming the second conductive type buried layer 23 and the first conductive type region 13 in order by ion implantation using a resist barrier;
and 4, step 4: after grooving is carried out on the basis of the step 3, depositing a second conductive type region 24 for filling, and carrying out field oxidation to form a first dielectric oxide layer 31;
and 5: forming a second dielectric oxide layer 32 by thermal oxidation, and depositing and etching to form a control gate polysilicon 41;
step 6: the implant activates the heavily doped first conductivity type region 14 and the heavily doped second conductivity type region 25.
Example 5
As shown in fig. 5, which is a schematic structural diagram of a high-voltage three-dimensional depleted super junction LDMOS device in embodiment 5 of the present invention, based on embodiment 1, the second conductivity type buried layer 23 is divided into three sections, which are respectively located in the middle of the second conductivity type well region 22, in the middle of the first conductivity type drift region 11, and beside the first conductivity type well region 12 at the right end of the first conductivity type drift region 11, and the remaining manufacturing processes are maintained unchanged. The break of the second conductive type buried layer 23 in the drift region introduces an extra electric field peak value in an off state, so that the surface field of the device is more uniform, and the purpose of further optimizing the electric field of the device is achieved. The second-conductivity-type buried layer 23 in the second-conductivity-type well region 22 can further increase the second-conductivity-type doping concentration therein, further suppressing the device parasitic tube on and auxiliary depletion drift region, and the rest of the operation principle is the same as that of embodiment 1.
Example 6
As shown in fig. 6, which is a top view of the high-voltage three-dimensional depleted super junction LDMOS device in embodiment 6 of the present invention, based on the implementation examples 1 to 5, the surface super junction can be adjusted to a shape in which the width of the first conductive type region 13 is greater than that of the second conductive type region 24, at this time, the implantation doses of the first conductive type region 13 and the second conductive type region 24 are no longer equal to each other, and the dose ratio is equal to the ratio of the strip width, so as to maintain the super junction charge balance, thereby further increasing the current conduction path of the device to reduce the specific on-resistance, and the rest of the working principle is the same as that in embodiment 1.
Example 7
As shown in fig. 7(a), which is a top view of a high-voltage three-dimensional depleted superjunction LDMOS device of embodiment 7 of the present invention, a full superjunction on the surface is changed into a half superjunction on the basis of the implementation examples 1 to 5, and more first conductivity type dopants are introduced near the drain end to optimize the surface field and obtain a lower specific on-resistance; fig. 7(b) shows another variation of embodiment 7 of the present invention, and a superjunction first conductivity type region 13 is introduced into the drain-side first conductivity type drift region based on fig. 7(a) to introduce more first conductivity type doping, and the operation principle is substantially the same as that of embodiment 1.
Example 8
As shown in fig. 8, which is a top view of a high-voltage three-dimensional depletion super junction LDMOS device according to embodiment 8 of the present invention, on the basis of embodiments 1 to 5, the shapes of the super junction first conductivity type region 13 and the second conductivity type region 24 are changed into a form in which the widths are linearly changed from the drain end to the source end, so that more first conductivity type doping is introduced into the drain end of the device to reduce the device specific conductance, and the remaining operating principles are substantially the same as those of embodiment 1.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A high-voltage three-dimensional depletion super junction LDMOS device is characterized by comprising:
the semiconductor device comprises a second conductive type substrate (21), a first conductive type drift region (11), a first conductive type well region (12) and a second conductive type well region (22), a first dielectric oxide layer (31), a second dielectric oxide layer (32), a second conductive type buried layer (23), first conductive type regions (13) and second conductive type regions (24) which are periodically arranged, a heavily doped first conductive type region (14), a heavily doped second conductive type region (25) and control grid polysilicon (41);
the first conduction type well region (12) is positioned on the right side in the first conduction type drift region (11), the second conduction type well region (22) is positioned on the left side of the first conduction type drift region (11) and is tangent to the first conduction type drift region, and the second conduction type well region (22) is connected with the second conduction type substrate (21); a heavily doped first conduction type region (14) and a heavily doped second conduction type region (25) are arranged in the second conduction type well region (22), and a heavily doped first conduction type region (14) is arranged in the first conduction type well region (12); the first dielectric oxide layer (31) is positioned above the first conduction type drift region (11), and the second dielectric oxide layer (32) is positioned above the second conduction type well region (22) and partially extends to the upper part of the first conduction type drift region (11);
the second conduction type buried layer (23) is located in the first conduction type drift region (11), a super junction structure formed by the first conduction type region (13) and the second conduction type region (24) is located above the second conduction type buried layer (23) and connected with the second conduction type buried layer (23), and the second conduction type buried layer (23) and the second conduction type region (24) surround the first conduction type region (13) in three directions to form a three-dimensional depletion super junction structure Fin-SJ structure.
2. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the first conductivity type region (13) and the second conductivity type region (24) alternately arranged periodically are formed by multiple implantations or a single implantation.
3. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the second conductive type buried layer (23) and the first conductive type region (13) and the second conductive type region (24) forming the super junction structure are both realized using photoresist to block ion implantation.
4. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the first conductivity type region (13) and the second conductivity type region (24) forming the super junction structure are aligned with the second conductivity type buried layer (3) in the first conductivity type drift region (11) or are shorter than or longer than the second conductivity type buried layer (23).
5. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the second conductive type buried layer (23) and the left ends of the first conductive type region (13) and the second conductive type region (24) are located below the gate polysilicon (41).
6. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the first conductivity type well region (12) and the second conductivity type well region (22) are obtained by one or more different energy implants.
7. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
8. The high-voltage three-dimensional depleted superjunction LDMOS device of claim 1, wherein: the second conductivity type substrate (21) is an SOI or sapphire dielectric or semiconductor material substrate.
9. The method for manufacturing the high-voltage three-dimensional depleted superjunction LDMOS device of any of claims 1 to 8, comprising the steps of:
step 1: injecting a push junction above a second conduction type substrate (21) to obtain a first conduction type drift region (11);
step 2: performing field oxidation on the basis of the structure in the step 1 to form a first dielectric oxide layer (31);
and step 3: a first conductive type well region (12) and a second conductive type well region (22) are respectively formed at the left end and the right end of the first conductive type drift region (11) in an injection mode;
and 4, step 4: forming a second conductive type buried layer (23) by implanting a push junction using a resist barrier;
and 5: forming a second dielectric oxide layer (32) by thermal oxidation, and depositing and etching to form control gate polysilicon (41);
step 6: forming a first conductivity type region (13) and a second conductivity type region (24) by implantation using a resist barrier;
and 7: the implant activates a heavily doped first conductivity type region (14) and a heavily doped second conductivity type region (25).
10. The manufacturing method of the high-voltage three-dimensional depleted superjunction LDMOS device of claim 9, wherein: the first conduction type drift region (11) is obtained in an epitaxial mode; or the step 4 and step 6 implantations precede step 2; or the super junction implantation of step 6 follows step 4 before step 5.
CN202010888999.3A 2020-08-28 2020-08-28 High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof Pending CN111969043A (en)

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