CN106057906A - Accumulated DMOS with P type buried layer - Google Patents
Accumulated DMOS with P type buried layer Download PDFInfo
- Publication number
- CN106057906A CN106057906A CN201610705723.0A CN201610705723A CN106057906A CN 106057906 A CN106057906 A CN 106057906A CN 201610705723 A CN201610705723 A CN 201610705723A CN 106057906 A CN106057906 A CN 106057906A
- Authority
- CN
- China
- Prior art keywords
- type
- buried layer
- doped region
- dmos
- heavily doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009825 accumulation Methods 0.000 claims description 46
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 230000007935 neutral effect Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000037361 pathway Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention belongs to the technical field of power semiconductors and especially relates to an accumulated DMOS with a P type buried layer. The accumulated DMOS with the P type buried layer is characterized in that an accumulated area is introduced, so that a threshold voltage and the conduction resistance are lowered; the structural body is internally provided with the P type buried layer, a transverse electric field can be further optimized based on an internal field plate, and the breakdown voltage of the device is improved; and a thick oxygen structure is adopted by the bottom part of a groove-type gate electrode, so that the gate-drain capacitance can be effectively lowered. Under the condition that the reverse breakdown voltages are identical, the accumulated DMOS is relatively small in threshold voltage and conduction resistance.
Description
Technical field
The invention belongs to power semiconductor technologies field, particularly to a kind of accumulation type DMOS with p type buried layer.
Background technology
The development of power MOS (Metal Oxide Semiconductor) device is on the basis of MOS device its own advantages, makes great efforts to improve pressure and fall is low-loss
Process.
Power DMOS is the electronic power switch device of new generation grown up on the basis of MOS integrated circuit technology,
The requirement of the big electric current of electronic equipment high power is realized on the basis of microelectronic technique.
Power MOSFET is many electronic conductions device, has the advantages such as switching speed is fast, input impedance is high, easy driving.Preferable
MOS should have relatively low conducting resistance, switching loss and higher blocking voltage.But conducting resistance and breakdown voltage, lead
There is restraining function between energising resistance and switching loss, limit the development of power MOS.In order to improve the property of power MOSFET
Can, abroad propose the new structures such as grid dividing structure (Split-gate).Split-gate structure can utilize its ground floor polycrystalline
Layer (Shield) reduces the electric field of drift region as " internal field plate ", so Split-gate structure is generally of lower leading
Energising resistance and higher breakdown voltage, and can be used for the TRENCH MOS product of high voltage (20V-250V).
Although both at home and abroad company achieves bigger progress in terms of optimizing conducting resistance and grid electric charge, but in recent years,
The fierce market competition is more and more higher to the performance requirement of device, so how uses the MOSFET structure design of advanced person to drop simultaneously
Low device R ds (on) and Qg remain the direction that each producer makes great efforts.The structure that the present invention proposes can improve device further
On-state loss and switching loss.
Summary of the invention
The present invention is directed to the problems referred to above, propose a kind of introducing accumulation type region in DMOS, in combination with internal field plate and P
The advantage of type buried regions so that the threshold voltage of DMOS is relatively low, conducting resistance is less and gate leakage capacitance is less has p type buried layer
Accumulation type DMOS.
Technical scheme: a kind of accumulation type DMOS with p type buried layer structure, including stacking gradually from bottom to up
Metalized drain 1, N+ substrate 2, N-drift region 3 and the metallizing source 12 arranged；It is light that upper strata, described N-drift region 3 has N-type
Doped region 8, p-type doped region 9, P+ heavily doped region 10 and N+ heavily doped region 11；Described P+ heavily doped region 10 and N+ heavily doped region 11
Upper surface contact with metallizing source 12, described N+ heavily doped region 11 between the P+ heavily doped region 10 of both sides and with its phase
Contact mutually；Described p-type doped region 9 is positioned at the underface of P+ heavily doped region 10 and contacts with each other with it；Described N-type is lightly doped district 8
It is positioned at the underface of N+ heavily doped region 11 and contacts with each other with it；Described N-drift region 3 also has grooved gate electrode and internal field
Plate 6, described grooved gate electrode vertically sequentially pass through N+ heavily doped region 11 and N-type district 8 is lightly doped after extend into N-drift
In district 3；Described grooved gate electrode is made up of gate oxide 51 and the gate electrode 4 being positioned in gate oxide 51, wherein gate oxide
The upper surface of 51 contacts with metallizing source 12, and thick oxide layer is formed on the bottom of gate oxide 5；Described internal field plate 6 is along vertically
Direction extends in N-drift region 3 after sequentially passing through P+ heavily doped region 10 and p-type doped region 9；The upper surface of described internal field plate 6
Contacting with metallizing source 12, the oxidized layer in side and bottom 5 of internal field plate 6 surrounds；It is characterized in that, described N-drift region
Also include in 3 that the p type buried layer 7 of multiple floating, described p type buried layer 7 are positioned at gate oxide 51 and the underface of oxide layer 5；Work as device
During part forward conduction, gate electrode 4 connects positive potential, and metalized drain 1 connects positive potential, metallizing source 12 connecting to neutral current potential；Work as device
During reverse blocking, gate electrode 4 and metallizing source 12 short circuit and connecting to neutral current potential, metalized drain 1 connects positive potential.
Further, the material that described oxide layer 5 uses is silicon dioxide or silicon dioxide and the composite wood of silicon nitride
Material.
Further, the material that described gate electrode 4 uses is polysilicon.
Further, the material that described internal field plate 6 uses is polysilicon or metal.
Beneficial effects of the present invention is, has that threshold voltage is less, conducting resistance optimizes and less grid leak further
The good characteristics such as electric capacity.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of accumulation type DMOS with p type buried layer that the present invention provides；
What Fig. 2 was that the present invention provides a kind of has the accumulation type DMOS of p type buried layer when additional no-voltage, exhausts line signal
Figure；
When a kind of accumulation type DMOS applied voltage with p type buried layer that Fig. 3 is that the present invention provides arrives threshold voltage
Current path schematic diagram；
Fig. 4 is free from the breakdown current voltage pattern of the accumulation type DMOS of the common DMOS of p type buried layer；
Fig. 5 is free from the breakdown current voltage pattern of the accumulation type DMOS of the accumulation type DMO of p type buried layer；
Fig. 6 is the breakdown current voltage pattern of the accumulation type DMOS with p type buried layer；
Fig. 7 is free from the breakdown current pathway figure of the accumulation type DMOS of the common DMOS of p type buried layer；
Fig. 8 is free from the breakdown current pathway figure of the accumulation type DMOS of the accumulation type DMOS of p type buried layer；
Fig. 9 is the breakdown current pathway figure of the accumulation type DMOS with p type buried layer；
Figure 10 is free from the conducting resistance figure of the accumulation type DMOS of the common DMOS of p type buried layer；
Figure 11 is free from the conducting resistance figure of the accumulation type DMOS of the accumulation type DMOS of p type buried layer；
Figure 12 is the conducting resistance figure of the accumulation type DMOS with p type buried layer；
Figure 13 is free from the conductive current path figure of the accumulation type DMOS of the common DMOS of p type buried layer；
Figure 14 is free from the conductive current path figure of the accumulation type DMO of p type buried layer；
Figure 15 is the conductive current path figure of the accumulation type DMOS with p type buried layer；
Figure 16 is free from the threshold voltage figure of the accumulation type DMOS of the common DMOS of p type buried layer；
Figure 17 is free from the threshold voltage figure of the accumulation type DMOS of the accumulation type DMOS of p type buried layer；
Figure 18 is the threshold voltage figure of the accumulation type DMOS with p type buried layer；
Figure 19 to Figure 28 is a kind of manufacturing process flow of a kind of accumulation type DMOS with p type buried layer that the present invention provides
Schematic diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is described in detail
As it is shown in figure 1, a kind of accumulation type DMOS with p type buried layer structure of the present invention, including layer the most successively
Folded metalized drain 1, N+ substrate 2, N-drift region 3 and the metallizing source 12 arranged；Upper strata, described N-drift region 3 has N-type
District 8, p-type doped region 9, P+ heavily doped region 10 and N+ heavily doped region 11 are lightly doped；Described P+ heavily doped region 10 and N+ heavily doped region
The upper surface of 11 contacts with metallizing source 12, described N+ heavily doped region 11 between the P+ heavily doped region 10 of both sides and and its
Contact with each other；Described p-type doped region 9 is positioned at the underface of P+ heavily doped region 10 and contacts with each other with it；Described N-type is lightly doped
District 8 is positioned at the underface of N+ heavily doped region 11 and contacts with each other with it；Described N-drift region 3 also has grooved gate electrode and internal
Field plate 6, described grooved gate electrode vertically sequentially pass through N+ heavily doped region 11 and N-type district 8 is lightly doped after extend into N-drift
Move in district 3；Described grooved gate electrode is made up of gate oxide 51 and the gate electrode 4 being positioned in gate oxide 51, wherein gate oxidation
The upper surface of layer 51 contacts with metallizing source 12, and thick oxide layer is formed on the bottom of gate oxide 5；Described internal field plate 6 is along hanging down
Nogata extends in N-drift region 3 after sequentially passing through P+ heavily doped region 10 and p-type doped region 9；The upper table of described internal field plate 6
Face contacts with metallizing source 12, and the oxidized layer in side and bottom 5 of internal field plate 6 surrounds；It is characterized in that, described N-drifts about
District 3 also including, the p type buried layer 7 of multiple floating, described p type buried layer 7 are positioned at gate oxide 51 and the underface of oxide layer 5；When
During device forward conduction, gate electrode 4 connects positive potential, and metalized drain 1 connects positive potential, metallizing source 12 connecting to neutral current potential；Work as device
During part reverse blocking, gate electrode 4 and metallizing source 12 short circuit and connecting to neutral current potential, metalized drain 1 connects positive potential.
The operation principle of the present invention is:
(1) forward conduction of device
A kind of accumulation type DMOS with p type buried layer provided by the present invention, electrode connection mode during its forward conduction
For: grooved gate electrode 4 connects positive potential, and metalized drain 1 connects positive potential, metallizing source 12 connecting to neutral current potential.When grooved gate electrode 4
For no-voltage or added positive voltage the least time, owing to the doping content of p-type doped region 9 is lightly doped the doping in district 8 more than N-type
Concentration, p-type doped region 9 and N-type are lightly doped the Built-in potential of the PN junction that district 8 is constituted can make p-type doped region 9 and gate oxidation
N-type between floor 5 is lightly doped district 8 and exhausts, and electron channel is blocked, as in figure 2 it is shown, now accumulation type DMOS is still in closedown
State.
Along with the increase of positive voltage added by grooved gate electrode 4, p-type doped region 9 and N-type are lightly doped the PN junction that district 8 is constituted
Built-in barrier region be gradually reduced.Owing to N-type is lightly doped the existence in district 8, device is easier to open, thus reduces threshold value electricity
Pressure.After positive voltage added by grooved gate electrode 4 is equal to or more than cut-in voltage, owing to the N-type at gate oxide 5 side is light
Producing the accumulation layer of how sub-electronics in doped region 8, this is that the flowing of many electron currents provides a low impedance path, conducting resistance from
And be reduced, as it is shown on figure 3, now accumulation type DMOS conducting, how sub-electronics under the effect of metalized drain 1 positive potential from
N+ heavily doped region 11 flows to metalized drain 1.Further, since the gate oxide 51 bottom grooved gate electrode 4 takes thick oxygen technique,
So gate leakage capacitance Cgd obtains bigger improvement.
(2) reverse blocking of device
A kind of accumulation type DMOS with p type buried layer provided by the present invention, electrode connection mode during its reverse blocking
For: grooved gate electrode 4 and metallizing source 12 short circuit and connecting to neutral current potential, metalized drain 1 connects positive potential.
Owing to during zero-bias, N-type between p-type doped region 9 and gate oxide 5 is lightly doped district 8 and has been completely depleted, many
The conductive path of sub-electronics is by pinch off.When increasing backward voltage, due to the existence of internal field plate 6, internal field plate 6 and N-drift region
3 constitute transverse electric field, and first the N-drift region 3 between internal field plate 6 and gate oxide 5 exhausts, and bears backward voltage.Continue to increase
During big backward voltage, due to the existence of p type buried layer 7, p type buried layer 7 and N-drift region constitutes transverse electric field, the breakdown voltage of device
Improve further.Along with the further increase of backward voltage, depletion layer boundaries is by the N-drift near metalized drain 1 side
District 3 extends to bear backward voltage.Now compared with the DMOS only with internal field plate structure, in N-drift region 3 doping content
In the case of identical, due to the existence of p type buried layer 7, the transverse electric field in the body of N-drift region 3 optimizes, further in breakdown voltage
Time identical, the conducting resistance of a kind of accumulation type DMOS with p type buried layer reduces further.
In sum, a kind of accumulation type DMOS with p type buried layer provided by the present invention, have threshold voltage less,
Conducting resistance optimizes and the good characteristic such as less gate leakage capacitance further.
In order to verify beneficial effects of the present invention, the present invention is had the accumulation type DMOS of p type buried layer and buries without p-type
The common DMOS of layer, the accumulation type DMOS without p type buried layer have carried out contrast simulation.In three kinds of structures, except being whether accumulation
Type and whether containing outside p type buried layer, other device parameters are the most identical.As shown in Fig. 4 to Figure 18, there is the accumulation type of p type buried layer
The combination property of DMOS is optimal, and not only threshold voltage is less, has higher breakdown voltage and relatively low ratio conducting resistance simultaneously
Value.
A kind of manufacturing process flow of a kind of accumulation type DMOS with p type buried layer of the present invention is as follows:
1, monocrystal silicon prepares and epitaxial growth.Such as Figure 19, using N-type heavy doping monocrystalline substrate 2, crystal orientation is<100>.Adopt
With method growth certain thickness and the N-drift regions 3 of doping content such as vapour phase epitaxies VPE, photolithography plate is utilized to carry out ion implanting,
Form p type buried layer 7, continue extension N-drift region.
2, ion implanting.Such as Figure 20, utilize photolithography plate to carry out PXing Zhu district boron and inject, form p-type doped region 9, carry out N-type
Post district phosphorus injects, and the implantation dosage of phosphorus should be relatively low herein, forms N-type and district 8 is lightly doped.
3, cutting.Such as Figure 21, deposit hard mask (such as silicon nitride), utilize photolithography plate to etch hard mask, carry out deep etching,
Etching groove grid region and internal field plate region, concrete etching technics can use reactive ion etching or plasma etching.
4, the filling of silicon dioxide.Such as Figure 22, with silica-filled groove grid region and internal field plate region.
5, the etching of silicon dioxide in internal field plate.Such as Figure 23, utilize photolithography plate first to the titanium dioxide in internal field plate region
Silicon performs etching.
6, the etching of silicon dioxide.Such as Figure 24, remove photolithography plate, same to the silicon dioxide in groove grid region and internal field plate region
Time perform etching, remove hard mask, this time slot grid region still left thicker silicon dioxide 51.
7, oxide layer is thermally grown.Such as Figure 25, groove grid region and internal field plate region sidewall are carried out oxide layer thermally grown, wherein groove
Grid region forms sidewall gate oxide 5.
8, the deposit of polysilicon and etching.Such as Figure 26, depositing polysilicon, the thickness of polysilicon to guarantee to fill up grooved
Region.Utilize the photolithography plate etching polysilicon to groove grid region, and above groove grid region, deposit silicon dioxide, and etching surface titanium dioxide
Silicon.
9, ion implanting.Such as Figure 27, p-type heavily doped region boron injects, and forms P+ heavily doped region 10, and N-type heavily doped region arsenic is noted
Enter, form N+ heavily doped region 7.
10, metallization.Such as Figure 28 front-side metallization, metal etch, back face metalization, passivation etc..
During making devices, can also be used with the semi-conducting materials such as carborundum, GaAs or germanium silicon and substitute body silicon.
Use a kind of accumulation type DMOS with p type buried layer of the present invention, have that threshold voltage is less, conducting resistance reduces
And the good characteristic such as less gate leakage capacitance.
Claims (4)
1. there is an accumulation type DMOS for p type buried layer structure, including the metalized drain being cascading from bottom to up
(1), N+ substrate (2), N-drift region (3) and metallizing source (12)；Described N-drift region (3) upper strata has N-type and district is lightly doped
(8), p-type doped region (9), P+ heavily doped region (10) and N+ heavily doped region (11)；Described P+ heavily doped region (10) and N+ heavy doping
The upper surface in district (11) contacts with metallizing source (12), and described N+ heavily doped region (11) is positioned at the P+ heavily doped region (10) of both sides
Between and contact with each other with it；Described p-type doped region (9) is positioned at the underface of P+ heavily doped region (10) and contacts with each other with it；
Described N-type is lightly doped district (8) and is positioned at the underface of N+ heavily doped region (11) and contacts with each other with it；Described N-drift region (3) is also
There is grooved gate electrode and internal field plate (6), described grooved gate electrode vertically sequentially pass through N+ heavily doped region (11) and
N-type extends in N-drift region (3) after district (8) is lightly doped；Described grooved gate electrode is by gate oxide (51) and is positioned at gate oxidation
Gate electrode (4) composition in layer (51), wherein the upper surface of gate oxide (51) contacts with metallizing source (12), gate oxide
(5) thick oxide layer is formed on bottom；Described internal field plate (6) vertically sequentially passes through P+ heavily doped region (10) and p-type is mixed
Extend into behind miscellaneous district (9) in N-drift region (3)；The upper surface of described internal field plate (6) contacts with metallizing source (12), internal
The side and bottom oxidized layer (5) of field plate (6) surrounds；It is characterized in that, described N-drift region (3) also includes multiple floating
P type buried layer (7), described p type buried layer (7) is positioned at gate oxide (51) and the underface of oxide layer (5)；When device forward conduction
Time, gate electrode (4) connects positive potential, and metalized drain (1) connects positive potential, metallizing source (12) connecting to neutral current potential；When device is reverse
During blocking-up, gate electrode (4) and metallizing source (12) short circuit and connecting to neutral current potential, metalized drain (1) connects positive potential.
A kind of accumulation type DMOS with p type buried layer structure the most according to claim 1, it is characterised in that described oxidation
Layer (5) material that uses is silicon dioxide or silicon dioxide and the composite of silicon nitride.
A kind of accumulation type DMOS with p type buried layer structure the most according to claim 2, it is characterised in that described grid electricity
The material that pole (4) uses is polysilicon.
A kind of accumulation type DMOS with p type buried layer structure the most according to claim 3, it is characterised in that described internal
The material that field plate (6) uses is polysilicon or metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610705723.0A CN106057906B (en) | 2016-08-22 | 2016-08-22 | A kind of accumulation type DMOS with p type buried layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610705723.0A CN106057906B (en) | 2016-08-22 | 2016-08-22 | A kind of accumulation type DMOS with p type buried layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106057906A true CN106057906A (en) | 2016-10-26 |
| CN106057906B CN106057906B (en) | 2018-11-23 |
Family
ID=57195487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610705723.0A Expired - Fee Related CN106057906B (en) | 2016-08-22 | 2016-08-22 | A kind of accumulation type DMOS with p type buried layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106057906B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731894A (en) * | 2017-09-02 | 2018-02-23 | 西安交通大学 | A kind of low on-resistance carborundum IGBT device and preparation method with floating area |
| CN111211174A (en) * | 2020-03-20 | 2020-05-29 | 济南安海半导体有限公司 | SGT-MOSFET semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037632A (en) * | 1995-11-06 | 2000-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20110303975A1 (en) * | 2005-06-10 | 2011-12-15 | Hamza Yilmaz | Field effect transistor with self-aligned source and heavy body regions |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
| CN104103693A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | U-groove power device and manufacturing method thereof |
| CN104380471A (en) * | 2012-06-13 | 2015-02-25 | 株式会社电装 | Silicon carbide semiconductor device and method for producing same |
-
2016
- 2016-08-22 CN CN201610705723.0A patent/CN106057906B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037632A (en) * | 1995-11-06 | 2000-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20110303975A1 (en) * | 2005-06-10 | 2011-12-15 | Hamza Yilmaz | Field effect transistor with self-aligned source and heavy body regions |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
| CN104380471A (en) * | 2012-06-13 | 2015-02-25 | 株式会社电装 | Silicon carbide semiconductor device and method for producing same |
| CN104103693A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | U-groove power device and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731894A (en) * | 2017-09-02 | 2018-02-23 | 西安交通大学 | A kind of low on-resistance carborundum IGBT device and preparation method with floating area |
| CN107731894B (en) * | 2017-09-02 | 2020-02-07 | 西安交通大学 | Low-on-resistance silicon carbide IGBT device with floating zone and preparation method |
| CN111211174A (en) * | 2020-03-20 | 2020-05-29 | 济南安海半导体有限公司 | SGT-MOSFET semiconductor device |
| CN111211174B (en) * | 2020-03-20 | 2023-01-31 | 济南安海半导体有限公司 | SGT-MOSFET semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106057906B (en) | 2018-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107799587A (en) | A kind of reverse blocking IGBT and its manufacture method | |
| CN110600537B (en) | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof | |
| CN106158973A (en) | A kind of accumulation type DMOS | |
| CN105870179B (en) | A kind of trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN106098777A (en) | A kind of splitting bar accumulation type DMOS device | |
| CN109065627A (en) | A kind of LDMOS device with polysilicon island | |
| CN106298939A (en) | A kind of accumulation type DMOS with complex media Rotating fields | |
| CN111668312A (en) | Groove silicon carbide power device with low on-resistance and manufacturing process thereof | |
| CN110504310A (en) | A kind of RET IGBT and preparation method thereof with automatic biasing PMOS | |
| CN113838922A (en) | Split-gate super-junction IGBT device structure with carrier concentration enhancement function and method | |
| CN105977302A (en) | Grooved gate MOS having buried layer structure | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN114171588B (en) | Bidirectional conduction groove gate power MOS device structure and manufacturing method | |
| CN110504260B (en) | Transverse groove type IGBT with self-bias PMOS and preparation method thereof | |
| CN103531614B (en) | Charge compensation semiconductor device | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| CN107768435A (en) | A kind of two-way IGBT and its manufacture method | |
| CN105957894A (en) | DMOS with composite dielectric layer structure | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof | |
| CN105742372A (en) | Grooved-gate metal oxide semiconductor diode with adjustable threshold voltage | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN108389895A (en) | Integrated power device based on superjunction and its manufacturing method | |
| CN106057906B (en) | A kind of accumulation type DMOS with p type buried layer | |
| CN210092093U (en) | Device of shielding grid power MOS | |
| CN106098799A (en) | A kind of accumulation type trench diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181123 Termination date: 20210822 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |