CN210092093U

CN210092093U - Device of shielding grid power MOS

Info

Publication number: CN210092093U
Application number: CN201821774060.9U
Authority: CN
Inventors: 李泽宏; 吴玉舟; 王为; 谢驰
Original assignee: Guizhou E Chip Microelectronics Technology Co ltd
Current assignee: Guizhou E Chip Microelectronics Technology Co ltd
Priority date: 2018-10-30
Filing date: 2018-10-30
Publication date: 2020-02-18
Anticipated expiration: 2028-10-30

Abstract

The utility model provides a device of shielded gate power MOS adopts undoped polycrystalline silicon at the sedimentary shielded gate in slot bottom, and its electric potential sets up to float empty simultaneously, does not link to each other with the source electrode electric potential, effectively reduces grid source electric capacity. The charge balance effect that the power MOS drift region was guaranteed to the shielding grid structure reduces on-resistance, improves breakdown voltage, and the potential line distribution of drift region when the semi-insulating modulation of utilizing undoped polycrystalline silicon is withstand voltage simultaneously is more even, thereby makes the utility model discloses the structure has the breakdown voltage higher than traditional shielding grid power MOS.

Description

Device of shielding grid power MOS

Technical Field

The utility model belongs to the technical field of power semiconductor device, concretely relates to device of shielding grid power MOS.

Background

The shielding grid power MOS forms a shielding grid by adding one-time polycrystalline deposition and etching under a groove grid on the basis of the structure of the traditional Trench MOS, the shielding grid is generally connected with a source electrode potential, and the capacitance between the grid and an opposite drain electrode, namely the Miller capacitance, is shielded. By adopting the shielding grid structure, the Miller capacitance can be greatly reduced, and the switching speed of the device is improved. Meanwhile, the breakdown voltage of the MOS can be obviously improved by utilizing the charge balance effect of the shielding grid, and the on-resistance of the device is reduced. But this greatly increases the gate-source capacitance since the shield gate is connected to the source. The power MOS with the shielding grid structure is improved, so that the grid-source capacitance is reduced, and the breakdown voltage in cut-off is further improved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem for providing a power MOS device with shielding grid structure, it can optimize the performance of device.

For solving the too big problem of traditional shielding bars power MOS grid source electric capacity, the utility model provides a novel shielding bars structure power MOS device adopts undoped polycrystalline silicon at the sedimentary shielding bars in slot bottom, and its electric potential sets up to the sky that floats simultaneously, does not link to each other with the source electrode electric potential, effectively reduces grid source electric capacity. The charge balance effect that the power MOS drift region was guaranteed to the shielding grid structure reduces on-resistance, improves breakdown voltage, and the potential line distribution of drift region when the semi-insulating modulation of utilizing undoped polycrystalline silicon is withstand voltage simultaneously is more even, thereby makes the utility model discloses the structure has the breakdown voltage higher than traditional shielding grid power MOS.

The technical scheme of the utility model, a shielded gate power MOS device, include metallization drain terminal electrode 1, N + substrate 2, be located the N-epitaxial layer 3 of N + substrate 2 top, N-epitaxial layer upper portion both sides are P type district 4, be provided with mutually independent N + source district 5 in the P type district 4, form oxidation formation bottom oxide layer 6 after the slot at N-epitaxial layer upper surface sculpture, the deposit does not dope polycrystalline silicon and sculpture and forms shielded gate 7, and the oxide layer 8 between the deposit oxide layer formation, reheating growth gate oxide layer 9 behind the oxide layer of the first half of sculpture slot, redeposit heavy doping polycrystalline silicon forms grid 10, sedimentary boron phosphorus silicon glass 11, upper surface metallization source 12.

Where the deposited heavily doped polysilicon 10 is connected to the gate potential and the undoped polysilicon is not connected to the source potential.

The beneficial effects of the utility model are that, when backward ending, because there is the deep groove of polycrystalline silicon and oxide layer formation to exist for the breakdown voltage of this power MOS is not only by epitaxial layer doping concentration and thickness decision, and the charge balance effect that the horizontal electric field that the deep groove was introduced produced is withstand voltage to it and has the additional action, in addition the utility model provides an electric field in the modulation epitaxial layer that half insulating property of undoped polycrystalline silicon shielding grid itself can be better, therefore under the condition that reaches certain voltage, the epitaxial layer concentration value can be selected higher, and this resistance when just doing benefit to showing and reducing forward switches on reduces the consumption when forward switching on. In addition, because the undoped polysilicon shielding grid is not connected with the source electrode, the grid-source capacitance is obviously reduced. Meanwhile, due to the restriction consideration of the non-gate source leakage current between the heavily doped polysilicon gate and the undoped polysilicon shielding gate, the requirement on the reliability of an oxide layer between the layers of the device is lowered, and the process complexity is simplified.

Drawings

Fig. 1 is a schematic structural diagram of a conventional Trench VDMOS device;

FIG. 2 is a schematic structural view of embodiment 1;

FIG. 3 is a schematic structural view of example 2;

Detailed Description

The utility model provides a shielded gate power MOS device on original structure basis, adopts undoped polycrystalline silicon when making the shielded gate, and the electric potential floats sky, does not link to each other with the device source electrode.

As shown in fig. 1, it is a schematic structural diagram of a conventional Trench VDMOS device. The solar cell comprises a metalized drain terminal electrode 1, a heavily doped N-type substrate 2, a lightly doped epitaxial N-layer 3, a P-type semiconductor body region 4, a heavily doped N-type source region 5, a gate oxide layer 6, a polycrystalline silicon gate electrode 7, a metalized source terminal electrode 10, and boron-phosphorus-silicon glass 8 between the heavily doped polycrystalline silicon gate electrode 7 and a metalized source terminal electrode 9. Compared with a shielding grid power MOS, the traditional Trench VDMOS device has large Miller capacitance and forward on resistance, and low breakdown voltage and switching speed.

Example 1:

as shown in fig. 2, a drain electrode 1, an N + substrate 2 and an N-epitaxial layer 3 located above the N + substrate 2 are metalized, P-type body regions 4 are arranged on two sides of the upper portion of the N-epitaxial layer 3, the P-type body regions 4 are provided with mutually independent N + source regions 5, a groove is formed on the upper surface of the N-epitaxial layer through etching and then oxidized to form a bottom oxide layer 6, undoped polysilicon is deposited and a shield gate 7 is formed through etching, an interlayer oxide layer 8 is formed through deposition, a gate oxide layer 9 is thermally grown after etching the oxide layer on the upper half portion of the groove, a gate electrode 10 formed through deposition of heavily doped polysilicon, deposited boron-phosphorus-silicon glass 11 and an upper surface metalized source electrode 12 are metalized. Wherein the undoped polysilicon shield gate 7 is not electrically connected to the source 12.

Example 2:

as shown in fig. 3, this embodiment is different from embodiment 1 in that the heavily doped polysilicon gate oxide layer 9 on the upper surface of the device is divided into two parts, which can further reduce the gate-source capacitance and miller capacitance of the device. The working principle of this example is the same as that of embodiment 1.

The utility model discloses a scheme is applicable to P channel shielding bars power MOS device simultaneously. The semiconductor material can adopt bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

Claims

1. A shielded gate power MOS device comprising a metallised drain electrode (1), an N + substrate (2) and an N-epitaxial layer (3) located over the N + substrate (2), characterised in that: the two sides of the upper part of the N-epitaxial layer (3) are provided with P-type body regions (4), the P-type body regions (4) are internally provided with N + source regions (5) which are independent of each other, a bottom oxide layer (6) is formed by oxidation after a groove is formed on the upper surface of the N-epitaxial layer (3) through etching, undoped polysilicon is deposited on the lower part of the bottom oxide layer (6) and etched to form a shielded gate (7), an inter-layer oxide layer (8) is formed by deposition of the oxide layer, a gate oxide layer (9) is thermally grown on the upper end of the oxide layer (6), heavily doped polysilicon is deposited again to form a gate (10), and boron-phosphorus-silicon glass (11) and an upper surface metalized source electrode (12; the shielding grid (7) is undoped polysilicon, and the potential floats and is not electrically connected with the source electrode (12).

2. The shielded gate power MOS device of claim 1 wherein: the shielding grid power MOS device is suitable for a P-channel shielding grid power MOS device.