CN106992208B - Thin silicon layer SOI (silicon on insulator) -based lateral insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Thin silicon layer SOI (silicon on insulator) -based lateral insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 44
- 239000010703 silicon Substances 0.000 title claims abstract description 44
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- 239000012212 insulator Substances 0.000 title claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 35
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- 230000000694 effects Effects 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 description 12
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
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- 239000000969 carrier Substances 0.000 description 5
- 238000000605 extraction Methods 0.000 description 4
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- 238000005215 recombination Methods 0.000 description 1
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Abstract
The invention discloses a thin silicon SOI (silicon on insulator) base transverse insulated gate bipolar transistor and a manufacturing method thereof. The novel thin silicon layer SOI-based lateral insulated gate bipolar transistor can eliminate the negative resistance effect when the device is conducted on the premise of ensuring the smaller turn-off time of the device, and improves the working stability of the device; in addition, the design structure of the shallow slot isolation and anode floating buffer area adopted by the device can be realized by adopting the shallow slot isolation process of the integrated circuit manufacturing process, and the design can also reduce the transverse size of the device and improve the current conducting capacity.
Description
Technical Field
The invention relates to an SOI (silicon on insulator) base conductivity modulation type high-voltage power device in the technical field of semiconductor power electronic devices, in particular to a thin silicon layer SOI base transverse insulated gate bipolar transistor.
Background
A Lateral insulated gate bipolar transistor (LIGBT: lateral Insulated Gate Bipolar Transistor) made of silicon on insulator (SOI: silicon On Insulator) as a substrate material, SOI-LIGBT for short, especially thin silicon layer SOI-LIGBT, is a key component of SOI high-voltage integrated circuit, has the advantages of simple driving, large current capability and easy integration, but has a much slower turn-off speed than a Lateral Double-diffused metal-oxide-semiconductor effect transistor (LDMOS) to cause larger switching loss, which affects the application of the SOI Lateral insulated gate bipolar transistor in a power integrated circuit.
Methods for improving the turn-off speed of a thin silicon layer SOI-LIGBT device and reducing the switching loss mainly comprise three types:
firstly, the service life of unbalanced carriers in the drift region is reduced, and the recombination rate is increased so as to improve the turn-off speed. While in fact reducing the lifetime of the unbalanced carriers in the drift region, the total number of unbalanced carriers is also reduced, which leads to an increase in on-resistance, so this approach has a trade-off problem;
secondly, controlling the minority carrier injection level from the anode to the drift region to achieve a compromise between on-resistance and off-time;
and thirdly, providing an unbalanced carrier extraction channel in the anode region, and rapidly reducing the total number of unbalanced carriers in the drift region when the device is turned off so as to improve the turn-off speed of the device. The structure of the unbalanced carrier extraction channel generally affects the minority carrier injection efficiency, i.e. the total number of unbalanced carriers in the drift region when on, and thus the on-resistance. In addition, in the forward opening process of the device, negative resistance effect is easy to occur in the conducting process due to the conversion of the carrier from the LDMOS conducting mode to the LIGBT conducting mode.
The novel structural device provided by the patent belongs to the third class of the method for improving the turn-off speed of the SOI-LIGBT device with the thin silicon layer, and the novel non-equilibrium carrier extraction channel in the anode region is provided to reduce the loss in the turn-off process, optimize the constraint relation between the on resistance and the turn-off time, and completely eliminate the negative resistance effect in the forward conduction process, so that the purposes of reducing the total loss in the working period of the device and improving the working stability of the device are achieved.
For the method of improving the turn-off speed of the thin silicon layer SOI-LIGBT device by providing an unbalanced carrier extraction channel in the anode region, complex device structure design is difficult to realize because the top silicon layer is very thin (typically about 1-2 um thick), and the device structures typically used in the prior art include a conventional anode short-circuit structure, a split anode structure, a dielectric isolation anode short-circuit structure, an anode raised dielectric isolation short-circuit structure, and the like. The existing structure is complex in processing technology or requires a large additional area.
Disclosure of Invention
The invention aims to solve the problems of complex processing technology, large additional area, weak forward conduction capability of devices and the like in the prior art.
The technical scheme adopted for realizing the purpose of the invention is that the thin silicon layer SOI-based lateral insulated gate bipolar transistor is characterized in that: the semiconductor device comprises a second conductive type substrate layer, an insulating medium layer, a second conductive type cathode well region, a heavily doped first conductive type cathode region, a heavily doped second conductive type cathode region, a cathode contact region, a gate medium layer, a first conductive type drift region, a first conductive type anode buffer region, a heavily doped second conductive type anode region, an anode contact region, a heavily doped first conductive type anode region, a shallow trench isolation region, a second conductive type floating region and a first conductive type anode well region.
The insulating dielectric layer covers the second conductive type substrate layer.
The second conductive type cathode well region, the first conductive type drift region, the first conductive type anode buffer region and the first conductive type anode well region are all covered on the insulating medium layer.
The heavily doped first conductivity type anode region and the shallow trench isolation region overlie the first conductivity type anode well region.
The second conductivity type floating region floats inside the first conductivity type anode well region.
The heavily doped second conductivity type anode region is located inside the first conductivity type anode buffer region.
The anode contact region covers a portion of the surface above the second conductivity type anode region and a portion of the surface above the heavily doped first conductivity type anode region, respectively.
The heavily doped first conductivity type cathode region and the heavily doped second conductivity type cathode region are located inside the second conductivity type cathode well region.
The cathode contact region covers the heavily doped second conductivity type cathode region, and the cathode contact region also covers a part of the surface above the heavily doped first conductivity type cathode region.
The gate dielectric layer covers the second conductivity type cathode well region, and the gate dielectric layer also covers part of the surface of the heavily doped first conductivity type cathode region and the first conductivity type drift region.
The gate contact region overlies a gate dielectric layer.
Further, the second conductivity type substrate layer, the insulating dielectric layer and the first conductivity type drift region constitute a thin silicon layer SOI base substrate.
Further, the heavily doped first conductivity type cathode region is in contact with the heavily doped second conductivity type cathode region.
Further, the second conductive type cathode well region and the first conductive type anode buffer region are respectively positioned at two sides of the first conductive type drift region. The first conductive-type anode well region is in contact with the first conductive-type anode buffer region.
Further, the shallow trench isolation region is in contact with the heavily doped first conductivity type anode region and the first conductivity type anode buffer region, respectively.
Further, the heavily doped second conductivity type anode region is not in contact with the first conductivity type drift region, the shallow trench isolation region, and the first conductivity type anode well region.
Further, the shallow trench isolation region is filled with an insulating medium.
A method of fabricating a thin silicon-on-SOI-based lateral insulated gate bipolar transistor comprising the steps of:
1) Providing a thin silicon layer SOI base substrate, wherein the substrate comprises a second conductive type substrate layer, an insulating dielectric layer positioned on the second conductive type substrate layer and a first conductive type drift region positioned on the insulating dielectric layer;
2) Forming a first conductive type anode buffer region and a first conductive type anode well region on the insulating medium layer respectively;
3) Etching a portion of the surface of the first conductivity type anode well region, forming a shallow trench isolation region on the etched surface over the first conductivity type anode well region;
4) Floating the second conductive type floating region inside the first conductive type anode well region;
5) Filling an insulating medium into the shallow trench isolation region;
6) Covering a part of the surface of the first conductive type drift region with a gate dielectric layer; covering the gate contact region on the gate dielectric layer;
7) Forming a second conductive type cathode well region in a partial region above the insulating dielectric layer;
8) Forming a heavily doped first conductivity type cathode region in a partial region of the second conductivity type cathode well region;
forming a heavily doped anode region of the first conductivity type in a partial region of the anode well region of the first conductivity type;
9) Forming a heavily doped second conductivity type cathode region in a partial region of the second conductivity type cathode well region;
forming a heavily doped anode region of the second conductivity type in a partial region of the anode buffer region of the first conductivity type;
10 A cathode contact region is covered on the heavily doped second conductive type cathode region, and the cathode contact region is also covered on part of the surface on the heavily doped first conductive type cathode region;
the anode contact region is respectively covered on a part of the surface above the anode region of the second conductivity type and a part of the surface above the anode region of the heavily doped first conductivity type.
The step 9) and the step 10) comprise a covering process of a surface layer insulating medium.
It is worth noting that the width and depth of the shallow trench isolation region and the second conductivity type floating region can be adjusted; the doping concentration of the second conductivity type floating region and the first conductivity type anode well region can be adjusted.
It should be noted that the above manufacturing method can be properly adjusted according to the actual production process without affecting the structure of the thin silicon layer SOI-based lateral insulated gate bipolar transistor.
The technical effects of the invention are undoubtedly that the invention has the following advantages:
the lateral insulated gate bipolar transistor uses a thin silicon layer SOI base as a substrate, and adopts a design structure of shallow slot isolation and anode floating buffer areas. Compared with a conventional short-circuit anode thin silicon layer SOI-LIGBT device, a segmented short-circuit anode thin silicon layer SOI-LIGBT device, a dielectric isolation anode thin silicon layer SOI-LIGBT device, an anode elevation thin silicon layer SOI-LIGBT device and the like in the prior art, the novel thin silicon layer SOI-based lateral insulated gate bipolar transistor can eliminate the negative resistance effect when the device is conducted on the premise that the smaller turn-off time of the device is ensured, and the working stability of the device is improved; in addition, the design structure of the shallow slot isolation and anode floating buffer area adopted by the device can be realized by adopting the shallow slot isolation process of the integrated circuit manufacturing process, and the design can also reduce the transverse size of the device and improve the current conducting capacity.
Drawings
Fig. 1 is a schematic structural diagram of a conventional shorted anode thin silicon layer SOI-LIGBT device in the prior art;
fig. 2 is a schematic structural diagram of a segmented shorted anode thin silicon layer SOI-LIGBT device in the prior art;
FIG. 3 is a schematic diagram of a dielectric isolation anode thin silicon layer SOI-LIGBT device of the prior art;
fig. 4 is a schematic structural diagram of an SOI-LIGBT device with an elevated thin silicon layer as an anode in the prior art;
fig. 5 is a schematic structural diagram of an embodiment 1 of a thin silicon layer SOI-LIGBT device provided by the present invention.
Fig. 6 is a schematic structural diagram of an embodiment 2 of a thin silicon layer SOI-LIGBT device provided by the present invention.
In the figure: the second conductive type substrate layer 1, the insulating dielectric layer 2, the second conductive type cathode well region 3, the heavily doped first conductive type cathode region 4, the heavily doped second conductive type cathode region 5, the cathode contact region 6, the gate contact region 7, the gate dielectric layer 8, the first conductive type drift region 9, the first conductive type anode buffer region 10, the heavily doped second conductive type anode region 11, the anode contact region 12, the heavily doped first conductive type anode region 13, the shallow trench isolation region 14, the second conductive type relief region 15 and the first conductive type anode well region 16.
Detailed Description
The present invention is further described below with reference to examples, but it should not be construed that the scope of the above subject matter of the present invention is limited to the following examples. Various substitutions and alterations are made according to the ordinary skill and familiar means of the art without departing from the technical spirit of the invention, and all such substitutions and alterations are intended to be included in the scope of the invention.
Example 1:
as shown in fig. 5, a thin silicon layer SOI-based lateral insulated gate bipolar transistor includes: the semiconductor device comprises a P-type substrate layer 1, an insulating medium layer 2, a P-type well region 3, an N+ cathode region 4, a P+ cathode region 5, a cathode contact region 6, a gate contact region 7, a gate medium layer 8, an N-type drift region 9, an N-type anode buffer region 10, a P+ type anode region 11, an anode contact region 12, an N+ type anode region 13, a shallow trench isolation region 14, a P+ type float region 15 and an N-type anode well region 16.
The insulating medium layer 2 is covered on the P-type substrate layer 1; the insulating medium layer 2 is silicon dioxide with the thickness of 2 mu m;
the P-type well region 3, the N-type drift region 9, the N-type anode buffer region 10 and the N-type anode well region 16 are all covered on part of the surface above the insulating medium layer 2; the N-type drift region 9 is silicon with the thickness of 1 mu m, wherein the phosphorus doping concentration is linearly increased along the direction from the cathode to the anode; the doping concentration of the N-type anode well region 16 is preferably 2e16 of phosphorus impurity.
The N+ type anode region 13 and the shallow slot isolation region 14 cover part of the surface above the N type anode well region 16; the doping concentration of the N+ type anode region 13 is that the phosphorus impurity with the concentration more than 19 times is heavily doped, and the preferable depth is 0.3 mu m; the shallow trench isolation region 14 preferably has a width of 2 μm and a depth of 0.5 μm; the shallow slot isolation region 14 is filled with insulating medium layer silicon dioxide;
the P+ type floating empty area 15 floats in the N type anode well region 16; the doping concentration of the P+ type float zone 15 is boron impurity heavy doping with the concentration more than 19 times; the width of the p+ -type float zone 15 is preferably 1 μm; the depth of the p+ -type goaf 15 is preferably 0.3 μm;
the P+ type anode region 11 is positioned inside the N type anode buffer region 10; the doping concentration of the P+ type anode region 11 is boron impurity heavy doping with the concentration more than 19 times, and the preferable depth is 0.3 mu m;
the anode contact region 12 covers a part of the surface above the P+ type anode region 11 and a part of the surface above the N+ type anode region 13, respectively;
the N+ cathode region 4 and the P+ cathode region 5 are positioned in the P-type well region 3; the doping concentration of the N+ cathode region 4 is that the phosphorus impurities with the concentration more than 19 times are heavily doped, and the preferable depth is 0.3 mu m; the doping concentration of the P+ cathode region 5 is boron impurity heavy doping with the concentration more than 19 times, and the preferable depth is 0.3 mu m;
the cathode contact region 6 covers the P+ cathode region 5, and the cathode contact region 6 also covers part of the surface above the N+ cathode region 4;
the gate dielectric layer 8 covers the n+ cathode region 4, and the gate dielectric layer 8 also covers part of the surfaces of the n+ cathode region 4 and the N-type drift region 9;
the gate contact region 7 is covered on the gate dielectric layer 8.
Compared with the transistor manufactured in the prior art, the negative resistance effect of the device in the on process is completely eliminated on the premise of ensuring the smaller off time of the device, or the required extra anode is large in transverse size and weak in current conduction capacity, or the process implementation mode is complex, and the process tolerance is difficult to control. The transistor manufactured by the embodiment is simple in manufacture, the process tolerance is easy to control, the negative resistance effect of the device in the on state can be completely eliminated on the premise of ensuring the smaller turn-off time of the device, the transverse size of the anode is only increased by 2 mu m, the shallow slot isolation depth is only 0.5 mu m, and the current conducting capacity is strong.
Example 2:
as shown in fig. 6, a thin silicon layer SOI-based lateral insulated gate bipolar transistor includes: the semiconductor device comprises a P-type substrate layer 1, an insulating medium layer 2, a P-type well region 3, an N+ cathode region 4, a P+ cathode region 5, a cathode contact region 6, a gate contact region 7, a gate medium layer 8, an N-type drift region 9, an N-type anode buffer region 10, a P+ type anode region 11, an anode contact region 12, an N+ type anode region 13, a shallow trench isolation region 14, a P+ type float region 15 and an N-type anode well region 16.
The insulating medium layer 2 is covered on the P-type substrate layer 1; the insulating medium layer 2 is silicon dioxide with the thickness of 2 mu m;
the P-type well region 3, the N-type drift region 9, the N-type anode buffer region 10 and the N-type anode well region 16 are all covered on part of the surface above the insulating medium layer 2; the N-type drift region 9 is silicon with the thickness of 1 mu m, wherein the phosphorus doping concentration is linearly increased along the direction from the cathode to the anode; the doping concentration of the N-type anode well region 16 is preferably 1e16 of phosphorus impurity.
The N+ type anode region 13 and the shallow slot isolation region 14 cover part of the surface above the N type anode well region 16; the doping concentration of the N+ type anode region 13 is that the phosphorus impurity with the concentration more than 19 times is heavily doped, and the preferable depth is 0.3 mu m; the shallow trench isolation region 14 preferably has a width of 3 μm and a depth of 0.2 μm; the shallow slot isolation region 14 is filled with insulating medium layer silicon dioxide;
the P+ type floating empty area 15 floats in the N type anode well region 16; the doping concentration of the P+ type float zone 15 is boron impurity heavy doping with the concentration more than 19 times; the width of the p+ -type float zone 15 is preferably 2 μm; the depth of the p+ -type goaf 15 is preferably 0.5 μm;
the P+ type anode region 11 is positioned inside the N type anode buffer region 10; the doping concentration of the P+ type anode region 11 is boron impurity heavy doping with the concentration more than 19 times, and the preferable depth is 0.3 mu m;
the anode contact region 12 covers a part of the surface above the P+ type anode region 11 and a part of the surface above the N+ type anode region 13, respectively;
the N+ cathode region 4 and the P+ cathode region 5 are positioned in the P-type well region 3; the doping concentration of the N+ cathode region 4 is that the phosphorus impurities with the concentration more than 19 times are heavily doped, and the preferable depth is 0.3 mu m; the doping concentration of the P+ cathode region 5 is boron impurity heavy doping with the concentration more than 19 times, and the preferable depth is 0.3 mu m;
the cathode contact region 6 covers the P+ cathode region 5, and the cathode contact region 6 also covers part of the surface above the N+ cathode region 4;
the gate dielectric layer 8 covers the n+ cathode region 4, and the gate dielectric layer 8 also covers part of the surfaces of the n+ cathode region 4 and the N-type drift region 9;
the gate contact region 7 is covered on the gate dielectric layer 8.
Compared with the transistor manufactured in the prior art, the negative resistance effect of the device in the on process can be completely eliminated on the premise of ensuring the smaller off time of the device, or the required extra anode has large transverse size and weak current conduction capability, or the process implementation mode is complex, and the process tolerance is difficult to control. The transistor manufactured by the embodiment is simple in manufacture, the process tolerance is easy to control, the negative resistance effect of the device in the on state can be completely eliminated on the premise of ensuring the smaller turn-off time of the device, the transverse size of the anode is only increased by 3 mu m, the shallow slot isolation depth is only 0.2 mu m, and the current conducting capacity is strong.
Claims (9)
1. A thin silicon-on-insulator SOI-based lateral insulated gate bipolar transistor, characterized by: the semiconductor device comprises a second conductive type substrate layer (1), an insulating medium layer (2), a second conductive type cathode well region (3), a heavily doped first conductive type cathode region (4), a heavily doped second conductive type cathode region (5), a cathode contact region (6), a gate contact region (7), a gate medium layer (8), a first conductive type drift region (9), a first conductive type anode buffer region (10), a heavily doped second conductive type anode region (11), an anode contact region (12), a heavily doped first conductive type anode region (13), a shallow trench isolation region (14), a second conductive type floating region (15) and a first conductive type anode well region (16);
the insulating medium layer (2) is covered on the second conductive type substrate layer (1);
the second conductive type cathode well region (3), the first conductive type drift region (9), the first conductive type anode buffer region (10) and the first conductive type anode well region (16) are all covered on the insulating medium layer (2);
the heavily doped first conductivity type anode region (13) and the shallow slot isolation region (14) are covered on the first conductivity type anode well region (16);
the second conductive type floating area (15) floats inside the first conductive type anode well region (16);
the heavily doped second-conductivity-type anode region (11) is positioned inside the first-conductivity-type anode buffer region (10);
the anode contact region (12) covers part of the surface above the anode region (11) of the second conductivity type and part of the surface above the anode region (13) of the heavily doped first conductivity type respectively;
the heavily doped first conductive type cathode region (4) and the heavily doped second conductive type cathode region (5) are positioned inside the second conductive type cathode well region (3);
the cathode contact region (6) covers the heavily doped second conductive type cathode region (5), and the cathode contact region (6) also covers part of the surface above the heavily doped first conductive type cathode region (4);
the grid dielectric layer (8) covers the second conductive type cathode well region (3), and the grid dielectric layer (8) also covers partial surfaces above the heavily doped first conductive type cathode region (4) and the first conductive type drift region (9);
the gate contact region (7) is covered on the gate dielectric layer (8).
2. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: the second conductive type substrate layer (1), the insulating dielectric layer (2) and the first conductive type drift region (9) form a thin silicon layer SOI base substrate.
3. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: the heavily doped first conductivity type cathode region (4) is in contact with the heavily doped second conductivity type cathode region (5).
4. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: the second conductive type cathode well region (3) and the first conductive type anode buffer region (10) are respectively positioned at two sides of the first conductive type drift region (9); the first conductivity type anode well region (16) is in contact with the first conductivity type anode buffer region (10).
5. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: the shallow trench isolation region (14) is respectively contacted with the heavily doped first-conductivity-type anode region (13) and the first-conductivity-type anode buffer region (10).
6. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: the heavily doped second conductivity type anode region (11) is not in contact with the first conductivity type drift region (9), the shallow trench isolation region (14) and the first conductivity type anode well region (16).
7. A thin silicon layer SOI-based lateral insulated gate bipolar transistor as in claim 1 wherein: and the shallow slot isolation region (14) is filled with an insulating medium.
8. A method of fabricating a thin silicon-on-SOI-based lateral insulated gate bipolar transistor comprising the steps of:
1) Providing a thin silicon layer SOI base substrate, wherein the substrate comprises a second conductive type substrate layer (1), an insulating medium layer (2) positioned on the second conductive type substrate layer (1), and a first conductive type drift region (9) positioned on the insulating medium layer (2);
2) Forming a first conductive type anode buffer region (10) and a first conductive type anode well region (16) on the insulating medium layer (2) respectively;
3) Etching a portion of the surface of the first conductivity type anode well region (16), forming a shallow trench isolation region (14) on the etched surface over the first conductivity type anode well region (16);
4) Floating the second conductivity type floating region (15) inside the first conductivity type anode well region (16);
5) Filling an insulating medium into the shallow trench isolation region (14);
6) Covering a part of the surface of the first conductive type drift region (9) with a gate dielectric layer (8); covering the grid electrode contact region (7) on the grid electrode dielectric layer (8);
7) Forming a second conductive type cathode well region (3) in a partial region above the insulating dielectric layer (2);
8) Forming a heavily doped first conductivity type cathode region (4) in a partial region of the second conductivity type cathode well region (3);
forming a heavily doped anode region (13) of the first conductivity type in a partial region of the anode well region (16) of the first conductivity type;
9) Forming a heavily doped second conductivity type cathode region (5) in a partial region of the second conductivity type cathode well region (3);
forming a heavily doped anode region (11) of the second conductivity type in a partial region of the anode buffer region (10) of the first conductivity type;
10 A cathode contact region (6) is covered on the heavily doped second conductive type cathode region (5), and the cathode contact region (6) is also covered on part of the surface on the heavily doped first conductive type cathode region (4);
the anode contact region (12) is respectively covered on a part of the surface above the anode region (11) of the second conductivity type and a part of the surface above the anode region (13) of the heavily doped first conductivity type.
9. A method of fabricating a thin silicon-on-SOI-based lateral insulated gate bipolar transistor as defined in claim 8 wherein: the step 9) and the step 10) comprise a covering process of a surface layer insulating medium.
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| CN112420824B (en) * | 2020-12-09 | 2022-08-19 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
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