CN106992208A - A kind of thin silicone layer SOI bases landscape insulation bar double-pole-type transistor and its manufacture method - Google Patents
A kind of thin silicone layer SOI bases landscape insulation bar double-pole-type transistor and its manufacture method Download PDFInfo
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- CN106992208A CN106992208A CN201610039763.6A CN201610039763A CN106992208A CN 106992208 A CN106992208 A CN 106992208A CN 201610039763 A CN201610039763 A CN 201610039763A CN 106992208 A CN106992208 A CN 106992208A
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- 229920001296 polysiloxane Polymers 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000009413 insulation Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 238000007667 floating Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 230000003139 buffering effect Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001550 time effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention discloses a kind of thin silicone layer SOI bases landscape insulation bar double-pole-type transistor and its manufacture method, the landscape insulation bar double-pole-type transistor is using thin silicone layer SOI bases as substrate, using shallow-trench isolation and the design structure of anode floating buffering area.This new thin silicone layer SOI bases landscape insulation bar double-pole-type transistor is on the premise of the device less turn-off time is ensured, negative resistance effect when can be turned on abatement device, improves the job stability of device；In addition, shallow-trench isolation and the design structure of anode floating buffering area that the device is used can be realized using the shallow grooved-isolation technique of integrated circuit fabrication process, and this design can also reduce the lateral dimension of device, improve current capacity.
Description
Technical field
The present invention relates to the SOI base conductance modulations in semiconductor power technical field of electronic devices
Type high voltage power device, specifically a kind of thin silicone layer SOI bases landscape insulation bar double-pole-type crystal
Pipe.
Background technology
With silicon-on-insulator (SOI：Silicon On Insulator) made for backing material
Landscape insulation bar double-pole-type transistor (LIGBT：Lateral Insulated Gate
Bipolar Transistor), abbreviation SOI-LIGBT, especially thin silicone layer SOI-LIGBT,
It is a key components of SOI high voltage integrated circuits, it has driving simple, electric current
Ability is big, it is easy to integrated advantage, but its turn-off speed is more than lateral double diffused metal-oxygen
Compound-semiconductor effect transistor (LDMOS, Lateral Double-diffused MOSFET)
Turn-off speed it is slow, cause its switching loss larger, it is double that this have impact on SOI landscape insulation bars
Application of the polar transistor in power integrated circuit.
Thin silicone layer SOI-LIGBT devices turn-off speed is improved to reduce the method for switching loss
Mainly there are three classes：
One is to reduce the life-span of nonequilibrium carrier in drift region, increases recombination rate, to carry
High turn-off speed.In fact in reduction drift region while nonequilibrium carrier lifetime, its is non-
Equilbrium carrier sum can also reduce, and this will cause conducting resistance to increase, and institute is in this way
In the presence of it is compromise the problem of；
Two be Minority carrier injection level of the control from anode to drift region, to reach conducting
Resistance and turn-off time it is compromise；
Three be to provide nonequilibrium carrier in anode region to extract passage out, rapid when off to reduce
The sum of nonequilibrium carrier in drift region, to improve the turn-off speed of device.It is non-equilibrium to carry
The structure that stream extracts passage out would generally influence Minority carrier injection efficiency, i.e. influence conducting
When drift region in nonequilibrium carrier sum, so as to influence conducting resistance.Also, in device
In positive opening process, because carrier is from LDMOS conduction modes to LIGBT conduction modes
Conversion, easily there is negative resistance effect in turn on process.
The new construction device that this patent is provided belongs to above-mentioned raising thin silicone layer SOI-LIGBT devices
The 3rd class in part turn-off speed method, by providing novel anode region nonequilibrium carrier
Passage is extracted out to reduce the loss of turn off process, optimize conducting resistance and between the turn-off time
Restriction relation, is completely eliminated the negative resistance effect during forward conduction, so as to reach reduction device
Total losses, the purpose of raising device job stability during part works.
For improving thin silicone layer by providing nonequilibrium carrier extraction passage in anode region
The method of SOI-LIGBT device turn-off speeds, due to top layer silicon very it is thin (typical thickness about 1~
2um), it is difficult to complicated device structure design is realized, in the prior art than more typical device
Structure includes conventional anodes short-circuit structure, separation anode construction, medium isolation anode in short circuit knot
Structure, anode raise medium isolation short-circuit structure etc..Or processing technology is complicated in existing structure,
Need larger additional areas.
The content of the invention
Present invention aim to address in the prior art, processing technology complexity is, it is necessary to larger
Additional areas, the problems such as device forward conduction ability is weak.
To realize that the technical scheme that the object of the invention is used is a kind of such, thin silicone layer SOI
Base landscape insulation bar double-pole-type transistor, it is characterised in that：Including the second conductivity type substrate
Layer, insulating medium layer, the second conduction type negative electrode well region, the conduction type of heavy doping first are cloudy
Polar region, the second conduction type of heavy doping cathodic region, negative contact zone, gate contact region, grid
It is pole dielectric layer, the first conduction type drift region, the first conduction type anode buffer area, heavily doped
Miscellaneous second conduction type anode region, positive contact area, the first conduction type of heavy doping anode region,
Shallow trench isolation region, the second conduction type floating area and the first conduction type anode well region.
The insulating medium layer is covered on the second conductivity type substrate layer.
The second conduction type negative electrode well region, the first conduction type drift region, the first conduction
Type anodes buffering area and the first conduction type anode well region, be covered in insulating medium layer it
On.
It is conductive that heavy doping the first conduction type anode region and shallow trench isolation region are covered in first
On type anodes well region.
Second conduction type floating area's floating is inside the first conduction type anode well region.
The second conduction type of heavy doping anode region is located at the first conduction type anode buffer area
It is internal.
The positive contact area is covered in the part table on the second conduction type anode region respectively
Part surface on face and the first conduction type of heavy doping anode region.
Heavy doping the first conduction type cathodic region and the second conduction type of heavy doping cathodic region
Positioned at the inside of the second conduction type negative electrode well region.
The negative contact zone is covered on the second conduction type of heavy doping cathodic region, described
Negative contact zone is also covered in the part surface on the first conduction type of heavy doping cathodic region.
The gate dielectric layer is covered on the second conduction type negative electrode well region, the grid
Dielectric layer is also covered in heavy doping the first conduction type cathodic region and the first conduction type drift region
On part surface.
The gate contact region is covered on gate dielectric layer.
Further, the second conductivity type substrate layer, insulating medium layer and the first conductive-type
Type drift region constitutes thin silicone layer SOI base substrates.
Further, heavy doping the first conduction type cathodic region and the conductive-type of heavy doping second
Type cathodic region is in contact.
Further, the second conduction type negative electrode well region and the first conduction type anode buffer
Area is located at the both sides of the first conduction type drift region respectively.The first conduction type anode trap
Area is in contact with the first conduction type anode buffer area.
Further, the shallow trench isolation region respectively with heavy doping the first conduction type anode region and
First conduction type anode buffer area is in contact.
Further, heavy doping the second conduction type anode region drifts about with the first conduction type
Area, shallow trench isolation region and the first conduction type anode well region are not contacted.
Further, dielectric is filled in the shallow trench isolation region.
A kind of method for manufacturing thin silicone layer SOI base landscape insulation bar double-pole-type transistors, it is special
Levy and be, comprise the following steps：
1) provide thin silicone layer SOI base substrates, the substrate include the second conductivity type substrate layer,
Positioned at the second conductivity type substrate layer on insulating medium layer, on insulating medium layer
The first conduction type drift region；
2) by the first conduction type anode buffer area and the first conduction type anode well region, respectively
It is formed on insulating medium layer；
3) part surface of the first conduction type anode well region is etched, shallow trench isolation region is formed
Etching surface on the first conduction type anode well region；
4) by second conduction type floating area's floating inside the first conduction type anode well region；
5) dielectric is filled to inside shallow trench isolation region；
6) gate dielectric layer is covered in the part surface on the first conduction type drift region；
Gate contact region is covered on gate dielectric layer；
7) the second conduction type negative electrode well region is formed to the part area on insulating medium layer
Domain；
8) the first conduction type of heavy doping cathodic region is formed at the second conduction type negative electrode well region
Subregion；
The first conduction type of heavy doping anode region is formed at the first conduction type anode well region
Subregion；
9) the second conduction type of heavy doping cathodic region is formed at the second conduction type negative electrode well region
Subregion；
The second conduction type of heavy doping anode region is formed at the first conduction type anode buffer area
Subregion；
10) negative contact zone is covered on the second conduction type of heavy doping cathodic region, it is cloudy
Pole contact zone is also covered in the part surface on the first conduction type of heavy doping cathodic region；
Positive contact area is covered in the part surface on the second conduction type anode region respectively
With the part surface on the first conduction type of heavy doping anode region.
The step 9) and step 10) between include the covering process of top layer dielectric.
What deserves to be explained is, the width in the shallow trench isolation region and the second conduction type floating area
It can be adjusted with depth；The second conduction type floating area and the first conduction type anode trap
The doping concentration in area can be adjusted.
What deserves to be explained is, do not influenceing the thin silicone layer SOI base landscape insulation bar double-pole-types
On the premise of transistor invention structure, above-mentioned manufacture method can be entered according to actual production technique
The appropriate adjustment of row.
The solution have the advantages that unquestionable, the present invention has advantages below：
The landscape insulation bar double-pole-type transistor is used using thin silicone layer SOI bases as substrate
The design structure of shallow-trench isolation and anode floating buffering area.With conventional short circuit of the prior art
Anode thin silicone layer SOI-LIGBT devices, segmentation short circuit anode thin silicone layer SOI-LIGBT devices,
Medium isolates anode thin silicone layer SOI-LIGBT devices and anode raises thin silicone layer SOI-LIGBT
Device etc. is compared, and the new thin silicone layer SOI bases landscape insulation bar double-pole-type transistor is being protected
On the premise of demonstrate,proving the device less turn-off time, negative resistance effect when can be turned on abatement device,
Improve the job stability of device；In addition, shallow-trench isolation and anode floating that the device is used
The design structure of buffering area can be real using the shallow grooved-isolation technique of integrated circuit fabrication process
It is existing, and this design can also reduce the lateral dimension of device, improve current capacity.
Brief description of the drawings
Fig. 1 is the structure of conventional short-circuit anode thin silicone layer SOI-LIGBT devices in the prior art
Schematic diagram；
Fig. 2 is the structure for being segmented short-circuit anode thin silicone layer SOI-LIGBT devices in the prior art
Schematic diagram；
Fig. 3 isolates the structure of anode thin silicone layer SOI-LIGBT devices for medium in the prior art
Schematic diagram；
Fig. 4 is the structural representation that prior art Anodic raises thin silicone layer SOI-LIGBT devices
Figure；
The structure of embodiment 1 for the thin silicone layer SOI-LIGBT devices that Fig. 5 provides for the present invention is shown
It is intended to.
The structure of embodiment 2 for the thin silicone layer SOI-LIGBT devices that Fig. 6 provides for the present invention is shown
It is intended to.
In figure：Second conductivity type substrate layer 1, insulating medium layer 2, the second conduction type are cloudy
Pole well region 3, the first conduction type of heavy doping cathodic region 4, heavy doping the second conduction type negative electrode
Area 5, negative contact zone 6, gate contact region 7, gate dielectric layer 8, the first conduction type
Drift region 9, the first conduction type anode buffer area 10, heavy doping the second conduction type anode
Area 11, positive contact area 12, the first conduction type of heavy doping anode region 13, shallow-trench isolation
Area 14, the second conduction type floating area 15, the first conduction type anode well region 16.
Embodiment
With reference to embodiment, the invention will be further described, but should not be construed this
Invent above-mentioned subject area and be only limitted to following embodiments.Think not departing from above-mentioned technology of the invention
In the case of thinking, according to ordinary skill knowledge and customary means, various replacements are made
And change, it all should include within the scope of the present invention.
Embodiment 1：
As shown in figure 5, a kind of thin silicone layer SOI Ji Hengxiangjueyuanshanshuanjixingjingtiguanbao
Include：P type substrate layer 1, insulating medium layer 2, P type trap zone 3, N+ cathodic regions 4, P+ negative electrodes
Area 5, negative contact zone 6, gate contact region 7, gate dielectric layer 8, N-type drift region 9,
N-type anode buffer area 10, P+ type anode region 11, positive contact area 12, N+ types anode region
13rd, shallow trench isolation region 14, P+ type floating area 15 and N-type anode well region 16.
The insulating medium layer 2 is covered on P type substrate layer 1；The insulating medium layer
2 be the silica of 2 μ m thicks；
The P type trap zone 3, N-type drift region 9, N-type anode buffer area 10 and N-type
Anode well region 16, is covered in the part surface on insulating medium layer 2；The N-type
Drift region 9 is the silicon of 1 μ m thick, and wherein phosphorus doping density is along negative electrode to anode side
To linearly increasing；The doping concentration of the N-type anode well region 16 is preferably 2e16 phosphorus
Impurity.
The N+ types anode region 13 and shallow trench isolation region 14 are covered in N-type anode well region 16
On part surface；The doping concentration of the N+ types anode region 13 is that concentration is more than 19 times
Phosphorus impurities heavy doping more than side, depth preferably is 0.3 μm；The shallow trench isolation region 14
Width be preferably 2 μm, depth is preferably 0.5 μm；Filled out in the shallow trench isolation region 14
Fill insulating medium layer silica；
The floating of P+ type floating area 15 is inside N-type anode well region 16；The P+
The doping concentration in type floating area 15 is the boron impurity heavy doping that concentration is more than more than 19 powers；
The width in the P+ type floating area 15 is preferably 1 μm；The depth in the P+ type floating area 15
Preferably 0.3 μm；
The P+ type anode region 11 is located inside N-type anode buffer area 10；The P+
The doping concentration of type anode region 11 is the boron impurity heavy doping that concentration is more than more than 19 powers,
It is preferred that depth be 0.3 μm；
The positive contact area 12 is covered each by the part table on P+ type anode region 11
Part surface on face and N+ types anode region 13；
The N+ cathodic regions 4 and P+ cathodic regions 5 are located at the inside of P type trap zone 3；Institute
The doping concentration for stating N+ cathodic regions 4 is the phosphorus impurities heavy doping that concentration is more than more than 19 powers,
It is preferred that depth be 0.3 μm；The doping concentration in the P+ cathodic regions 5 is that concentration is more than 19
Boron impurity heavy doping more than power, depth preferably is 0.3 μm；
The negative contact zone 6 is covered on P+ cathodic regions 5, the negative contact zone 6
Also it is covered in the part surface on N+ cathodic regions 4；
The gate dielectric layer 8 is covered on N+ cathodic regions 4, the gate dielectric layer 8
Also it is covered in the part surface on N+ cathodic regions 4 and N-type drift region 9；
The gate contact region 7 is covered on gate dielectric layer 8.
When reaching the guarantee less shut-off of device relative to obtained transistor in the prior art
Between on the premise of negative resistance effect when being completely eliminated break-over of device, or required extra sun
Pole lateral dimension is big, current capacity is weak, otherwise technique implementation is complicated, technique is held
Poor difficult control.Transistor fabrication made from the present embodiment is simple, and process allowance is easy to control,
Negative resistance when ensureing that break-over of device can be completely eliminated on the premise of the device less turn-off time
Effect, anode lateral dimension only increases by 2 μm, and shallow-trench isolation depth is only 0.5 μm, its electricity
Flow ducting capacity strong.
Embodiment 2：
As shown in fig. 6, a kind of thin silicone layer SOI Ji Hengxiangjueyuanshanshuanjixingjingtiguanbao
Include：P type substrate layer 1, insulating medium layer 2, P type trap zone 3, N+ cathodic regions 4, P+ negative electrodes
Area 5, negative contact zone 6, gate contact region 7, gate dielectric layer 8, N-type drift region 9,
N-type anode buffer area 10, P+ type anode region 11, positive contact area 12, N+ types anode region
13rd, shallow trench isolation region 14, P+ type floating area 15 and N-type anode well region 16.
The insulating medium layer 2 is covered on P type substrate layer 1；The insulating medium layer
2 be the silica of 2 μ m thicks；
The P type trap zone 3, N-type drift region 9, N-type anode buffer area 10 and N-type
Anode well region 16, is covered in the part surface on insulating medium layer 2；The N-type
Drift region 9 is the silicon of 1 μ m thick, and wherein phosphorus doping density is along negative electrode to anode side
To linearly increasing；The doping concentration of the N-type anode well region 16 is preferably 1e16 phosphorus
Impurity.
The N+ types anode region 13 and shallow trench isolation region 14 are covered in N-type anode well region 16
On part surface；The doping concentration of the N+ types anode region 13 is that concentration is more than 19 times
Phosphorus impurities heavy doping more than side, depth preferably is 0.3 μm；The shallow trench isolation region 14
Width be preferably 3 μm, depth is preferably 0.2 μm；Filled out in the shallow trench isolation region 14
Fill insulating medium layer silica；
The floating of P+ type floating area 15 is inside N-type anode well region 16；The P+
The doping concentration in type floating area 15 is the boron impurity heavy doping that concentration is more than more than 19 powers；
The width in the P+ type floating area 15 is preferably 2 μm；The depth in the P+ type floating area 15
Preferably 0.5 μm；
The P+ type anode region 11 is located inside N-type anode buffer area 10；The P+
The doping concentration of type anode region 11 is the boron impurity heavy doping that concentration is more than more than 19 powers,
It is preferred that depth be 0.3 μm；
The positive contact area 12 is covered each by the part table on P+ type anode region 11
Part surface on face and N+ types anode region 13；
The N+ cathodic regions 4 and P+ cathodic regions 5 are located at the inside of P type trap zone 3；Institute
The doping concentration for stating N+ cathodic regions 4 is the phosphorus impurities heavy doping that concentration is more than more than 19 powers,
It is preferred that depth be 0.3 μm；The doping concentration in the P+ cathodic regions 5 is that concentration is more than 19
Boron impurity heavy doping more than power, depth preferably is 0.3 μm；
The negative contact zone 6 is covered on P+ cathodic regions 5, the negative contact zone 6
Also it is covered in the part surface on N+ cathodic regions 4；
The gate dielectric layer 8 is covered on N+ cathodic regions 4, the gate dielectric layer 8
Also it is covered in the part surface on N+ cathodic regions 4 and N-type drift region 9；
The gate contact region 7 is covered on gate dielectric layer 8.
When reaching the guarantee less shut-off of device relative to obtained transistor in the prior art
Between on the premise of negative resistance effect when can be completely eliminated break-over of device, or required volume
Outer anode lateral dimension is big, current capacity is weak, otherwise technique implementation is complicated, work
The hardly possible control of skill tolerance.Transistor fabrication made from the present embodiment is simple, and process allowance is easy to control,
It is negative when that break-over of device can be completely eliminated on the premise of ensureing the device less turn-off time
Inhibition effect, anode lateral dimension only increases by 3 μm, and shallow-trench isolation depth is only 0.2 μm, its
Current capacity is strong.
Claims (9)
1. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors, it is characterised in that：Including the second conductivity type substrate layer (1), insulating medium layer (2), second conduction type negative electrode well region (3), the first conduction type of heavy doping cathodic region (4), the second conduction type of heavy doping cathodic region (5), negative contact zone (6), gate contact region (7), gate dielectric layer (8), first conduction type drift region (9), first conduction type anode buffer area (10), the second conduction type of heavy doping anode region (11), positive contact area (12), the first conduction type of heavy doping anode region (13), shallow trench isolation region (14), second conduction type floating area (15) and the first conduction type anode well region (16)；
The insulating medium layer (2) is covered on the second conductivity type substrate layer (1)；
The second conduction type negative electrode well region (3), the first conduction type drift region (9), the first conduction type anode buffer area (10) and the first conduction type anode well region (16), are covered on insulating medium layer (2)；
The first conduction type of heavy doping anode region (13) and shallow trench isolation region (14) are covered on the first conduction type anode well region (16)；
The second conduction type floating area (15) floating is internal in the first conduction type anode well region (16)；
It is internal that the second conduction type of heavy doping anode region (11) is located at the first conduction type anode buffer area (10)；
The positive contact area (12) is covered each by the part surface on the second conduction type anode region (11) and the part surface on the first conduction type of heavy doping anode region (13)；
The first conduction type of heavy doping cathodic region (4) and the second conduction type of heavy doping cathodic region (5) are located at the inside of the second conduction type negative electrode well region (3)；
The negative contact zone (6) is covered on the second conduction type of heavy doping cathodic region (5), and the negative contact zone (6) is also covered in the part surface on the first conduction type of heavy doping cathodic region (4)；
The gate dielectric layer (8) is covered on the second conduction type negative electrode well region (3), and the gate dielectric layer (8) is also covered in the part surface on the first conduction type of heavy doping cathodic region (4) and the first conduction type drift region (9)；
The gate contact region (7) is covered on gate dielectric layer (8).
2. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：The second conductivity type substrate layer (1), insulating medium layer (2) and the first conduction type drift region (9) constitute thin silicone layer SOI base substrates.
3. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：The first conduction type of heavy doping cathodic region (4) and the second conduction type of heavy doping cathodic region (5) are in contact.
4. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：The second conduction type negative electrode well region (3) and the first conduction type anode buffer area (10) are located at the both sides of the first conduction type drift region (9) respectively；The first conduction type anode well region (16) is in contact with the first conduction type anode buffer area (10).
5. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：The shallow trench isolation region (14) is in contact with the first conduction type of heavy doping anode region (13) and the first conduction type anode buffer area (10) respectively.
6. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：The second conduction type of heavy doping anode region (11) does not contact with the first conduction type drift region (9), shallow trench isolation region (14) and the first conduction type anode well region (16).
7. a kind of thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 1, it is characterised in that：Filling dielectric in the shallow trench isolation region (14).
8. a kind of method for manufacturing thin silicone layer SOI base landscape insulation bar double-pole-type transistors, it is characterised in that comprise the following steps：
1) thin silicone layer SOI base substrates are provided, the substrate includes the second conductivity type substrate layer (1), the insulating medium layer (2) on the second conductivity type substrate layer (1), the first conduction type drift region (9) on insulating medium layer (2)；
2) by the first conduction type anode buffer area (10) and the first conduction type anode well region (16), it is respectively formed on insulating medium layer (2)；
3) part surface of the first conduction type anode well region (16) is etched, shallow trench isolation region (14) are formed at the etching surface on the first conduction type anode well region (16)；
4) it is the second conduction type floating area (15) floating is internal in the first conduction type anode well region (16)；
5) to filling dielectric inside shallow trench isolation region (14)；
6) gate dielectric layer (8) is covered in the part surface on the first conduction type drift region (9)；Gate contact region (7) are covered on gate dielectric layer (8)；
7) the second conduction type negative electrode well region (3) is formed to the subregion on insulating medium layer (2)；
8) the first conduction type of heavy doping cathodic region (4) is formed to the subregion of the second conduction type negative electrode well region (3)；
The first conduction type of heavy doping anode region (13) is formed to the subregion of the first conduction type anode well region (16)；
9) the second conduction type of heavy doping cathodic region (5) is formed to the subregion of the second conduction type negative electrode well region (3)；
The second conduction type of heavy doping anode region (11) is formed to the subregion in the first conduction type anode buffer area (10)；
10) negative contact zone (6) are covered on the second conduction type of heavy doping cathodic region (5), negative contact zone (6) are also covered in the part surface on the first conduction type of heavy doping cathodic region (4)；
Positive contact area (12) are covered each by the part surface on the second conduction type anode region (11) and the part surface on the first conduction type of heavy doping anode region (13).
9. a kind of method for manufacturing thin silicone layer SOI base landscape insulation bar double-pole-type transistors according to claim 8, it is characterised in that：The step 9) and step 10) between include the covering process of top layer dielectric.
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