CN109273534A - A kind of device of novel shielding gate power MOS - Google Patents
A kind of device of novel shielding gate power MOS Download PDFInfo
- Publication number
- CN109273534A CN109273534A CN201811280364.4A CN201811280364A CN109273534A CN 109273534 A CN109273534 A CN 109273534A CN 201811280364 A CN201811280364 A CN 201811280364A CN 109273534 A CN109273534 A CN 109273534A
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- Prior art keywords
- grid
- power mos
- polysilicon
- gate power
- shielding gate
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000034655 secondary growth Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of novel shielding gate power MOS device proposed by the present invention, using the polysilicon shield grid that undope, which is not connected with source electrode, and without interlevel oxide layer between grid and shield grid.Floating proposed by the present invention undopes polysilicon shield grid structure, while keeping low Miller capacitance similar with traditional shielded gate structures, the breakdown voltage of device, reduction forward conduction resistance are significantly improved, gate-source capacitance is significantly reduced, that is, reduces the input capacitance of device.Additionally due to without interlevel oxide layer between heavily doped polysilicon grid and the polysilicon shield grid that undope, improve grid oxygen reliability, it can direct thermally grown gate oxide after making shielding gate power MOS device of the invention manufacture groove simultaneously, it eliminates original tradition shielding gate power MOS manufacture shield grid and forms the process flow of gate structure, simplify complex process degree.
Description
Technical field
The invention belongs to power semiconductor device technology fields, and in particular to a kind of device of novel shielding gate power MOS
Structure and its manufacturing method.
Background technique
Novel shielding gate power MOS is primary more by increasing in the structure basis of traditional Trench MOS under slot grid
Crystalline substance deposit and etching form dhield grid, which is generally connected with source potential, shield grid and opposite drain electrode it
Between capacitor, i.e. Miller capacitance.Miller capacitance can be substantially reduced using shielded gate structures, improves the switching speed of device.Simultaneously
It is remarkably improved the breakdown voltage of MOS using the charge balance effect of shield grid, reduces the conducting resistance of device.But due to shielding
Grid are connected with source electrode, this can greatly increase gate-source capacitance.In practical manufacturing process, in long gate oxide, due to polysilicon
The reason of shield grid, the gate oxide at shield grid can grow thinner, this leakage current that will lead to grid oxygen increases, pressure resistance
It reduces, brings the integrity problem of gate oxide.Gate-source capacitance can be made to reduce this shielded gate structures power MOS improvement, cut
Breakdown voltage further increases when only, and device reliability can also be enhanced.
Summary of the invention
The technical problems to be solved by the invention are to provide a kind of power MOS (Metal Oxide Semiconductor) device with shielded gate structures, it can be with
The performance of optimised devices.
To solve the problems, such as that traditional novel shielding gate power MOS gate-source capacitance is excessive, grid oxygen reliability, the present invention proposes one kind
Novel shielding grid structure power MOS (Metal Oxide Semiconductor) device uses the polysilicon to undope, while its current potential in the shield grid of channel bottom deposit
It is set as floating, is not connected with source potential, gate-source capacitance is effectively reduced.Furthermore interlevel oxidation is not done between grid and shield grid
Layer, avoids thus bring grid oxygen reliability problem, while simplifying the process of shielded gate structures manufacture.
Shielded gate structures guarantee that the charge balance effect of the drift region power MOS reduces conducting resistance, improves breakdown voltage, together
Shi Liyong undope polysilicon half insulation modulation pressure-resistant when drift region potential line distribution it is more uniform so that this hair
Bright structure has breakdown voltage more higher than traditional novel shielding gate power MOS.The polysilicon floating that undopes makes tool of the present invention
There is gate-source capacitance identical with tradition Trench VDMOS, and substantially reduces grid leak Miller capacitance.
The technical scheme is that a kind of novel shielding gate power MOS device, including metallization drain terminal electrode 1, N+ lining
Bottom 2, the N- epitaxial layer 3 above N+ substrate 2, N- epitaxial layer top two sides are the area PXing Ti 4, in the area PXing Ti 4
It is provided with mutually independent N+ source region 5, gate oxide 6, deposit, which undopes, polysilicon and to be etched and form shield grid 7, is deposited heavily doped
Miscellaneous polysilicon forms grid 8, the boron-phosphorosilicate glass 9 of deposit, upper surface metallizing source 10.
The heavily doped polysilicon 10 wherein deposited is connect with grid potential, and the polysilicon to undope does not connect with source potential
It connects.
Beneficial effects of the present invention are, reversely when cut-off, due to the deep trench formed with the presence of polysilicon and oxide layer, make
The breakdown voltage for obtaining power MOS is not only determined that the transverse electric field that deep trench introduces is generated by outer layer doping concentration and thickness
Charge balance effect booster action is had to its pressure resistance, furthermore the half of the polysilicon shield grid proposed by the present invention that undope itself
Insulation characterisitic can preferably modulate the electric field in epitaxial layer, thus under conditions of reaching certain voltage, epitaxial layer concentration value can
Selection is higher, this is advantageous for reducing resistance when device forward conduction, reduces power consumption when forward conduction.Additionally due to this hair
The polysilicon shield grid that undope in bright are not connected with source electrode, so that device has grid source identical with traditional Trench VDMOS
Capacitor.Simultaneously because without interlevel oxide layer between heavily doped polysilicon grid and the polysilicon shield grid that undope, thus in flow
In journey can a secondary growth gate oxide, avoid what traditional novel shielding gate power MOS had been grown after having deposited interlevel oxide layer
The partially thin problem of grid oxygen bottom thickness, improves the reliability of component grid oxidizing layer, simplifies process complexity.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional Trench VDMOS device；
Fig. 2 is the structural schematic diagram of embodiment 1；
Fig. 3 is the structural schematic diagram of embodiment 2.
Specific embodiment
A kind of novel shielding gate power MOS device proposed by the present invention, on the basis of original structure, when making shield grid
Using the polysilicon that undopes, and current potential floating, it is not connected with device source electrode.
As shown in Figure 1, being the structural schematic diagram of traditional Trench VDMOS device.Including metallization drain terminal electrode 1, heavily doped
Extension N- floor 3, P-type semiconductor body area 4, heavily doped N-type source region 5, gate oxide 6, polysilicon gate electricity is lightly doped in miscellaneous N-type substrate 2
Boron-phosphorosilicate glass 8 between pole 7, metallization source electrode 10, heavily doped polysilicon gate electrode 7 and metallizing source electrode 9.Phase
Than in novel shielding gate power MOS, traditional Trench VDMOS device Miller capacitance, forward conduction resistance are larger, breakdown voltage,
Switching speed is lower.
Embodiment 1:
As shown in Fig. 2, metallization drain terminal electrode 1, N+ substrate 2, the N- epitaxial layer 3 above N+ substrate 2, the N- epitaxial layer
Top two sides are the area PXing Ti 4, are provided with mutually independent N+ source region 5 in the area PXing Ti 4, gate oxide 6, deposit undopes
Polysilicon and etching form shield grid 7, and deposit heavily doped polysilicon forms grid 8, the boron-phosphorosilicate glass 9 of deposit, upper surface gold
Categoryization source electrode 10.The polysilicon shield grid 7 wherein to undope are not electrically connected with the formation of source electrode 10.
Embodiment 2:
As shown in figure 3, this example difference from Example 1 is, the heavily doped polysilicon grid on surface on the device is divided into
Two parts, the design can further decrease the gate-source capacitance and Miller capacitance of device.The working principle of this example and 1 phase of embodiment
Together.
The solution of the present invention is suitable for P-channel novel shielding gate power MOS device simultaneously.The semiconductor material can be used
Body silicon, silicon carbide, GaAs, indium phosphide or germanium silicon.
Claims (4)
1. a kind of novel shielding gate power MOS device, including metallize drain terminal electrode (1), N+ substrate (2), be located at N+ substrate (2)
The N- epitaxial layer (3) of top, it is characterised in that: N- epitaxial layer (3) the top two sides are the area PXing Ti (4), the area PXing Ti
(4) mutually independent N+ source region (5) is provided in, oxidation forms bottom after N- epitaxial layer (3) upper surface etches and to form groove
Oxide layer (6), successively deposit undopes and polysilicon and etches and form shield grid (7) and deposit heavily doped in the bottom oxidization layer (6)
Miscellaneous polysilicon forms grid (8), successively deposits the boron-phosphorosilicate glass (9) and upper surface metal of deposit in the area PXing Ti (4) upper surface
Change source electrode (10), is electrically connected wherein the polysilicon shield grid (7) to undope are not formed with source electrode (10).
2. novel shielding gate power MOS device according to claim 1, which is characterized in that in heavily doped polysilicon grid
(7) it and undopes between polysilicon shield grid (8) without interlevel oxide layer (11).
3. novel shielding gate power MOS device according to claim 1, which is characterized in that the novel shielding gate power MOS
Device is suitable for P-channel novel shielding gate power MOS device.
4. novel shielding gate power MOS device according to claim 1, which is characterized in that the semiconductor material can be adopted
With body silicon, silicon carbide, GaAs, indium phosphide or germanium silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811280364.4A CN109273534A (en) | 2018-10-30 | 2018-10-30 | A kind of device of novel shielding gate power MOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811280364.4A CN109273534A (en) | 2018-10-30 | 2018-10-30 | A kind of device of novel shielding gate power MOS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109273534A true CN109273534A (en) | 2019-01-25 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811280364.4A Pending CN109273534A (en) | 2018-10-30 | 2018-10-30 | A kind of device of novel shielding gate power MOS |
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| Country | Link |
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| CN (1) | CN109273534A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584365A (en) * | 2020-04-29 | 2020-08-25 | 北京时代民芯科技有限公司 | Manufacturing method of low-miller capacitance groove grid VDMOS device |
| CN111785627A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of IGBT device with trench gate |
| CN112164722A (en) * | 2020-11-04 | 2021-01-01 | 深圳市威兆半导体有限公司 | Shielded gate MOSFET device with uniformly doped channel and processing technology |
| CN116525663A (en) * | 2023-07-05 | 2023-08-01 | 江苏应能微电子股份有限公司 | Trench type power MOSFET device with gate source end clamping structure and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1162665A2 (en) * | 2000-06-08 | 2001-12-12 | Siliconix Incorporated | Trench gate MIS device and method of fabricating the same |
| US20030030092A1 (en) * | 2001-08-10 | 2003-02-13 | Darwish Mohamed N. | Trench MIS device with reduced gate-to-drain capacitance |
| TW200834745A (en) * | 2007-02-02 | 2008-08-16 | Mosel Vitelic Inc | Trench metal-oxide-semiconductor field-effect transistor and fabrication method thereof |
| US7494876B1 (en) * | 2005-04-21 | 2009-02-24 | Vishay Siliconix | Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same |
| CN209626226U (en) * | 2018-10-30 | 2019-11-12 | 贵州恒芯微电子科技有限公司 | A kind of device of novel shielding gate power MOS |
-
2018
- 2018-10-30 CN CN201811280364.4A patent/CN109273534A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1162665A2 (en) * | 2000-06-08 | 2001-12-12 | Siliconix Incorporated | Trench gate MIS device and method of fabricating the same |
| US20030030092A1 (en) * | 2001-08-10 | 2003-02-13 | Darwish Mohamed N. | Trench MIS device with reduced gate-to-drain capacitance |
| US7494876B1 (en) * | 2005-04-21 | 2009-02-24 | Vishay Siliconix | Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same |
| TW200834745A (en) * | 2007-02-02 | 2008-08-16 | Mosel Vitelic Inc | Trench metal-oxide-semiconductor field-effect transistor and fabrication method thereof |
| CN209626226U (en) * | 2018-10-30 | 2019-11-12 | 贵州恒芯微电子科技有限公司 | A kind of device of novel shielding gate power MOS |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584365A (en) * | 2020-04-29 | 2020-08-25 | 北京时代民芯科技有限公司 | Manufacturing method of low-miller capacitance groove grid VDMOS device |
| CN111584365B (en) * | 2020-04-29 | 2024-01-30 | 北京时代民芯科技有限公司 | Manufacturing method of low miller capacitance trench gate VDMOS device |
| CN111785627A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of IGBT device with trench gate |
| CN112164722A (en) * | 2020-11-04 | 2021-01-01 | 深圳市威兆半导体有限公司 | Shielded gate MOSFET device with uniformly doped channel and processing technology |
| CN116525663A (en) * | 2023-07-05 | 2023-08-01 | 江苏应能微电子股份有限公司 | Trench type power MOSFET device with gate source end clamping structure and preparation method thereof |
| CN116525663B (en) * | 2023-07-05 | 2023-09-12 | 江苏应能微电子股份有限公司 | Trench type power MOSFET device with gate source end clamping structure and preparation method thereof |
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