CN108717946A - A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device - Google Patents
A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device Download PDFInfo
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- CN108717946A CN108717946A CN201810727522.XA CN201810727522A CN108717946A CN 108717946 A CN108717946 A CN 108717946A CN 201810727522 A CN201810727522 A CN 201810727522A CN 108717946 A CN108717946 A CN 108717946A
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- 230000011218 segmentation Effects 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000011982 device technology Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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Abstract
The low super junction power device than leading of high voltage of the present invention belongs to semiconductor power device technology field.The present invention introduces segmentation p type buried layer in conventional super-junction structure, and the p type buried layer is between drift region and substrate.The segmentation p type buried layer assisted depletion N-type drift region of introducing, the ratio conducting resistance of device when reducing ON state, in OFF state, the internal field distribution of modulation device improves the breakdown voltage of device.P type buried layer from source to leakage length gradual change can optimize the distribution of charges in drift region, reduce drift region for the charge compensation of superjunction layer and in the charge compensation that drain electrode side increases drift region to superjunction layer in source, realize the charge balance of superjunction layer.The high voltage with segmentation p type buried layer that can get various function admirables using the present invention is low than leading lateral superjunction semiconductor power device.
Description
Technical field
High voltage of the present invention is low to belong to power semiconductor skill than leading novel segmentation P buried layer super junction power devices
Art field.
Background technology
Power semiconductor is also known as semiconductor electronic electrical device, is the core devices in electric energy power conversion.Work(
Major requirement is that have high breakdown voltage BV, low ratio conducting resistance in the design of rate deviceR on,spWith realization ON state and OFF state
Between rapid translating.But the problem of there is " the silicon limit " in power MOSFET device, i.e., it is more resistance to device than conducting resistance
Pressure is increased with the relationship of 2.5 powers, the conduction loss of device can be made to increase than conducting resistance increase, be reduced the performance of device, this
Significantly limit application of the MOSFET power devices in high pressure field.Realize that device compares conducting resistanceR on,spBetween pressure-resistant BV
Good compromise, be the main research work of design power device.
In order to optimize the relationship than conducting resistance and device pressure resistance, the Chen Xing academicians that assist propose superjunction（Super
Juction, abbreviation SJ）Power device, super junction power device replace the drift region of single doping with the PN items being arranged alternately with each other.
It is mutually exhausted between PN items, so the PN items of super junction power device can accomplish that higher doping concentration realizes that the low ratio of device is led
Be powered resistance.However the N items in superjunction PN items not only can mutually be exhausted with P items, can yet be generated and be exhausted with P type substrate, and
From source to drain depletion intensity enhancing, this has just broken delicate charge balance between superjunction PN items, to reduce hitting for device
Wear voltage.
Invention content
It is to be solved by this invention, aiming at substrate auxiliary consumption existing for the lateral super-junction high-voltage power device of above-mentioned tradition
Problem to the greatest extent, proposes a kind of lateral high-voltage device of Ultra-low Specific conducting resistance.The invention reside in by the drift region of superjunction devices
Segmentation p type buried layer assisted depletion drift region is introduced between substrate, is improved the breakdown voltage of device, is reduced the ratio electric conduction of device
Resistance, alleviates " the silicon limit " problem of device.Device each p type buried layer in OFF state can form reverse-biased PN with drift region
Knot, plays the role of assisted depletion drift region, and drift region concentration can also increase to reduce the ratio conducting resistance of device when ON state.
Increased drift region concentration, which also will increase, simultaneously is formed by PN junction between drift region and substrateE maxSo that substrate participation exhausts
Range it is bigger, improve longitudinal pressure resistance of device.
The technical scheme is that：
A kind of superjunction devices that there is the low ratio of segmentation p type buried layer high voltage to lead, structure cell include P type substrate 1, N-type drift
Area 21, the areas PXing Ti 31, the first N-type heavily doped region 23, p-type heavily doped region 32, the second N-type heavily doped region 24, n-type doping item 22,
P-type adulterates item 33, the first p type buried layer 34, the second p type buried layer 35, source electrode 51, polysilicon 52, gate oxide 41, drain electrode electricity
Pole 53, underlayer electrode 54；1 upper surface of the P type substrate is provided with N-type drift region 21；The areas PXing Ti are provided in the drift region
31, upper surface connects with 21 portion of upper surface of N-type drift region, and lower surface connects with the portion of upper surface of P type substrate 1；Institute
There are mutually independent N-type heavily doped region 23 and p-type heavily doped region 32 inside the areas ShuPXing Ti 31；The source electrode 51 is arranged in P
The upper surface of type heavily doped region 32 and the second N-type heavily doped region 23, right end portion are covered in the first N-type heavily doped region 23, institute
State gate oxide 41 and 31 upper surface of PXing Ti areas be set, left end portion covers the first N-type heavily doped region 23, upper surface with it is more
The lower surface of crystal silicon 52 contacts；The second N-type heavily doped region 24 is provided in the N-type drift region 21, upper surface drifts about with N-type
21 portion of upper surface of area connects, and right surface connects with the right surface in 21 part of N-type drift region, and upper surface is provided with drain electrode
53；N-type doping item 22 and p-type the doping item 33 being arranged alternately along Z positive directions in the N-type drift region 21, left surface is all prolonged
It extend into the areas PXing Ti 31, and independently of each other with the first N-type heavily doped region 23, right surface and the second N-type heavily doped region 24
It is in contact, upper surface connects with 21 upper surface of N-type drift region, and lower surface is not in contact with 1 upper surface of P type substrate.It is described
Underlayer electrode 54 is arranged in the lower surface of P type substrate 1.
It is preferred that on 41 right end portion of gate oxide covering n-type doping item 22 and p-type doping item 33.
It is preferred that N-type heavily doped region 23 is on the right of p-type heavily doped region 32, and it is in contact.
It is preferred that 32 left surface of p-type heavily doped region connects with 31 left surface of the areas PXing Ti, the first N-type heavily doped region
23 connect with the 32 upper surface areas Dou HePXing Ti of p-type heavily doped region, 31 upper surface, 23 right surface of the first N-type heavily doped region and following table
In the areas MianPXing Ti 31,32 lower surface of p-type heavily doped region is in the areas PXing Ti 31.
It is preferred that being equipped with the first p type buried layer 34 and the second p type buried layer between P type substrate 1 and N-type drift region 21
35。
It is preferred that 34 upper surface of the first p type buried layer is in the areas PXing Ti 31 and N-type drift region 21, lower surface is set
It sets in P type substrate 1.
It is preferred that 35 upper surface of the second p type buried layer, in N-type drift region 21, lower surface is arranged in P type substrate
In 1.
It is preferred that the length of the first p type buried layer 34 is more than the second p type buried layer 35.
Beneficial effects of the present invention are：The P items 33 and N items 22 of alternating-doping are added first in drift region 21, constitutes super
Junction structure；Secondly segmentation p-type is introduced between drift region 21 and substrate 1 for substrate-assisted depletion effect existing for superjunction devices
Buried layer, it is larger close to source electrode side the first p type buried layer length, it is shorter close to drain electrode side the second p type buried layer length.In OFF state
When, superjunction layer assisted depletion drift region, segmentation p type buried layer also can assisted depletion drift region and substrate.In ON state, high concentration
Drift region can provide the low impedance path of electronics.Because superjunction can use shallow junction deep, the CMOS of structure of the invention compatibility standard
Technique, it is easy to implement in technique.
Description of the drawings
Fig. 1, which is a kind of of the embodiment of the present invention 1, has the segmentation low lateral super junction high-voltage device structure than conducting resistance of p type buried layer
Schematic diagram；
Fig. 2 is a kind of exemplary construction schematic diagram for segmentation p type buried layer being divided into the embodiment of the present invention 2 multistage；
Fig. 3 is a kind of exemplary construction schematic diagram that segmentation p type buried layer is made into linear varying doping P items in the embodiment of the present invention 3；
Fig. 4 is a kind of exemplary construction schematic diagram being put into superjunction in the body of drift region in the embodiment of the present invention 4；
Fig. 5 is a kind of exemplary construction schematic diagram that the P items in superjunction are changed into hafnium in the embodiment of the present invention 5；
Fig. 6 is the width for enabling N width in superjunction layer be more than P items in the embodiment of the present invention 6.
Claims (9)
1. the low segmentation p type buried layer superjunction devices than leading of high voltage, it is characterised in that：Its structure cell includes P type substrate（1）,N
Type drift region（21）, the areas PXing Ti（31）, the first N-type heavily doped region（23）, the first p-type heavily doped region（32）, the second N-type it is heavily doped
Miscellaneous area（24）, n-type doping item（22）, p-type adulterate item（33）, source electrode（51）, polysilicon（52）, gate oxide（41）, leakage
Pole electrode（53）, underlayer electrode（54）；The P type substrate（1）N-type drift region is arranged in upper surface（21）；The N-type drift region
（21）In be provided with the areas PXing Ti（31）, upper surface and N-type drift region（21）Portion of upper surface connects, and lower surface is served as a contrast with p-type
Bottom（1）Portion of upper surface connect；The areas PXing Ti（31）It is internally provided with N-type heavily doped region（23）With p-type heavily doped region
（32）；The source electrode（51）It is arranged in p-type heavily doped region（32）With the first N-type heavily doped region（23）Upper surface, it is right
Hold the first N-type heavily doped region of covering part（23）, the gate oxide（41）It is arranged in the areas PXing Ti（31）Upper surface, it is left
Hold the first N-type heavily doped region of covering part（23）, upper surface and polysilicon（52）Lower surface contact；The N-type drift
Area（21）In be provided with the second N-type heavily doped region（24）, upper surface and N-type drift region（21）Portion of upper surface connects, right
Surface and N-type drift region（21）The right surface in part connects, and upper surface is provided with drain electrode（53）；The N-type drift region
（21）It is middle to be arranged alternately n-type doping item along Z-direction（22）Item is adulterated with p-type（33）, left surface extends into the areas PXing Ti
（31）In, and with the first N-type heavily doped region（23）Independently of each other, right surface and the second N-type heavily doped region（24）It is in contact,
Its upper surface and N-type drift region（21）Upper surface connects, lower surface not with P type substrate（1）Upper surface is in contact.
2. high voltage according to claim 1 is low than leading lateral superjunction devices, it is characterised in that：The gate oxide（41）
The n-type doping item of right end covering part（22）Item is adulterated with p-type（33）.
3. high voltage according to claim 1 is low than leading lateral superjunction devices, it is characterised in that：P-type heavily doped region（32）
Left surface is in contact with p-type bulk portion left surface, right surface and the first N-type heavily doped region（23）Left surface is in contact.
4. high voltage according to claim 3 is low than leading lateral superjunction devices, it is characterised in that：First N-type heavily doped region
（23）With p-type heavily doped region（32）The upper surface areas Jun YuPXing Ti（31）Upper surface connects, left surface and the areas PXing Ti（31）Left-handed watch
Face connects, and right surface is with lower surface in the areas PXing Ti（31）It is interior.
5. high voltage according to claim 1 is low than leading lateral superjunction devices, it is characterised in that：P type substrate（1）With N-type
Drift region（21）Between be equipped with the first p type buried layer（34）With the second p type buried layer（35）.
6. high voltage according to claim 5 is low than leading lateral superjunction devices, it is characterised in that：First p type buried layer（34）
Upper surface is in the areas PXing Ti（31）And N-type drift region（21）Interior, lower surface is arranged in P type substrate（1）In.
7. low than leading lateral superjunction devices according to the high voltage that claim 5 is stated, it is characterised in that：Second p type buried layer（35）On
Surface is in N-type drift region（21）Interior, lower surface is arranged in P type substrate（1）In.
8. low than leading lateral superjunction devices according to the high voltage that claim 5 is stated, it is characterised in that：First p type buried layer（34）'s
Length is more than the second p type buried layer（35）.
9. low than leading lateral superjunction devices according to the high voltage that claim 1 is stated, it is characterised in that：Underlayer electrode（54）Setting exists
P type substrate（1）Lower surface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810727522.XA CN108717946A (en) | 2018-07-05 | 2018-07-05 | A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device |
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| CN201810727522.XA CN108717946A (en) | 2018-07-05 | 2018-07-05 | A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device |
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Cited By (4)
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|---|---|---|---|---|
| CN110112217A (en) * | 2019-04-15 | 2019-08-09 | 杭州电子科技大学 | Anti-single particle burns LDMOS device |
| CN111969043A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof |
| CN112531026A (en) * | 2019-09-17 | 2021-03-19 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
| CN113078204A (en) * | 2021-03-25 | 2021-07-06 | 电子科技大学 | Gallium nitride 3D-RESURF field effect transistor and manufacturing method thereof |
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| CN111969043A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | High-voltage three-dimensional depletion super junction LDMOS device and manufacturing method thereof |
| CN113078204A (en) * | 2021-03-25 | 2021-07-06 | 电子科技大学 | Gallium nitride 3D-RESURF field effect transistor and manufacturing method thereof |
| CN113078204B (en) * | 2021-03-25 | 2022-05-17 | 电子科技大学 | Gallium nitride 3D-RESURF field effect transistor and manufacturing method thereof |
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Application publication date: 20181030 |