CN110112217A - Anti-single particle burns LDMOS device - Google Patents
Anti-single particle burns LDMOS device Download PDFInfo
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- CN110112217A CN110112217A CN201910298966.0A CN201910298966A CN110112217A CN 110112217 A CN110112217 A CN 110112217A CN 201910298966 A CN201910298966 A CN 201910298966A CN 110112217 A CN110112217 A CN 110112217A
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- 239000002245 particle Substances 0.000 title claims abstract description 11
- 238000002513 implantation Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002787 reinforcement Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000005510 radiation hardening Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention proposes a kind of anti-single particles to burn LDMOS device, and the structure is by making a P in the drift region of device‑Buried structure, wherein P‑The doping concentration of buried layer and longitudinal junction depth can be controlled by implantation dosage and Implantation Energy, P‑The lateral dimension and distribution shape of buried layer can be controlled by mask plate patterns.Under the conditions of identical pressure resistance, P‑Buried layer can further improve the doping concentration of drift region, to realize the reduction than conducting resistance.Simultaneously because P‑Buried layer has modulating action to drift region transverse electric field, and the generation rate of electron-hole pair is greatly lowered after heavy ion can be made incident, effectively inhibits the conducting of parasitic transistor, and single event burnout threshold value electricity can be improved under the premise of improving device basic electricity characteristic.
Description
Technical field
The present invention relates to power semiconductor radiation hardening technology, specifically a kind of anti-single particle is burnt
LDMOS device structure.
Background technique
LDMOS (lateral double-diffused MOS) is due to being easier with CMOS technology compatible and switching speed
It is fast and be widely used in making RF integrated circuit and high voltage integrated circuit, can be used for RF power amplifier in wireless telecommunications and
Power supply management device in aerospace system.Currently, LDMOS has evolved to the stage of comparative maturity, external each major company
All there are many LDMOS products to emerge to meet the needs of various power, but aerospace with LDMOS usually to sacrifice basic electricity characteristic
It exchanges the improvement of radiation resistance for for cost, therefore is limited all the time by self performance.Single event burnout (single
Event burnout, SEB) effect belongs to one kind of most serious in heavy ion radiation effect, and heavy ion, which is injected after device, to be lost
Energy can be converted into the electron-hole pair of high concentration, and then cause Transient Currents.N inside LDMOS+Source region, P-
Area and N-Drift region together constitutes parasitic bipolar junction transistor (bipolar junction transistor, BJT), and
The appearance of transient current very likely makes parasitic BJT forward conduction, and transient current can increased dramatically under parasitic BJT amplification
Until burning device.Therefore, aerospace with high performance how is designed under the conditions of not sacrificing LDMOS basic electricity characteristic to use
LDMOS has very important scientific meaning and researching value.
SEB effect was most reported earlier than 1986, was proposed successively there are many SEB reinforcement means later and from emulation and real
It tests two faces and all gives verifying.Wherein effective method is included in device inside progress P+Source region extension, it is parasitic by reducing
The principle of effect improves the anti-SEB performance of device；And buffer layer is introduced between drift region and substrate can reduce substrate knot
The SEB threshold voltage of device can be improved in peak electric field, the principle by reducing electron-hole pair impact ionization rate；In addition, passing through
Introducing minority carrier life time complex centre in drift region can effectively reduce the electron-hole pair concentration excited after heavy ion incidence, in turn
Improve the SEB reinforcement ability of device.It will be appreciated, however, that above method is also sacrificed while raising device anti-SEB ability
The basic electricity characteristic of device, this will limit aerospace semiconductor devices to high performance demand.
Summary of the invention
The present invention proposes a kind of anti-single particle burning for the deficiency in existing semiconductor power device SEB reinforcement technique
LDMOS device structure is ruined, which introduces a P in drift region by ion implantation technique-Buried structure, in identical resistance to press strip
Ratio conducting resistance (the R of device can be reduced under partsp) the SEB threshold voltage of device can be improved again.Wherein P-The doping of buried layer is dense
Degree, longitudinal junction depth and cross direction profiles can be controlled by ion implanting, to be optimal result.
A kind of anti-single particle of the present invention burns LDMOS device, further includes P on the basis of traditional SOI LDMOS structure-It buries
Layer；The P-Buried layer is arranged below shallow-trench isolation oxide layer；P-Buried layer can close to shallow-trench isolation oxide layer bottom or and shallow slot every
A distance is kept from oxide layer；P-Buried layer lateral dimension is not more than shallow-trench isolation oxygen length.
Preferably, the P-Buried layer does integral or section structure according to mask plate.
Preferably, P-The doping concentration of buried layer is higher than drift region concentration.
Preferably, P-The doping concentration of buried layer and longitudinal junction depth are controlled by implantation dosage and Implantation Energy.
The present invention has the advantages that proposing a kind of anti-single particle burns LDMOS device structure, which is infused based on ion
Enter technology and makes a P in device drift region-Buried structure, wherein P-The doping concentration of buried layer and longitudinal junction depth can pass through injection
Dosage and Implantation Energy are controlled, P-The lateral dimension and distribution shape of buried layer can be controlled by mask plate patterns.By
In P-Buried structure can reduce the surface field of device, and the lateral breakdown voltage of drift region can be mentioned significantly under the conditions of same concentration
It is high.And according to the pressure-resistant principle of LDMOS, lateral breakdown voltage reduces with the increase of drift region concentration, therefore proposes knot
Structure can further improve the doping concentration of drift region under the conditions of identical pressure resistance, to realize RspReduction.In addition, due to P-It buries
Layer has modulating action to drift region transverse electric field, can make field distribution is more uniform to thereby reduce peak electric field, enable weight from
The generation rate of electron-hole pair is greatly lowered after sub- incidence, finally realizes the improvement of SEB performance.
Detailed description of the invention
Fig. 1 is traditional SOI LDMOS structure schematic diagram.
Fig. 2 is P-SOI LDMOS structure schematic diagram of the buried layer close to shallow trench isolation region bottom.
Fig. 3 is P on the basis of Fig. 2-The SOI LDMOS structure schematic diagram of buried layer segmentation distribution.
Fig. 4 is P-Buried layer is located at the SOI LDMOS structure schematic diagram below shallow trench isolation region.
Fig. 5 is the SEB threshold voltage curve figure of structure shown in Fig. 1.
Fig. 6 is the SEB threshold voltage curve figure of structure shown in Fig. 2.
Implement principle and simulation result
To make the object, technical solutions and advantages of the present invention clearer, the present invention is carried out below in conjunction with attached drawing specific
It illustrates.
Due to P of the invention-Buried structure is suitable for all LDMOS devices, uses heavy ion irradiation simulating, verifying below
Mode only compares discussion to two kinds of structures shown in Fig. 1 and Fig. 2:
1. incident ion linear energy transfer value (linear energy transfer, LET) is 0.1pC/ μm, incident
Track is in drift region central region (vertical incidence and run through entire device)；The charge density that incident ion generates is Gauss point
Cloth: orbital radius is 0.05 μm, and the initial time that charge generates is 4 × 10-12S, the width of Gaussian function are 2 × 10-12s。
2. Fig. 1 structure is 200V traditional SOI LDMOS: cellular width is 15.0 μm, and buried oxide layer is with a thickness of 2.0 μm, drift
Area is with a thickness of 2.0 μm；Drift region concentration is 1.0 × 1016cm-3, gate oxide thickness 75nm；
3. Fig. 2 is to introduce P-The SOI LDMOS general structure of buried layer, with Fig. 1 the difference is that being introduced in Fig. 2 structure
P-Buried structure specifically includes the P being lightly doped-Type substrate 1, in P-Buried oxide layer 2 and N are sequentially formed on type substrate 1-Drift
Move area 3；P is formed by ion implantation doping-Area 4, P+Ohmic contact regions 5, N+Source contact zone 6, N-Buffer layer 7 and N+Drain contact area
8；Ion implantation technique is used to form P after etching isolated groove-Buried layer 13 deposits shallow-trench isolation oxide layer 9 later；It is situated between in grid oxygen
Polysilicon electrode 10 is made on matter layer, finally deposits source metal electrode 11 and drain metal electrode 12 again.
4. Fig. 3 and Fig. 2 is the difference is that Fig. 3 structure can be by P by changing mask plate shape-Buried layer be made into 13a~
The segmentation of 13c is distributed, and has better protective effect to device surface electric field.
5. Fig. 4 and Fig. 2 changes ion implantation energy for P the difference is that Fig. 4 structure passes through-Buried layer accomplish shallow slot every
From below area, there is better modulating action to transverse electric field.
Conclusion is emulated according to Fig.5, when incident ion LET value is 0.1pC/ μm, the SEB threshold voltage of Fig. 1 structure
It is 120V, is the 60% of breakdown voltage.Simultaneously the structure than conducting resistance Rsp=12.9m Ω cm2。
Conclusion is emulated according to Fig.6, when incident ion LET value is 0.1pC/ μm, the SEB threshold voltage of Fig. 2 structure
It can be improved to 200V, be the 100% of breakdown voltage value.Just because of introducing P in Fig. 2 structure-Buried structure passes through lateral electricity
Drift region electron-hole creation rate is greatly lowered in field modulation, reduces the transient current for acting on parasitic BJT, device
SEB threshold voltage be significantly improved.In addition, the structure than conducting resistance Rsp=10.2m Ω cm2, compare Fig. 1 structure
Reduce 20.9%.
Obviously, those skilled in the art can carry out various changes and deformation without departing from essence of the invention to the present invention
Mind and range.It is noted that above is only a specific embodiment of the present invention, it is not intended to limit the present invention, it is all in this hair
Within bright spirit and principle, the modulation and optimization done should all belong to the covering scope of the claims in the present invention.
Claims (4)
1. anti-single particle burns LDMOS device, it is characterised in that: further include P on the basis of traditional SOI LDMOS structure-Buried layer；
The P-Buried layer is arranged below shallow-trench isolation oxide layer；P-Buried layer can be close to shallow-trench isolation oxide layer bottom or and shallow-trench isolation
Oxide layer keeps a distance；P-Buried layer lateral dimension is not more than shallow-trench isolation oxygen length.
2. anti-single particle according to claim 1 burns LDMOS device, it is characterised in that: the P-Buried layer is according to exposure mask
Version does integral or section structure.
3. anti-single particle according to claim 1 burns LDMOS device, it is characterised in that: P-The doping concentration of buried layer is higher than
Drift region concentration.
4. anti-single particle according to claim 1 burns LDMOS device, it is characterised in that: P-The doping concentration of buried layer and vertical
It is controlled to junction depth by implantation dosage and Implantation Energy.
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| CN201910298966.0A CN110112217A (en) | 2019-04-15 | 2019-04-15 | Anti-single particle burns LDMOS device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863608A (en) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | Single-particle-burnout-resistant high-power transistor and manufacturing method thereof |
| CN113594256A (en) * | 2021-08-18 | 2021-11-02 | 电子科技大学 | High-voltage single-particle-irradiation-resistant PSOI LDMOS device structure |
| CN113871482A (en) * | 2021-09-29 | 2021-12-31 | 杭州电子科技大学 | LDMOS device for improving single-particle burnout resistance effect |
| CN114551574A (en) * | 2022-02-28 | 2022-05-27 | 电子科技大学 | High-voltage single-particle reinforced LDMOS device |
| CN114613843A (en) * | 2022-03-14 | 2022-06-10 | 杭州电子科技大学 | SOI LDMOS device reinforcing structure capable of resisting total dose radiation effect |
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| CN108717946A (en) * | 2018-07-05 | 2018-10-30 | 长沙理工大学 | A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device |
Cited By (8)
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