CN113871482A - LDMOS device for improving single-particle burnout resistance effect - Google Patents

LDMOS device for improving single-particle burnout resistance effect Download PDF

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CN113871482A
CN113871482A CN202111147936.3A CN202111147936A CN113871482A CN 113871482 A CN113871482 A CN 113871482A CN 202111147936 A CN202111147936 A CN 202111147936A CN 113871482 A CN113871482 A CN 113871482A
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silicon carbide
layer
drain
source
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CN113871482B (en
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王颖
杨洋
李兴冀
杨剑群
曹菲
包梦恬
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses an LDMOS device for improving single event burnout resistance effect, belonging to the field of power semiconductor devices and comprising a substrate, wherein a first silicon carbide buried layer is formed on the substrate, and the first silicon carbide buried layer is an N-type silicon carbide buried layer; the active top layer is formed on the first silicon carbide buried layer and comprises a source region, a well region, a drain buffer region, a drain region and a drift region; the device top layer is formed on the surface of the active top layer and comprises a source electrode, a drain electrode, a gate oxide layer, a grid electrode, a field oxide layer and a field plate; the invention effectively reduces the collection of drain electrode electrons, reduces the drain electrode buffer current and prevents the device from generating single-particle burning effect; meanwhile, the surface electric field of the top silicon can be adjusted by adding the P-type silicon carbide buried layer, the electric field peak value of the drift region is reduced, the number of electron hole pairs generated in the drift region is relatively reduced, the collection amount of the drain electrode and the source electrode is reduced, and the probability of single-particle burning of the device is reduced.

Description

LDMOS device for improving single-particle burnout resistance effect
Technical Field
The application relates to the field of power semiconductor devices, in particular to an LDMOS device for improving the single-particle burnout resistance effect.
Background
The LDMOS device is a power device with a double diffusion structure. The technology is to implant two times in the same source/drain region, and the concentration of one implantation is larger (the typical implantation dosage is 1015 cm)-2) Arsenic (As) of (a), the concentration of the other implantation being small (typical dose 1013 cm)-2) Boron (B) of (2). The implant is followed by a high temperature drive-in process, which, because boron diffuses faster than arsenic, diffuses further along the lateral direction under the gate boundary, forming a concentration-graded channel whose channel length is determined by the difference between the two lateral diffusions. In order to increase the breakdown voltage, there is a drift region between the active region and the drain region. The drift region in the LDMOS is the key of the design of the device, and the impurity concentration of the drift region is lower, so that when the LDMOS is connected with high voltage, the drift region can bear higher voltage due to high resistance. The polycrystal of the LDMOS is expanded to the field oxide of the drift region to serve as a field plate, so that the surface electric field of the drift region can be weakened, and the breakdown voltage can be improved. The magnitude of the field plate is closely related to the length of the field plate. To make the field plate function sufficiently, the SiO is designed2The thickness of the layer, the length of the field plate should be designed.
The LDMOS fabrication process combines the BPT and gallium arsenide processes. Different from the standard MOS process, in the device packaging, the LDMOS does not adopt a BeO beryllium oxide isolating layer, but is directly connected on the substrate in a hard mode, so that the heat-conducting property is improved, the high-temperature resistance of the device is improved, and the service life of the device is greatly prolonged. Due to the negative temperature effect of the LDMOS tube, the leakage current of the LDMOS tube is automatically equalized when being heated, and a hot spot is not formed on the local current of the collector like the positive temperature effect of a bipolar tube, so that the LDMOS tube is not easy to damage. The LDMOS transistor greatly enhances the load mismatch and overdrive withstand capability. And similarly, due to the automatic current sharing function of the LDMOS tube, the input-output characteristic curve bends slowly at a 1dB compression point (a saturation section for large signal application), so that the dynamic range is widened, and the amplification of analog and digital television radio frequency signals is facilitated. The LDMOS is approximately linear when small signals are amplified, almost no intermodulation distortion exists, and the correction circuit is greatly simplified. The direct current grid current of the MOS device is almost zero, the bias circuit is simple, and a complex active low-impedance bias circuit with positive temperature compensation is not needed.
For LDMOS, the thickness of the epitaxial layer, the doping concentration, the length of the drift region are the most important characteristic parameters. The breakdown voltage can be increased by increasing the length of the drift region, but this increases the chip area and on-resistance. The withstand voltage and the on-resistance of the high-voltage DMOS device depend on the concentration and the thickness of the epitaxial layer and the compromise selection of the length of the drift region. Since the requirements of withstand voltage and on-resistance for the concentration and thickness of the epitaxial layer are contradictory. High breakdown voltage requires a thick lightly doped epitaxial layer and a long drift region, while low on-resistance requires a thin heavily doped epitaxial layer and a short drift region, so that optimal epitaxial parameters and drift region length must be selected to obtain the minimum on-resistance on the premise of satisfying a certain source-drain breakdown voltage.
However, when the LDMOS device is in an irradiation environment, electron-hole pairs generated in the substrate are collected by the drain and the source, and the drain buffer current of the device is increased, so that the device is more likely to generate a single-particle burnout effect, and therefore, the improvement of the single-particle burnout effect of the conventional LDMOS device becomes a hot problem in the research field. Therefore, further research on the traditional LDMOS is needed, and the structure is improved so as to improve the single event burnout resistance of the device.
Disclosure of Invention
The invention aims to provide an LDMOS device capable of effectively improving the single-event burnout resistance effect, and aims to improve the single-event burnout resistance effect of the device and optimize the overall performance of the device.
In order to achieve the above technical object, the present application provides an LDMOS device for improving resistance to single event burnout effect, comprising:
the device comprises a substrate, wherein a first silicon carbide buried layer is formed on the substrate, and the first silicon carbide buried layer is an N-type silicon carbide buried layer;
the active top layer is formed on the first silicon carbide buried layer and comprises a source region, a well region, a drain buffer region, a drain region and a drift region;
and the device top layer is formed on the surface of the active top layer, and comprises a source electrode, a drain electrode, a gate oxide layer, a grid electrode, a field oxide layer and a field plate.
Preferably, the first buried silicon carbide layer further comprises at least three second buried silicon carbide layers disposed in the N-type buried silicon carbide layer, wherein the second buried silicon carbide layers are disposed on the same horizontal plane.
Preferably, the second buried silicon carbide layer is arranged in the middle of the N-type buried silicon carbide layer;
the second buried silicon carbide layer includes a P1 buried silicon carbide layer, a P2 buried silicon carbide layer, and a P3 buried silicon carbide layer.
Preferably, the source region comprises a P + source region and an N + source region;
the well region comprises a P-well region and a P + well region;
the drain electrode buffer area is an N-drain electrode buffer area;
the drain region is an N + drain region;
the drift region is an N-type drift region.
Preferably, the P + well region is formed on the first buried silicon carbide layer;
the P + source region, the N + source region and the P-well region are sequentially formed on the upper surface of the P + well region.
Preferably, the drift region is formed on one side of the P-well region and the P + well region;
and an N-drain buffer region and an N + drain region are arranged at one end of the drift region, which is far away from the P-well region, the P + well region and the first silicon carbide buried layer, wherein the N + drain region is connected with the drift region through the N-drain buffer region.
Preferably, the upper surface of the N + drain region is provided with a drain electrode;
the upper surfaces of the P + source region and the N + source region are provided with source electrodes;
the upper surfaces of the drift region and the N-drain buffer region are provided with field oxide layers;
one end of the field oxide layer is provided with a grid electrode and a grid oxide layer, wherein the grid electrode is arranged on the upper surface of the grid oxide layer.
Preferably, the lower surface of the gate oxide layer is respectively connected with the P-well region and the drift region.
Preferably, the upper surfaces of the gate and the field oxide layer are on the same horizontal plane;
the upper surfaces of the grid and the field oxide layer are also provided with field plates.
Preferably, the source electrode, the grid electrode and the grid oxide layer are provided with an opening and a first width of the opening;
a misalignment region and a second width of the misalignment region are arranged between the source electrode and the N + source region, wherein a metal material is arranged on the upper surface of the misalignment region, and the metal material is the same as the material of the source electrode;
the first width is the same as the second width.
The structure of the invention has the following beneficial effects:
according to the LDMOS device capable of effectively improving the single-event burnout resistance effect, the silicon carbide buried layer is added between the substrate and the top-layer silicon with the edge, the wide forbidden band characteristic of the silicon carbide material is utilized, the P-type silicon carbide can be used up by the N-type silicon carbide in the single-event impact process, the electrons generated in the substrate need to penetrate through the silicon carbide buried layer to reach the drain electrode, higher energy is needed, the collection of the drain electrode electrons can be effectively reduced due to the addition of the silicon carbide buried layer, the drain electrode buffer current is reduced, and the single-event burnout effect of the device is prevented; meanwhile, the surface electric field of the top silicon layer can be adjusted by adding the P-type silicon carbide buried layer, the electric field peak value of the drift region is reduced, the number of electron hole pairs generated in the drift region is relatively reduced, the collection amount of the drain electrode and the source electrode is reduced, and the probability of single-particle burning of the device is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic structural diagram of an LDMOS device designed based on the present invention to effectively improve the single event burnout resistance;
FIG. 2 is a schematic diagram of a conventional LDMOS device structure;
FIG. 3 is a graph of drain transient current versus time for two devices;
the structure comprises a substrate 1, an N-type silicon carbide layer 2, a P1 silicon carbide buried layer 3, a P2 silicon carbide buried layer 4, a P3 silicon carbide buried layer 5, a P + source region 6, an N + source region 7, a P-well region 8, a P + well region 9, an N-type drift region 10, an N-drain buffer region 11, an N + drain region 12, a source electrode 13, a gate electrode 14, a gate oxide layer 15, a field plate 16, a field oxide layer 17 and a drain electrode 18.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1-3, the present invention provides an LDMOS device for improving the resistance to the single event burnout effect, comprising:
the manufacturing method comprises the following steps of forming a substrate 1, wherein a first silicon carbide buried layer is formed on the substrate 1, and the first silicon carbide buried layer is an N-type silicon carbide buried layer 2;
the active top layer is formed on the first silicon carbide buried layer and comprises a source region, a well region, a drain buffer region, a drain region and a drift region;
and the device top layer is formed on the surface of the active top layer, wherein the device top layer comprises a source electrode 13, a drain electrode 18, a gate oxide layer 15, a gate 14, a field oxide layer 17 and a field plate 16.
Further, the first buried silicon carbide layer further comprises at least three second buried silicon carbide layers arranged in the N-type buried silicon carbide layer 2, wherein the second buried silicon carbide layers are arranged on the same horizontal plane.
Further, the second silicon carbide buried layer is arranged in the middle of the N-type silicon carbide buried layer 2;
the second buried silicon carbide layers include a P1 buried silicon carbide layer 3, a P2 buried silicon carbide layer 4, and a P3 buried silicon carbide layer 5.
Further, the source region comprises a P + source region 6 and an N + source region 7;
the well region comprises a P-well region 8 and a P + well region 9;
the drain buffer region is an N-drain buffer region 11;
the drain region is an N + drain region 12;
the drift region is an N-type drift region 10.
Further, a P + well region 9 is formed on the first buried silicon carbide layer;
the P + source region 6, the N + source region 7 and the P-well region 8 are sequentially formed on the upper surface of the P + well region 9.
Further, an N-type drift region 10 is formed at one side of the P-well region 8 and the P + well region 9;
one end of the drift region, which is far away from the P-well region 8, the P + well region 9 and the first silicon carbide buried layer, is provided with an N-drain buffer region 11 and an N + drain region 12, wherein the N + drain region 12 is connected with the N-type drift region 10 through the N-drain buffer region 11.
Further, the upper surface of the N + drain region 12 is provided with a drain 18;
the upper surfaces of the P + source region 6 and the N + source region 7 are provided with source electrodes 13;
the upper surfaces of the N-type drift region 10 and the N-drain buffer region 11 are provided with field oxide layers 17;
one end of the field oxide layer 17 is provided with a gate 14 and a gate oxide layer 15, wherein the gate 14 is arranged on the upper surface of the gate oxide layer 15.
Further, the lower surface of the gate oxide layer 15 is connected to the P-well region 8 and the N-drift region 10, respectively.
Further, the upper surfaces of the gate 14 and the field oxide layer 15 are on the same level;
the upper surfaces of the gate 14 and the field oxide layer 15 are also provided with a field plate 16.
Further, an opening and a first width of the opening are formed between the source electrode 13 and the gate electrode 14 and between the source electrode and the gate oxide 15;
a second width including a misalignment region and a misalignment region is formed between the source 13 and the N + source region 7, wherein a metal material is further arranged on the upper surface of the misalignment region, and the metal material is the same as that of the source 13;
the first width is the same as the second width.
Example 1: as shown in fig. 1, the LDMOS device of the present invention for effectively improving the single event burnout resistance effect includes: the field-effect transistor comprises a substrate 1, an N-type silicon carbide layer 2, a P1 silicon carbide buried layer 3, a P2 silicon carbide buried layer 4, a P3 silicon carbide buried layer 5, a P + source region 6, an N + source region 7, a P-well region 8, a P + well region 9, an N-type drift region 10, an N-drain buffer region 11, an N + drain region 12, a source electrode 13, a grid electrode 14, a grid oxide layer 15, a field plate 16, a field oxide layer 17 and a drain electrode 18. The P-type silicon carbide buried layer is positioned in the middle of the N-type silicon carbide buried layer 2.
As shown in fig. 2, the conventional LDMOS device includes: the field plate comprises a substrate 1, a P + source region 2, an N + source region 3, a P-well region 4, a P + well region 5, an N-type drift region 6, an N-drain buffer region 7, an N + drain region 8, a source electrode 9, a grid electrode 10, a grid oxide layer 11, a field plate 12, a field oxide layer 13 and a drain electrode 14.
According to the simulation result shown in fig. 3, it can be found that, under the conditions that LET is 5pC/μm and Vd is 15V, the single-particle burnout effect of the structure proposed by the present invention is compared with that of the conventional LDMOS device, because the wide bandgap semiconductor material silicon carbide is added to the structure proposed by the present invention, the electron hole pair in the substrate cannot be collected by the drain and the source, the drain buffer current gradually increases with the lapse of the single-particle incidence time and finally returns to zero, and the single-particle burnout effect does not occur. For the traditional LDMOS device, electrons generated in the substrate are collected by the drain electrode, the buffer current of the drain electrode is gradually increased, so that the parasitic transistor is conducted, and the device is burnt. The structure provided by the invention is proved to have good single event burnout resistance.
The device structure provided by the invention comprises from bottom to top: the device comprises a substrate silicon layer, a silicon carbide buried layer, a top-layer silicon and a device top layer. The silicon carbide buried layers comprise N-type buried layers, and P1, P2 and P3 silicon carbide buried layers are formed in the N-type silicon carbide buried layers through ion implantation. The depletion of N-type silicon carbide is realized by utilizing P-type silicon carbide, in the single-particle burnout effect, single-particle impact can generate electron-hole pairs in the device, and the electron-hole pairs generated in the substrate need to cross the silicon carbide layer by utilizing the wide forbidden band characteristic of the silicon carbide material, so that higher energy is required, and the collection amount of electrons at the drain end can be effectively reduced; meanwhile, due to the addition of the P-type silicon carbide buried layer, the electric field of the drift region can be effectively adjusted, the electric field peak value of the drift region is reduced, electron hole pairs generated in the drift region are relatively reduced, and the collection amount of the drain electrode and the source electrode is reduced. In conclusion, the structure provided by the invention can effectively improve the single-particle burnout resistance of the device.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the present invention in its spirit and scope. Are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An LDMOS device for improving resistance to single event burnout effects, comprising:
the device comprises a substrate, wherein a first silicon carbide buried layer is formed on the substrate, and the first silicon carbide buried layer is an N-type silicon carbide buried layer;
an active top layer formed on the first silicon carbide buried layer, wherein the active top layer includes a source region, a well region, a drain buffer region, a drain region, and a drift region;
the device top layer is formed on the surface of the active top layer, and comprises a source electrode, a drain electrode, a gate oxide layer, a grid electrode, a field oxide layer and a field plate.
2. An LDMOS device for improving resistance to single event burnout according to claim 1, comprising:
the first silicon carbide buried layer further comprises at least three second silicon carbide buried layers arranged in the N-type silicon carbide buried layer, wherein the second silicon carbide buried layers are arranged on the same horizontal plane.
3. An LDMOS device for improving resistance to single event burnout according to claim 2, comprising:
the second silicon carbide buried layer is arranged in the middle of the N-type silicon carbide buried layer;
the second buried silicon carbide layer includes a P1 buried silicon carbide layer, a P2 buried silicon carbide layer, and a P3 buried silicon carbide layer.
4. An LDMOS device for improving resistance to single event burnout according to claim 3, comprising:
the source region comprises a P + source region and an N + source region;
the well region comprises a P-well region and a P + well region;
the drain buffer region is an N-drain buffer region;
the drain region is an N + drain region;
the drift region is an N-type drift region.
5. An LDMOS device for improving resistance to single event burnout according to claim 4, wherein:
the P + well region is formed on the first silicon carbide buried layer;
the P + source region, the N + source region and the P-well region are sequentially formed on the upper surface of the P + well region.
6. An LDMOS device for improving resistance to single event burnout according to claim 5, wherein:
the drift region is formed on one side of the P-well region and the P + well region;
and the N-drain buffer region and the N + drain region are arranged at one end of the drift region, which is far away from the P-well region, the P + well region and the first silicon carbide buried layer, wherein the N + drain region is connected with the drift region through the N-drain buffer region.
7. An LDMOS device for improving resistance to single event burnout according to claim 6, wherein:
the drain electrode is arranged on the upper surface of the N + drain region;
the source electrodes are arranged on the upper surfaces of the P + source region and the N + source region;
the field oxide layers are arranged on the upper surfaces of the drift region and the N-drain buffer region;
one end of the field oxide layer is provided with the grid electrode and the gate oxide layer, wherein the grid electrode is arranged on the upper surface of the gate oxide layer.
8. An LDMOS device for improving resistance to single event burnout according to claim 7, comprising:
the lower surface of the gate oxide layer is respectively connected with the P-well region and the drift region.
9. An LDMOS device as claimed in claim 8 for improving resistance to single event burnout effect wherein:
the grid and the upper surface of the field oxide layer are on the same horizontal plane;
the gate and the upper surface of the field oxide layer are also provided with the field plate.
10. An LDMOS device for improving resistance to single event burnout effect according to claim 9, further characterized in that:
an opening and a first width of the opening are arranged between the source electrode and the grid electrode and between the source electrode and the grid oxide layer;
a misalignment region and a second width of the misalignment region are arranged between the source electrode and the N + source region, wherein a metal material is further arranged on the upper surface of the misalignment region, and the metal material is the same as the source electrode;
the first width is the same as the second width.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551574A (en) * 2022-02-28 2022-05-27 电子科技大学 High-voltage single-particle reinforced LDMOS device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681621A (en) * 2015-02-15 2015-06-03 上海华虹宏力半导体制造有限公司 High-voltage LDMOS for source electrode rising voltage use and manufacturing method for high-voltage LDMOS
US20170309738A1 (en) * 2014-11-24 2017-10-26 Centre National De La Recherche Scientifique (Cnrs Vertically structured power transistor with trench supply electrode
CN108511528A (en) * 2018-04-11 2018-09-07 西安电子科技大学 Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof
CN110112217A (en) * 2019-04-15 2019-08-09 杭州电子科技大学 Anti-single particle burns LDMOS device
CN110518070A (en) * 2019-09-03 2019-11-29 深圳第三代半导体研究院 One kind being suitable for single chip integrated silicon carbide LDMOS device and its manufacturing method
CN113782610A (en) * 2021-09-14 2021-12-10 江苏芯唐微电子有限公司 SOI LDMOS device for improving self-heating effect

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170309738A1 (en) * 2014-11-24 2017-10-26 Centre National De La Recherche Scientifique (Cnrs Vertically structured power transistor with trench supply electrode
CN104681621A (en) * 2015-02-15 2015-06-03 上海华虹宏力半导体制造有限公司 High-voltage LDMOS for source electrode rising voltage use and manufacturing method for high-voltage LDMOS
CN108511528A (en) * 2018-04-11 2018-09-07 西安电子科技大学 Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof
CN110112217A (en) * 2019-04-15 2019-08-09 杭州电子科技大学 Anti-single particle burns LDMOS device
CN110518070A (en) * 2019-09-03 2019-11-29 深圳第三代半导体研究院 One kind being suitable for single chip integrated silicon carbide LDMOS device and its manufacturing method
CN113782610A (en) * 2021-09-14 2021-12-10 江苏芯唐微电子有限公司 SOI LDMOS device for improving self-heating effect

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551574A (en) * 2022-02-28 2022-05-27 电子科技大学 High-voltage single-particle reinforced LDMOS device
CN114551574B (en) * 2022-02-28 2023-09-15 电子科技大学 High-voltage single-particle reinforced LDMOS device

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