CN114551574A - High-voltage single-particle reinforced LDMOS device - Google Patents

High-voltage single-particle reinforced LDMOS device Download PDF

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CN114551574A
CN114551574A CN202210189091.2A CN202210189091A CN114551574A CN 114551574 A CN114551574 A CN 114551574A CN 202210189091 A CN202210189091 A CN 202210189091A CN 114551574 A CN114551574 A CN 114551574A
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injection
drain
region
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ldmos
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CN114551574B (en
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方健
魏亚瑞
雷一博
江秋亮
王腾磊
刘颖
金丽生
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides a high-voltage single-particle reinforced LDMOS device, which comprises a P-type substrate, a deep N-type well region, a P-type buried layer, an N-type drift region, a P-type well region, a source region P + injection, a source region N + injection, a gate oxide layer, a source region Ptop injection, a drain electrode N + injection and polysilicon, wherein the pn junction is changed into two diodes by shortening the width of an original N + doped transverse drain region of a conventional device and adding an N-doping, the two anodes of the two diodes are connected, and the N-N + also forms a new backward diode from the drift region to the drain region, so that the probability of avalanche breakdown is reduced, for the conventional LDMOS device, the whole device is burnt out due to the positive feedback of a parasitic P-N (SCR) structure of a source and the avalanche breakdown of a drain electrode, and the result shows that the breakdown voltage of the single-particle reinforced LDMOS is reduced to 569V from 660V and is reduced by 13.7%, the SEB threshold voltage is increased from 197V to 291V, which is increased by 47.7%. Below the safe BV, the safety and reliability of the LDMOS system can be greatly improved as Vth-SEB increases.

Description

High-voltage single-particle reinforced LDMOS device
Technical Field
The invention relates to the field of semiconductor power devices, in particular to a high-voltage SEB-haranded LDMOS device structure.
Background
With the widespread use of spacecraft in military and civilian aerospace industries, more and more electronic devices are applied to space environments, such as satellite-borne Beidou systems, satellite communication systems, remote sensing systems and the like. When the spacecraft works in the space, radiation particles in the radiation environment generate adverse radiation effects on electronic components on the spacecraft, so that higher requirements are put on the reliability of the spacecraft.
When the LDMOS device is applied to a switching power supply, an LDO (low dropout regulator) and a charging circuit of a spacecraft, the LDMOS device is necessarily influenced by interference radiation. There are a large number of charged particles and cosmic rays in the cosmic space, and when a high energy particle beam in space "bombards" the device, high density unbalanced electron-hole pairs are generated along the heavy ion orbits and drift under the action of a strong electric field, and once the parasitic bipolar transistor is turned on, its positive feedback will result in a large current and a low voltage. A single event current may cause a single event disturbance if a transient current propagates through the combinational logic of the digital circuit and is latched in the memory element.
Single event effects can be classified as recoverable and non-recoverable. The single event upset, single event transient pulse, single event function interruption and the like belong to recoverable effects, generally occur on CMOS devices, soft errors are not enough to damage the devices, and normal work can be recovered through means of current limiting resistors, power supply resetting and the like. Unrecoverable means that a single particle causes physical damage or permanent functional damage to a device, such as single particle latch-up, single particle burnout and single particle gate penetration are two unrecoverable effects occurring on a power MOSFET.
Fig. 1 is a cross-sectional view of a conventional LDMOS device. Comprises a P-type substrate 1 at the bottom; a deep N-type well region 2 located above the right of the P-type substrate 1; the P-type buried layer 3 is positioned above and to the left of the P substrate 1; the N-type drift region 4 is positioned on the right side of the P-type buried layer 3; the P-type well region 5 is positioned above and to the left of the P-type buried layer 3; a source region P + implantation 7 positioned above and to the left of the P-type well region 5; a source region N + implant 8 located to the right of the source region P + implant 7; a gate oxide layer 9 positioned on the upper right of the P-type well region 5; a source region Ptop implant 10 located above the local buried oxide layer 6; a local field oxide layer 11 over the Ptop implant 10; a drain N + injection 12 positioned at the upper right of the local buried oxide layer 6; polysilicon 13 over the gate oxide layer 9.
As shown in fig. 2, which is a schematic diagram of the interior of a single-particle driven device, when particles are driven into the device, due to the existence of the drain terminal and the substrate voltage, under the action of an electric field formed by the voltage, electron-hole pairs on incident trajectories of the particles undergo diffusion drift motion, and finally converge to the drain to form a large transient current. For single-particle transient pulses, it is worth noting that the output driven by the previous stage in the driving circuit is propagated to the input of the next stage, so-called "glitches" are generated, and when the pulse width of the "glitches" is wide enough, the circuit is abnormal.
As shown in fig. 3, when the device is in an off state, particles are driven into the device from the drain, a large number of electron-hole pairs are generated in the particle trajectory, according to the "funnel effect" theory, the electrons move toward the high potential electrode, and the holes move toward the low potential electrode, so as to form a funnel. Along with the lapse of time, the electron hole pair diffuses to the two sides of the particle track under the action of the drain terminal voltage, the current flows to the P-well region, so that a potential is generated between the P-well and the N + source, when the potential is high enough, the PN junction of the P-well/the N + source is forward biased, meanwhile, due to the high potential of the drain electrode, an NPN parasitic transistor formed by the N drift region, the P-well and the N + source is in an amplification state, and finally, the LDMOS device is burnt out along with the increase of the leakage current. Yet another possible explanation is that electron-hole pairs on the particle trajectories undergo impact ionization in the depletion region, causing avalanche breakdown of the device, eventually with excessive current flowing through the device, eventually leading to thermal burn-out of the device.
FIG. 4 shows a single particle irradiation schematic and heavy ion beam parameters. In order to analyze the response of different structures of LDMOS devices to heavy ion beam implantation, the necessary simulations were performed using Sentaurus TCAD. In the simulation, the implantation of the heavy ion beam was simulated by a gaussian distribution having a characteristic radius of 0.5 μm and a distribution range of 30 μm (the longitudinal length of the device is 100 μm). In order to accurately reflect the response mechanism under irradiation, the following physical models are adopted for all simulations, wherein (1) the SRH recombination and Auger recombination which are doping dependent, (2) a thermodynamic model, and (3) the influence of temperature, doping, an electric field and carrier-scattering on the mobility; meanwhile, considering the role of heavy ions in SiO2, SiO2 is considered as an equivalent semiconductor material. Experiments prove that the obtained simulation result is basically consistent with the experimental data in the high-voltage transistor. The response of the LDMOS to SEB depends to a large extent on the bias voltage of the drain and the LET of the heavy ions. As shown in FIG. 4, the mechanism for analyzing SEB is simpler and more intuitive, the LET of heavy ions is set to 0.2pC/μm (1pC/μm is equal to 96.53 MeV-cm 2/mg) and the incident direction of heavy ions is 90 degrees, which varies with the drain voltage, and the incident range is fixed at 30 μm.
Fig. 5 shows the drain current response of SEB after a heavy ion beam is incident from the conventional LDMOS drift region. SEBs are related to the LET orbitals of heavy ions and also to the bias conditions. From the track point of view, the sensitive sites are in regions where the electric field is relatively high or completely depleted. The results indicate that the state in which the LDMOS device is most sensitive to SEB response is the OFF state. Therefore, before performing the SEE simulation, the gate, source and substrate are placed on a common ground (0V) with reference to the device cross-section of the conventional LDMOS in fig. 1. The drain is set at a relatively positive bias with respect to ground from a low voltage to a high voltage. As shown in fig. 4, the heavy ion beam only generates transient current when the drain voltage does not exceed 196V. When SEE gradually disappears, the transient current decreases with the recombination of electron-hole pairs and finally returns to the original state, which is called a safety response in the actual LDMOS circuit. However, impact ionization by the current-induced electric field occurs when the drain voltage reaches 197V and above. Impact ionization of the generated electron-hole can turn on the fragile parasitic p-n-p transistor (T1), resulting in a large current for the lateral parasitic transistor (T1). The positive current feedback between T1 and T2 and avalanche breakdown caused by impact ionization inside the device will work together, generating a large amount of heat, resulting in eventual device destruction.
Aiming at the problems, a high-voltage SEB-haranded LDMOS device structure is provided at present.
Disclosure of Invention
The invention aims to solve the problem that after single-particle irradiation, for a traditional LDMOS device, the whole device is burnt out due to positive feedback of a parasitic p-n-p-n (SCR) structure of a source and avalanche breakdown of a drain. Considering the randomness of single-particle irradiation and the severity of SEB, a feasible SEB-hardened LDMOS structure is provided, and the safety and reliability of an LDMOS system can be greatly improved with the increase of Vth-SEB below safe BV. .
In order to achieve the purpose, the technical scheme of the invention is as follows:
a high-voltage single-particle-reinforced LDMOS device comprises a P-type substrate 1 located at the bottom, a deep N-type well region 2 located on the upper right of the P-type substrate 1, a P-type buried layer 3 located on the upper left of the P-type substrate 1, an N-type drift region 4 located on the right side of the P-type buried layer 3, a P-type well region 5 located on the upper right of the P-type buried layer 3, a source region P + injection 7 located on the upper left of the inside of the P-type well region 5, a source region N + injection 8 located on the right side of the source region P + injection 7 inside the P-type well region 5, a gate oxide layer 9 located on the upper right of the P-type well region 5, a source region Ptop injection 10 located on the upper inside of the N-type drift region 4, a local field oxide layer 11 located on the upper Ptop injection 10, a drain N-injection 14 located on the upper right of the inside of the deep N-type well region 2, a drain N + injection 12 located on the right side of the N-type drift region 4, a drain N + injection 14, Polysilicon 13 over the gate oxide layer 9.
Preferably, the depth of the drain N + implant 12 is shallower than the drain N-implant 14, the length of the drain N + implant 12 in the horizontal direction is shorter than the drain N-implant 14, the horizontal direction is parallel to the surface of the device, the N-drift region 4-the drain N-implant 14-the N-drift region 4 forms two diodes, the two diodes have two anodes connected, at the same time, the drain N-implant 14 and the drain N + implant 12+ also form a new backward diode from the N-drift region 4 to the channel, so as to reduce the probability of avalanche breakdown, and meanwhile, the drain N-implant 14 is located in the drain region, does not affect the channel, and therefore has no effect on the threshold voltage of the LDMOS.
Preferably, the threshold Vth-SEB for single-particle reinforcement increases with the addition of N-doping, but when the N-doping concentration exceeds 1.17cm-3When the concentration is increased, the threshold Vth-SEB of single particle reinforcement is reduced; due to the introduction of N-doping, an original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the threshold Vth-SEB of single-particle reinforcement can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
The working principle of the invention is as follows: the invention shortens the lateral width of the original N + doping of the drain region in the prior art device and adds N-doping, so that the pn junction (Ndrift-N +) in the prior art device is changed into two diodes (Ndrift-N-Ndrift) and has two positive electrodes connected, and meanwhile, the N-N + can also form a new reverse diode to drift from a sewer, thereby reducing the possibility of avalanche breakdown. Meanwhile, the N-doping is positioned in the drain region, so that the channel is not influenced, and the threshold voltage of the LDMOS is not influenced. For reliability and safety considerations, the N-doping concentration corresponding to the Vth-SEB maximum should be the best. At this concentration, the BV of the SEB-reinforced LDMOS was 569V, which is 13.7% lower than the 660V of the conventional LDMOS. Without irradiation, BV can still maintain high voltage 569V, so it can be used in working environment higher than 500V, but once single particle under irradiation occurs, Vth-SEB of LDMOS can increase from 197V to 291V, and safe working voltage can increase by 47.7%.
The invention has the beneficial effects that: as shown in fig. 7, for the conventional LDMOS device, when the drain voltage is 197V or more, the p-n-p-n structure of the parasitic transistor is turned on and the current is increased until thermal burnout occurs. Meanwhile, under the action of a high electric field, the collision ionization of injected carriers can cause avalanche breakdown of the drain region. For the SEB reinforced LDMOS, the drain voltage of 290V or lower can ensure the safety and reliability of the high-voltage LDMOS circuit. Although the BV of the LDMOS decreased from 660V to 569V by 13.7%, the Vth-SEB increased from 197V to 291V by 47.7%. Once SEB occurs, the LDMOS will be destroyed. The safety of the LDMOS circuit is greatly improved at a safe BV in view of the randomness of the single shot and the severity of the SEB.
Drawings
FIG. 1 is a cross-sectional view of a conventional LDMOS device;
FIG. 2 is an internal schematic view of a single particle driven device;
FIG. 3 is a schematic diagram of single particle burnout;
FIG. 4 is a single particle irradiation schematic and heavy ion beam parameters;
FIG. 5 is a diagram showing the drain current response of SEB after a heavy ion beam is incident from the conventional LDMOS drift region;
FIG. 6 is a cross-sectional view of an SEB-pinned LDMOS device of the present invention;
FIG. 7 shows the response of the drain current of SEB after a heavy ion beam is incident from the drift region of the SEB-buried LDMOS device.
The structure comprises a P-type substrate 1, a deep N-type well region 2, a P-type buried layer 3, an N-type drift region 4, a P-type well region 5, a local buried oxide layer 6, a source region P + injection 7, a source region N + injection 8, a gate oxide layer 9, a source region Ptop injection 10, a local field oxide layer 11, a drain electrode N + injection 12, polycrystalline silicon 13 and a drain electrode N-injection 14.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As shown in fig. 6, this embodiment provides a high-voltage single-particle-strengthened LDMOS device, which includes a P-type substrate 1 at the bottom, a deep N-type well region 2 at the upper right of the P-type substrate 1, a P-type buried layer 3 at the upper left of the P-type substrate 1, an N-type drift region 4 at the right side of the P-type buried layer 3, a P-type well region 5 at the upper right of the P-type buried layer 3, a source region P + implant 7 at the upper left of the P-type well region 5, a source region N + implant 8 at the right side of the source region P + implant 7 in the P-type well region 5, a gate oxide layer 9 at the upper right of the P-type well region 5, a source Ptop implant 10 at the upper inside of the N-type drift region 4, a local field oxide layer 11 at the upper part of the source region op implant 10, a drain N-implant 14 at the upper right of the deep N-type well region 2, a gate oxide layer 14 at the upper right of the deep N-type well region, A drain N + implant 12 located at the right side of the drain N-implant 14 at the upper right of the N-type drift region 4, and polysilicon 13 located above the gate oxide layer 9.
The depth of the drain N + injection 12 is shallower than that of the drain N-injection 14, the length of the drain N + injection 12 in the horizontal direction is smaller than that of the drain N-injection 14, the horizontal direction is parallel to the surface of the device, the N-type drift region 4-the drain N-injection 14-the N-type drift region 4 forms two diodes, the 2 diodes are connected with two anodes, meanwhile, the drain N-injection 14 and the drain N + injection 12+ also form a new backward diode from the N-type drift region 4 to a channel, so that the probability of avalanche breakdown is reduced, meanwhile, the drain N-injection 14 is located in the drain region, the channel is not affected, and therefore the threshold voltage of the LDMOS is not affected.
With the addition of N-doping, the threshold Vth-SEB of single-particle reinforcement increases with the increase of the N-doping concentration, but when the N-doping concentration exceeds 1.17cm-3When the concentration is increased, the threshold Vth-SEB of single particle reinforcement is reduced; due to the introduction of N-doping, an original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the threshold Vth-SEB of single-particle reinforcement can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
Compared with the LDMOS with the conventional structure shown in the figure 1, the LDMOS of the invention has the advantages that the width of the original N + doped transverse drain region is shortened, and one N-doping is added, so that the former pn junction (Ndrift-N +) becomes two diodes (Ndrift-N-Ndrift) and two anodes are connected, and meanwhile, the N-N + can also form a new reverse diode from the drift region to the drain region, thereby reducing the possibility of avalanche breakdown.
The lateral width of the original N + doping of the drain region of the conventional structure is shortened and the N-doping is added, so that the pn junction (Ndrift-N +) of the conventional structure is changed into two diodes (Ndrift-N-Ndrift) and has two anode connections, and meanwhile, the N-N + can also form a new reverse diode which drifts from a sewer, thereby reducing the possibility of avalanche breakdown. Meanwhile, the N-doping is positioned in the drain region, so that the channel is not influenced, and the threshold voltage of the LDMOS is not influenced.
The Vth-SEB increases with the increase of the N-doping concentration with the addition of the N-doping, but decreases with the increase of the concentration when the N-doping concentration exceeds 1.17 cm-3. This is because it is difficult to form two reverse diodes between the N-drift and the N-drift when the concentration is too low and not much different from the drift region doping concentration, and it is also difficult to form a reverse diode between the N-and the N + when the N-doping concentration is too high and not much different from the N + doping concentration in the drain. In addition, due to the introduction of N-doping, the original surface field structure is destroyed, resulting in the decrease of BV (breakdown voltage) in the LDMOS as the N-concentration increases. Therefore, it is necessary to find a balance point between BV and Vth-SEB.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (3)

1. The utility model provides a high pressure single particle consolidates LDMOS device which characterized in that: the field oxide type field-effect transistor comprises a P-type substrate (1) positioned at the bottom, a deep N-type well region (2) positioned at the upper right of the P-type substrate (1), a P-type buried layer (3) positioned at the upper left of the P-type substrate (1), an N-type drift region (4) positioned at the right side of the P-type buried layer (3), a P-type well region (5) positioned above the P-type buried layer (3), a source region P + injection (7) positioned at the upper left of the inside of the P-type well region (5), a source region N + injection (8) positioned at the right side of the source region P + injection (7) in the P-type well region (5), a gate oxide layer (9) positioned at the upper right of the P-type well region (5), a source region Ptop injection (10) positioned at the upper inside of the N-type drift region (4), a local oxide layer (11) positioned above the Ptop injection (10), a drain N-type well region (14) positioned at the upper right of the deep N-type well region (2), A drain N + injection (12) positioned at the right side of the drain N-injection (14) at the upper right part of the N-type drift region (4), and polycrystalline silicon (13) positioned above the gate oxide layer (9).
2. The high-voltage single-particle reinforced LDMOS device of claim 1, wherein: the depth of the drain N + injection (12) is shallower than that of the drain N-injection (14), the length of the horizontal direction of the drain N + injection (12) is smaller than that of the drain N-injection (14), the horizontal direction is parallel to the surface of the device, the N-type drift region (4) -drain N-injection (14) -N-type drift region (4) forms two diodes, the two diodes are connected through two anodes, meanwhile, the drain N-injection (14) and the drain N + injection (12) + also form a new backward diode from the N-type drift region (4) to a channel, so that the probability of avalanche breakdown is reduced, meanwhile, the drain N-injection (14) is located in the drain region, the channel is not influenced, and therefore the threshold voltage of the LDMOS is not influenced.
3. The high-voltage single-particle reinforced LDMOS device of claim 1, wherein: with the addition of N-doping, the threshold Vth-SEB of single-particle reinforcement increases with the increase of the N-doping concentration, but when the N-doping concentration exceeds 1.17cm-3When the concentration is increased, the threshold Vth-SEB of single particle reinforcement is reduced; due to the introduction of N-doping, an original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the threshold Vth-SEB of single-particle reinforcement can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
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