CN102044562A

CN102044562A - High-voltage double-diffused metal-oxide-semiconductor (DMOS) device

Info

Publication number: CN102044562A
Application number: CN2009102016906A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-10-16
Filing date: 2009-10-16
Publication date: 2011-05-04

Abstract

The invention discloses a high-voltage double-diffused metal-oxide-semiconductor (DMOS) device, comprising a drift region, a drain region, a channel region, a source region, a gate oxidation layer, a gate and a buried layer, wherein the drift region is positioned between the channel region and the gate region; the source region is formed on the channel region; and the buried layer is buried in the drift region and connected with the channel region. The buried layer and the channel region is respectively provided with a first conducting type, and the source region, the drain region and the drift region are respectively provided with a second conducting type. The buried layer can guide high potential of the drift region introduced by the drain region to a deep part of the drift region, so that the electric field of the drift region is two-dimensionally uniformly distributed, the accumulation of the electric field on the surface of the drift region is reduced, and therefore, the breakdown probability occurring on the surface of the drift region is reduced, and the breakdown voltage is increased. On the basis of increasing the breakdown voltage, by increasing the doping concentration of the drift region or reducing the size of the device, the on resistance of the DMOS can be reduced and the characteristics of the device can be improved.

Description

High pressure DMOS device

Technical field

The present invention relates to a kind of DMOS device, particularly relate to a kind of high pressure DMOS device and manufacturing process thereof with high-breakdown-voltage, low on-resistance.

Background technology

As shown in Figure 1, be the generalized section of conventional high-tension DMOS device.The conventional high-tension device comprises a well region 110, and source region 105, drain region 102, channel region 103 and drift region 101 all are formed in the well region 110.Be formed with gate oxide 106 on channel region, field oxide 107 is formed at above the drift region and between device in the isolated area territory.Grid 108 covers on the gate oxide 106 and covers the subregion of field oxide 107.Between leaking, the source adds high voltage during the work of conventional high-tension DMOS device, the PN junction that forms between drift region and raceway groove is under the high reverse biased effect of drain terminal, to form depletion region between described PN junction, because described PN junction approaches the drift region surface location, electric field will be concentrated in described raceway groove and drift region near surface and easily make device produce surface breakdown.

Easily concentrate on the device drift region surface owing to electric field in the traditional devices, and the puncture voltage of device is reduced, is to reduce the doping content of drift region or increase the drift region size for the puncture voltage that makes device reaches higher value according to a kind of traditional method is arranged, the conducting resistance of drift region is increased, but reduced the performance of device like this.

Summary of the invention

Technical problem to be solved by this invention provides a kind of high pressure DMOS device, can improve the conducting resistance that puncture voltage also reduces device simultaneously.

For solving the problems of the technologies described above, the invention provides a kind of high pressure DMOS device, comprising: a drift region, a drain region, a channel region, a source region, a gate oxide, a field oxide, a grid and a buried regions.Formation one has the well region of second conduction type on the substrate with first conduction type, and described drift region is the part between channel region and drain region in the well region.Described drain region is formed in the described well region and with described drift region one end and joins, and has second conduction type, forms a drain terminal in described drain region.Described channel region is formed in the described well region and with the described drift region other end and joins, and has first conduction type.Described source region is formed in the described channel region, has second conduction type, forms a source end in described source region.Described gate oxide is formed at the channel region top and all covers channel region, and part covers source region and drift region.Described field oxide is formed on the drift region, and an end is the boundary with described drain region, and the other end and described gate oxide join.Described grid is formed on described gate oxide and the field oxide, covers whole described gate oxides, covers all or part of field oxide.Described buried regions is embedded in the described drift region, and the one end is connected with described channel region, and the other end has first conduction type to the horizontal expansion of drain terminal direction.

The ion concentration of buried regions described in the present invention is 2～5 times of ion concentration of described drift region, adjusts buried regions concentration by the dosage that the buried regions ion injects.

The present invention is by making the buried regions with first conduction type below the drift region with second conduction type, described drift region and buried regions have formed a PN junction, and the drift region voltage of described PN junction is introduced by drain terminal, and buried regions voltage is identical with described channel region.Because it is high that the ion concentration of the described drift region of ion concentration of described buried regions is wanted, described PN junction can all vertically exhaust described drift region after adding high pressure.Because the present invention has been Duoed the ability that vertically exhausts of a drift region than conventional high pressure DMOS device, so described drift region can produce exhausting of horizontal vertical two directions, make the drain terminal high potential introduce the depths, drift region, make electric field produce Two dimensional Distribution, improve the uniformity of Electric Field Distribution, reduced the electric field that concentrates on the surface, drift region.Therefore reduced the possibility that the generation of surface, drift region punctures, effectively raised the puncture voltage of described high pressure DMOS device, the puncture voltage that the present invention can improve described high pressure DMOS effectively is approximately 10%.After improving described high pressure DMOS puncture voltage, by increasing the conducting resistance that drift region doping content or reduction of device size can reduce described high pressure DMOS.

Description of drawings

The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:

Fig. 1 is a conventional high-tension DMOS schematic cross-section;

Fig. 2 is a high pressure DMOS schematic cross-section of the present invention.

Embodiment

As shown in Figure 2, the embodiment of the invention mainly comprises: a drift region 1, a drain region 2, a channel region 3, a source region 5, a gate oxide 6, a field oxide 7, a grid 8 and a buried regions 4.

(substrate is not drawn in Fig. 2) formation one has the well region 10 of second conduction type on the substrate with first conduction type, and described drift region 4 is the part between channel region 3 and drain region 2 in the well region 10.Described drain region 2 is formed in the described well region 10 and with described drift region 1 one ends and joins, and has second conduction type, forms a drain terminal 21 in described drain region 2.Described channel region 3 is formed in the described well region 10 and with described drift region 1 other end and joins, and has first conduction type.Described source region 5 is formed in the described channel region 3, has second conduction type, forms a source end 51 in described source region 5.Described gate oxide 6 is a polysilicon gate, is formed at channel region 3 tops and all covers channel region 3.Described field oxide 7 is formed on the drift region 1, and an end is the boundary with described drain region 2, and the other end and described gate oxide 6 join.Described grid 8 is formed on described gate oxide 6 and the field oxide 7, covers whole described gate oxides 6, covers all or part of field oxide 7.Described grid both sides is formed with side wall 9.Described buried regions 4 is embedded in the described drift region 1, and the one end is connected with described channel region 3, and the other end has first conduction type to drain terminal 2 direction horizontal expansions.

The width of described buried regions 4 by its near the edge 41 of drain region direction with and determine with the distance between the edge 31 that described channel region is connected, described buried regions is no more than the edge 81 of described polysilicon gate near the edge 41 of drain region direction, described buried regions 4 and described field oxide have certain overlapping, and the size of overlay region is from the zero field oxide district to the edge 81 of described polysilicon gate.Buried regions width for NLDMOS or PLDMOS is generally 1000 dusts～4000 dusts.The exact value of described buried regions width requires to determine according to the puncture voltage of described high pressure DMOS device.

Described buried regions 4 forms by ion implantation technology, ion implanted region territory scope is injected window by ion and is determined, ion injects window one end and is defined as the edge 41 of described buried regions near the drain region direction, and ion injects edge, boundary 52 or the edge, boundary 31 of described channel region and described drift region or the arbitrary position between edge, above-mentioned two boundaries that the window other end is defined as described channel region and described source region.The buried regions ion will avoid high temperature to pick for a long time into after injecting, and guarantees the buried regions width at 1000 dusts～4000 dusts,

The ion concentration of described buried regions 4 is 2～5 times of ion concentration of described drift region 1, adjusts buried regions concentration by the dosage that the buried regions ion injects.The degree of depth of the energy control buried regions 4 that injects by the buried regions ion, the degree of depth of described buried regions be by the spacing decision between buried regions and the field oxide bottom, and the distance of buried regions between bottom the oxygen of field is 500 dust to 2000 dusts usually.For the asymmetrical NLDMOS of N type, described buried regions district carries out P type ion to be injected, and normally adopts the boron ion to inject, and the implantation dosage scope is 1e12～1e13cm ^-2, the injection energy range is 60KeV～150KeV.For the asymmetrical PLDMOS of P type, described buried regions district carries out N type ion to be injected, and normally adopts phosphorus or arsenic ion to inject, and injects if carry out the buried regions ion of phosphorus, and the implantation dosage scope is 1e12～1e13cm ^-2, the injection energy range is 100KeV～300KeV; Inject if carry out the buried regions ion of arsenic, the implantation dosage scope is 1e12～1e13cm ^-2, the injection energy range is 200KeV～500KeV.The standard of the ion concentration of described buried regions 4 and the accurate control of the degree of depth is to satisfy described high pressure DMOS device when high bias voltage is worked the described drift region 1 of described buried regions 4 upper areas is all exhausted.

The embodiment of the invention provides a kind of process for making of high pressure DMOS device, comprises following main technique step: an active area photoetching and an oxidation; Photoetching of DMOS channel region and ion inject; Buried regions zone photoetching and ion inject; The photoetching of drift region and ion inject; The growth of grid oxygen; The deposit of polysilicon and etching; The ion that leak in the source injects; Later process.

The present invention is by making buried regions below the drift region, it is about 10% to improve the puncture voltage of device effectively, and therefore having living space further increases drift region concentration or reduce device size to reduce conducting resistance.DMOS is an example with 40V N type, and the puncture voltage of traditional devices is 51V, and conducting resistance is 65mohm.mm2; Behind the p type buried layer of device of the present invention by below, increase N type drift region, the puncture voltage of device is increased to 57V from 51V, and conducting resistance is 67mohm.mm2, and is almost constant.If the doping content of N type drift region is improved 50%, the traditional devices puncture voltage drops to 42V from 51V, and its conducting resistance is reduced to 47mohm.mm2; Adopt the puncture voltage of the new unit of the present invention of buried regions still to reach 52V, its conducting resistance is similar to traditional devices.

More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a high pressure DMOS device is characterized in that: comprising: a drift region, a drain region, a channel region, a source region, a gate oxide, a field oxide, a grid and a buried regions; Formation one has the well region of second conduction type on the substrate with first conduction type, and described drift region is the part between channel region and drain region in the well region; Described drain region is formed in the described well region and with described drift region one end and joins, and has second conduction type, forms a drain terminal in described drain region; Described channel region is formed in the described well region and with the described drift region other end and joins, and has first conduction type; Described source region is formed in the described channel region, has second conduction type, forms a source end in described source region; Described gate oxide is formed at the channel region top and all covers channel region, and part covers source region and drift region; Described field oxide is formed on the drift region, and an end is the boundary with described drain region, and the other end and described gate oxide join; Described grid is formed on described gate oxide and the field oxide, covers whole described gate oxides, covers all or part of field oxide; Described buried regions is embedded in the described drift region, and the one end is connected with described channel region, and the other end has first conduction type to the horizontal expansion of drain terminal direction.

2. high pressure DMOS device as claimed in claim 1, it is characterized in that: the width of described buried regions near the edge of drain region direction with and with edge that described channel region is connected between distance, described buried regions is no more than the edge of described polysilicon gate near the drain region direction near the edge of drain region direction; Described buried regions width requires to determine according to the puncture voltage of described high pressure DMOS device.

3. high pressure DMOS device as claimed in claim 1 or 2, it is characterized in that: described buried regions forms by ion implantation technology, ion implanted region territory scope is injected window by ion and is determined, ion injects window one end and is defined as the edge of described buried regions near the drain region direction, and ion injects edge, boundary or the edge, boundary of described channel region and described drift region or the arbitrary position between edge, above-mentioned two boundaries that the window other end is defined as described channel region and described source region.

4. as claim 1 or 2 or 3 described high pressure DMOS devices, it is characterized in that: the ion concentration of described buried regions is 2～5 times of ion concentration of described drift region, adjusts buried regions concentration by the dosage that the buried regions ion injects.

5. as claim 1 or 2 or 3 described high pressure DMOS devices, it is characterized in that: by the energy control buried layer depth that the buried regions ion injects, the degree of depth of described buried regions is 500 dust to 2000 dusts.

6. as claim 4 or 5 described high pressure DMOS devices, it is characterized in that: the standard of the ion concentration of described buried regions and the accurate control of the degree of depth is to satisfy described high pressure DMOS device when high bias voltage is worked the described drift region of described buried regions upper area is all exhausted.

7. as claim 1 or 3 described high pressure DMOS devices, it is characterized in that: when first conduction type that described buried regions had was the N type, the ion implanted impurity of described buried regions was phosphorus or arsenic; When first conduction type that described buried regions had was the P type, the ion implanted impurity of described buried regions was a boron.