CN103633089B - Polysilicon resistance and manufacture method thereof - Google Patents
Polysilicon resistance and manufacture method thereof Download PDFInfo
- Publication number
- CN103633089B CN103633089B CN201210297949.3A CN201210297949A CN103633089B CN 103633089 B CN103633089 B CN 103633089B CN 201210297949 A CN201210297949 A CN 201210297949A CN 103633089 B CN103633089 B CN 103633089B
- Authority
- CN
- China
- Prior art keywords
- region
- conduction type
- field oxide
- type
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of polysilicon resistance, be formed with field oxide on a silicon substrate, polysilicon resistance is arranged on the field oxide of the drain terminal of LDMOS device; In the direction of the width, the two ends of polysilicon resistance are formed with the first resistance electrode and the second resistance electrode respectively, the same widths position at the two ends in drain region is formed respectively the first drain terminal electrode and the second drain terminal electrode, in use, first drain terminal electrode is identical with the voltage added by the first resistance electrode, and the second drain terminal electrode is identical with the voltage added by the second resistance electrode.The invention also discloses a kind of manufacture method of polysilicon resistance.The present invention can improve the operating voltage of polysilicon resistance, and polysilicon resistance can be worked under the bias voltage of more than 700V or-700V.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of polysilicon resistance.The invention still further relates to a kind of manufacture method of polysilicon resistance.
Background technology
As shown in Figure 1, be the structural representation of existing polysilicon resistance, the structure of existing polysilicon resistance comprises: substrate 101; Well region 102, is formed on substrate 101, can be P type trap zone or N-type well region; Local oxidation layer (LOCOS) 103, for isolating active area on the substrate 101; Polysilicon resistance 104, is formed at the top of described local oxidation layer 103.Existing polysilicon resistance is generally applied to the lower occasion of operating voltage, when operating voltage is lower, the thickness of local oxidation layer 103 can hold the difference of the voltage can stood in the voltage on polysilicon resistance 104 and the well region 102 under the field oxide 103 of local completely.If but when existing polysilicon resistance being applied to the higher occasion of operating voltage, then local oxidation layer 103 can be breakdown, suppose that the operating voltage required for polysilicon resistance 104 is 700V, and the breakdown electric field of local oxidation layer 103 is when being 1E6V/cm, the thickness of then required local oxidation layer 103 is at least 7 μm, and the local oxidation layer 103 of thickness like this is can not be getable.The operating voltage of existing polysilicon resistance is the high pressure that cannot reach more than 700V.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of polysilicon resistance, can improve the operating voltage of polysilicon resistance, make polysilicon resistance can more than more than 700V or-700V (more than absolute value) bias voltage under work.For this reason, the present invention also provides a kind of manufacture method of polysilicon resistance.
For solving the problems of the technologies described above, the invention provides a kind of polysilicon resistance, being formed with field oxide on a silicon substrate, polysilicon resistance is arranged on LDMOS(Laterally Diffused Metal Oxide Semiconductor) on the field oxide of the drain terminal of device, direction from the source region of described LDMOS device to drain region is length direction, vertical with this length direction and the direction parallel with described surface of silicon is Width, in the direction of the width, the two ends of described polysilicon resistance are formed with the first resistance electrode and the second resistance electrode respectively, the two ends in described drain region are formed with the first drain terminal electrode and the second drain terminal electrode respectively, described first drain terminal electrode and described first resistance electrode are positioned on the line of same length direction, described second drain terminal electrode and described second resistance electrode are positioned on the line of same length direction, described drain region is not connected with described polysilicon resistance, in use, described first drain terminal electrode is identical with the voltage added by described first resistance electrode, described second drain terminal electrode is identical with the voltage added by described second resistance electrode, and on the source electrode of described LDMOS device, grid, channel region extraction electrode and silicon substrate electrode, institute's making alive is zero.
Further improvement is, described LDMOS device comprises:
Channel region, is made up of the second conduction type well region.
Drift region, is made up of the first conduction type well region, in a lateral direction described drift region and described channel region adjacent.
Described source region is made up of the heavily doped region of the first conduction type be formed in described channel region.
Described drain region is made up of the heavily doped region of the first conduction type be formed in described drift region; Described drain region and described channel region are separated by a segment distance, the field oxide of drain terminal is made to be the first field oxide, described first field oxide is between described drain region and described channel region, the side autoregistration of described drain region and described first field oxide, the opposite side of described first field oxide and described channel region are separated by a segment distance.
The draw-out area of channel region, is made up of the heavily doped region of the second conduction type be formed in described channel region.
Grid polycrystalline silicon, above the surface of silicon being formed at described channel region, the side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to above described first field oxide, and from described source region, to the direction in described drain region, described grid polycrystalline silicon covers described channel region, described drift region described first field oxide and described channel region and described first field oxide of part successively; Between the described channel region of described grid polycrystalline silicon and its covering and described drift region, isolation has gate oxide.
Second conduction type top layer, to be formed in described drift region and near the lower surface of described first field oxide.
Described polysilicon resistance and described grid polycrystalline silicon are formed by same layer etching polysilicon, and described polysilicon resistance and described grid polycrystalline silicon are separated by a segment distance.
Further improvement is, described LDMOS device is N-type LDMOS device, described first conduction type is N-type, described second conduction type is P type, described second conduction type well region is P type trap zone, described first conduction type well region is N-type well region, and described second conduction type top layer is P type top layer; Or, described LDMO
S device is P type LDMOS device, described first conduction type is P type, described second conduction type is N-type, and described second conduction type well region is N-type well region, described first conduction type well region is P type trap zone, and described second conduction type top layer is N-type top layer.
For solving the problems of the technologies described above, the manufacture method of polysilicon resistance provided by the invention comprises the steps:
Form LDMOS device on a silicon substrate.
Polysilicon resistance is formed on the field oxide of the drain terminal of described LDMOS device.
Direction from the source region of described LDMOS device to drain region is length direction with this length direction is vertical and the direction parallel with described surface of silicon is Width; Two ends on the Width of described polysilicon resistance form the first resistance electrode and the second resistance electrode respectively, two ends on the Width in described drain region form the first drain terminal electrode and the second drain terminal electrode respectively, and described first drain terminal electrode and described first resistance electrode are positioned on the line of same length direction, described second drain terminal electrode and described second resistance electrode are positioned on the line of same length direction.
Further improvement is, the step forming described LDMOS device is:
Step one, on described silicon substrate, form the first conduction type well region, form drift region by described first conduction type well region.
Step 2, form field oxide on a silicon substrate.
Step 3, on described silicon substrate, form the second conduction type well region, form channel region by described second conduction type well region; In a lateral direction described drift region and described channel region adjacent; Make the field oxide of drain terminal be the first field oxide, described first field oxide is between described drain region and described channel region.
Step 4, form the second conduction type top layer by ion implantation technology, described second conduction type top layer is arranged in described drift region and near the lower surface of described first field oxide.
Step 5, form gate oxide in described silicon substrate front, depositing polysilicon layer on described gate oxide.
Step 6, carry out chemical wet etching form grid polycrystalline silicon and described polysilicon resistance simultaneously to described polysilicon, described polysilicon resistance and described grid polycrystalline silicon are separated by a segment distance; Described grid polycrystalline silicon is positioned at above the surface of silicon of described channel region, the side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to above described first field oxide, and from described source region, to the direction in described drain region, described grid polycrystalline silicon covers described channel region, described drift region described first field oxide and described channel region and described first field oxide of part successively.
Step 7, the source and drain of carrying out the first conduction type are infused in the heavily doped region of the first conduction type formed in described channel region and in described drift region, and described source region is made up of the heavily doped region of the first conduction type be formed in described channel region; Described drain region is made up of the heavily doped region of the first conduction type be formed in described drift region; The side autoregistration of described source region and described grid polycrystalline silicon, the side autoregistration of described drain region and described first field oxide.
Step 8, the heavy doping ion of carrying out the second conduction type are infused in the draw-out area forming channel region in described channel region.
Further improvement is, described LDMOS device is N-type LDMOS device, described first conduction type is N-type, described second conduction type is P type, described second conduction type well region is P type trap zone, described first conduction type well region is N-type well region, and described second conduction type top layer is P type top layer.
Further improvement is, N-type well region described in step one is increased temperature by ion implantation and pushes away trap and formed, and the implanted dopant of the ion implantation of described N-type well region is phosphorus, Implantation Energy is 100keV ~ 300keV, implantation dosage is 10
11cm
-2~ 10
14cm
-2, the temperature that the high temperature of described N-type well region pushes away trap is 1000 DEG C ~ 1200 DEG C, the time is 100 minutes ~ 500 minutes; Described P type trap zone in step 3 is formed in described N-type well region by ion implantation, and the implanted dopant of the ion implantation of described P type trap zone is boron, Implantation Energy is 0keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2, inject number of times be one or many inject.
Further improvement is, the implanted dopant of the ion implantation of the described P type top layer in step 4 is boron, Implantation Energy is 100keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2.
Further improvement is, the implanted dopant phosphorus that the described source and drain of step 7 is injected or arsenic, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject;
The implanted dopant boron of the ion implantation of the draw-out area of described channel region, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.
Further improvement is, described LDMOS device is P type LDMOS device, described first conduction type is P type, described second conduction type is N-type, described second conduction type well region is N-type well region, described first conduction type well region is P type trap zone, and described second conduction type top layer is N-type top layer.
The present invention is by the field oxide that polysilicon resistance is arranged on the drain terminal of LDMOS device, and in use, while the voltage that the first resistance electrode and second resistance electrode of polysilicon resistance are added, it is identical that the first drain terminal electrode in drain region and the second drain terminal electrode also add corresponding voltage, and the source electrode of LDMOS device, grid, on channel region extraction electrode and silicon substrate electrode, institute's making alive is zero, N-type LDMOS device is corresponded to when the voltage added by the first drain terminal electrode or the second drain terminal electrode is increased to 700V(gradually from 0V) time, or correspond to P type LDMOS device when the voltage added by the first drain terminal electrode or the second drain terminal electrode increases (increase of absolute value) gradually from 0V to-700V() time, can depletion region be formed in drift region and this depletion region can along with the increase of the voltage of drain terminal electrode broadening gradually.
When the voltage of the first drain terminal electrode or the second drain terminal electrode is lower, time under the field oxide that depletion region does not have broadening to cover to polysilicon resistance, polysilicon resistance is identical with the current potential in the silicon under its field oxide, as current potential in the silicon under the field oxide below the first resistance electrode is identical with the first drain terminal electrode, therefore in silicon under field oxide below the first resistance electrode, current potential is also just identical with the polysilicon resistance current potential at the first resistance electrode place, so now field oxide does not bear voltage.
When the voltage of the first drain terminal electrode or the second drain terminal electrode is higher, time under the field oxide that depletion region broadening covers to polysilicon resistance, because a part of drain terminal electrode institute making alive can be shared in depletion region, so have potential difference between silicon depletion region under the field oxide of polysilicon resistance and drain terminal electrode, therefore also have identical potential difference between silicon depletion region under the field oxide of polysilicon resistance and polysilicon resistance, this potential difference for polysilicon resistance to drain region lateral separation between the width of silicon depletion region that formed, the Breadth Maximum of this depletion region is also the lateral separation of polysilicon resistance to drain region, due to polysilicon resistance arrange relatively near drain region, therefore therefore polysilicon resistance can not be very large with the potential difference in the silicon under its field oxide covered, the field oxide of general thickness as 4000 dusts is can be proof.Therefore, as long as institute's making alive is lower than the puncture voltage of this LDMOS on drain region and polysilicon resistance, polysilicon resistance of the present invention just can normally work.So in the direction of the width, drain region and polysilicon resistance can be taken as 0V to 700V(and correspond to N-type LDMOS device) or 0V to-700V(corresponding to P type LDMOS device) between any value.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing polysilicon resistance;
Fig. 2 is the structural representation of embodiment of the present invention polysilicon resistance;
Fig. 3 is the voltage-current curve figure of embodiment of the present invention polysilicon resistance;
Fig. 4 A-Fig. 4 D is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention polysilicon resistance.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the present invention polysilicon resistance.Embodiment of the present invention polysilicon resistance, the LDMOS device adopted in embodiment of the present invention polysilicon resistance is described for N-type LDMOS device, and embodiment of the present invention polysilicon resistance comprises:
One P-type silicon substrate 1, described silicon substrate 1 is formed with N-type well region 2, silicon substrate 1 is also formed with field oxide 3.Described N-type well region 2 was increased temperature by ion implantation to push away trap formation before the described field oxide 3 of formation, and the implanted dopant of the ion implantation of described N-type well region 2 is phosphorus, Implantation Energy is 100keV ~ 300keV, implantation dosage is 10
11cm
-2~ 10
14cm
-2, the temperature that the high temperature of described N-type well region 2 pushes away trap is 1000 DEG C ~ 1200 DEG C, the time is 100 minutes ~ 500 minutes.Described field oxide 3 is local oxidation layer (LOCOS), and thickness is 4000 dust ~ 8000 dusts.
Described P-type silicon substrate 1 is formed with LDMOS device, and described LDMOS device comprises:
Channel region 4, is made up of P well region, and the P type trap zone of described channel region 4 is formed in described N-type well region 2 by ion implantation, and the implanted dopant of the ion implantation of described P type trap zone is boron, Implantation Energy is 0keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2, inject number of times be one or many inject.
Drift region, is made up of N-type well region 2, in a lateral direction described drift region and described channel region 4 adjacent.
Source region 8, is made up of the heavily doped region of the N-type be formed in described channel region 4 and N+ district.
Drain region 9, is made up of the heavily doped region of the N-type be formed in described drift region and N+ district.Described source region 8 and N+ district, described drain region 9 inject by source and drain to be formed simultaneously, it is after follow-up grid polycrystalline silicon 6 is formed that described source and drain is injected, utilizing grid polycrystalline silicon 6 and field oxide 3 to do, hardmask carries out injecting, and the implanted dopant phosphorus that described source and drain is injected or arsenic, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.
Described drain region 9 and described channel region 4 are separated by a segment distance, the field oxide 3 of drain terminal is made to be the first field oxide 3, described first field oxide 3 is between described drain region 9 and described channel region 4, the side autoregistration of described drain region 9 and described first field oxide 3, the opposite side of described first field oxide 3 and described channel region 4 are separated by a segment distance.
The draw-out area 10 of channel region, is made up of the heavily doped region of the P type be formed in described channel region 4 and P+ district.Being formed by ion implantation of the draw-out area 10 of described channel region, the implanted dopant boron of this ion implantation, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.
Grid polycrystalline silicon 6, be formed at silicon substrate 1 surface of described channel region 4, the side autoregistration of described source region 8 and described grid polycrystalline silicon 6, the opposite side of described grid polycrystalline silicon 6 extends to above described first field oxide 3, and from described source region 8, to the direction in described drain region 9, described grid polycrystalline silicon 6 covers described channel region 4, described drift region described first field oxide 3 and described channel region 4 and described first field oxide 3 of part successively; Between the described channel region 4 of described grid polycrystalline silicon 6 and its covering and described drift region, isolation has gate oxide.
P type top layer 5, to be formed in described drift region and near the lower surface of described first field oxide 3.Described P type top layer is formed by ion implantation after N-type well region 2 and P type trap zone are formed, before gate oxide formation, and the implanted dopant of the ion implantation of described P type top layer is boron, Implantation Energy is 100keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2.Described P type top layer 5 is also formed in described drift region outside described first field oxide 3 and described channel region 4 simultaneously, owing to not having the stop of described first field oxide 3, the described drift region of described P type top layer 5 outside described first field oxide 3 and the degree of depth in described channel region 4 are less than the degree of depth of the described P type top layer 5 be positioned at bottom described first field oxide 3.
Polysilicon resistance 7, on the field oxide 3 being formed in the drain terminal of LDMOS device, described polysilicon resistance 7 and described grid polycrystalline silicon 6 are formed by same layer etching polysilicon, described polysilicon resistance 7 and described grid polycrystalline silicon 6 are separated by a segment distance, can regulate the resistance value of described polysilicon resistance by carrying out described polysilicon resistance 7 adulterating.Direction from the source region 8 of described LDMOS device to drain region 9 is length direction, vertical with this length direction and and the surperficial parallel direction of described silicon substrate 1 be Width, in the direction of the width, the two ends of described polysilicon resistance 7 are formed with the first resistance electrode 7a and the second resistance electrode 7b respectively, the two ends in described drain region 9 are formed with the first drain terminal electrode 9a and the second drain terminal electrode 9b respectively, described first drain terminal electrode 9a and described first resistance electrode 7a is positioned on the line of same length direction, described second drain terminal electrode 9b and described second resistance electrode 7b is positioned on the line of same length direction, described drain region 9 is not connected with described polysilicon resistance 7.Described first resistance electrode 7a, the second resistance electrode 7b, described second drain terminal electrode 9b and described second resistance electrode 7b are drawn by metal contact hole.Source electrode is drawn by metal contact hole in described source region 8, channel region extraction electrode is drawn by metal contact hole in the draw-out area 10 of described channel region, described grid polycrystalline silicon 6 draws grid by metal contact hole, and described P-type silicon substrate 1 is also connected with silicon substrate electrode.In use, described first drain terminal electrode 9a is identical with the voltage added by described first resistance electrode 7a, described second drain terminal electrode 9b is identical with the voltage added by described second resistance electrode 7b, and on described source electrode, described grid, described channel region extraction electrode and described silicon substrate electrode, institute's making alive is zero.
The embodiment of the present invention is by being arranged on the field oxide of the drain terminal of N-type LDMOS device by polysilicon resistance 7, and in use, while the voltage that the first resistance electrode 7a and the second resistance electrode 7b of polysilicon resistance 7 are added, it is identical that the first drain terminal electrode 9a in drain region 9 and the second drain terminal electrode 9b also add corresponding voltage, and the source electrode of N-type LDMOS device, grid, on channel region extraction electrode and silicon substrate electrode, institute's making alive is zero, when the voltage added by the first drain terminal electrode 9a or the second drain terminal electrode 9b is increased to 700V gradually from 0V, can depletion region be formed in drift region and this depletion region can along with the increase of the voltage of drain terminal electrode broadening gradually.
When the voltage of the first drain terminal electrode 9a or the second drain terminal electrode 9b is lower, time under the field oxide 3 that depletion region does not have broadening to cover to polysilicon resistance 7, polysilicon resistance 7 is identical with the current potential in the silicon under its field oxide 3, as current potential in the silicon under the field oxide 3 below the first resistance electrode 7a is identical with the first drain terminal electrode 9a, therefore in silicon under field oxide 3 below the first resistance electrode 7a, current potential is also just identical with polysilicon resistance 7 current potential at the first resistance electrode 7a place, so now field oxide 3 does not bear voltage.
When the voltage of the first drain terminal electrode 9a or the second drain terminal electrode 9b is higher, time under the field oxide 3 that depletion region broadening covers to polysilicon resistance 7, because a part of drain terminal electrode institute making alive can be shared in depletion region, so have potential difference between silicon depletion region under the field oxide 3 of polysilicon resistance 7 and drain terminal electrode, wherein drain terminal electrode potential wants large, therefore also have identical potential difference between silicon depletion region under the field oxide 3 of polysilicon resistance 7 and polysilicon resistance 7, this potential difference for polysilicon resistance 7 to drain region 9 lateral separation between the width of silicon depletion region that formed, the Breadth Maximum of this depletion region is also the lateral separation of polysilicon resistance 7 to drain region 9, due to polysilicon resistance 7 arrange relatively near drain region 9, therefore therefore polysilicon resistance 7 can not be very large with the potential difference in the silicon under its field oxide 3 covered, the field oxide 3 of general thickness as 4000 dusts is can be proof.Therefore, as long as institute's making alive is lower than the puncture voltage of this N-type LDMOS on drain region 9 and polysilicon resistance 7, polysilicon resistance 7 of the present invention just can normally work.So in the direction of the width, drain region and polysilicon resistance can be taken as any value between 0V to 700V.
In the embodiment of the present invention, the puncture voltage of LDMOS device can reach more than 700V, and namely the voltage endurance capability of the drift region of LDMOS device is more than 700V, therefore the operating voltage of polysilicon resistance 7 also can reach more than 700V.As shown in Figure 3, be voltage-current curve figure between the polysilicon resistance of the embodiment of the present invention and silicon substrate; Can find out on the longitudinal direction between polysilicon resistance and silicon substrate, only have when the operating voltage on polysilicon resistance is greater than more than 800V, just there will be leakage current, therefore the operating voltage of the polysilicon resistance of the embodiment of the present invention is all right within above-mentioned withstand voltage, so the embodiment of the present invention can realize the polysilicon resistance that operating voltage is more than 700V.
As shown in Fig. 4 A to Fig. 4 D, it is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention polysilicon resistance.The manufacture method of embodiment of the present invention polysilicon resistance comprises the steps:
Step one, as shown in Figure 4 A, silicon substrate 1 forms N-type well region 2, described N-type well region 2 is increased temperature by ion implantation and pushes away trap and formed, and the implanted dopant of the ion implantation of described N-type well region 2 is phosphorus, Implantation Energy is 100keV ~ 300keV, implantation dosage is 10
11cm
-2~ 10
14cm
-2, the temperature that the high temperature of described N-type well region 2 pushes away trap is 1000 DEG C ~ 1200 DEG C, the time is 100 minutes ~ 500 minutes.Drift region is formed by described N-type well region 2.
Step 2, as shown in Figure 4 B, described silicon substrate 1 forms field oxide 3.Described field oxide 3 is thermal oxide layers, and is adopt local oxidation layer (LOCOS) technique to be formed, and the thickness of described field oxide 3 is 4000 dust ~ 8000 dusts.
Step 3, as shown in Figure 4 C, described silicon substrate 1 forms P type trap zone, forms channel region 4 by described P type trap zone; In a lateral direction described drift region and described channel region 4 adjacent; Make the field oxide 3 of drain terminal be the first field oxide 3, described first field oxide 3 is between described drain region 9 and described channel region 4.P type trap zone described in the embodiment of the present invention is formed in described N-type well region 2 by ion implantation, and the implanted dopant of the ion implantation of described P type trap zone is boron, Implantation Energy is 0keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2, inject number of times be one or many inject.
Step 4, as shown in Figure 4 C, forms P type top layer 5 by ion implantation technology, and described P type top layer 5 is arranged in described drift region and near the lower surface of described first field oxide 3.The implanted dopant of the ion implantation of described P type top layer 5 is boron, Implantation Energy is 100keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2.
Described P type top layer 5 is also formed in described drift region outside described first field oxide 3 and described channel region 4 simultaneously, owing to not having the stop of described first field oxide 3, the described drift region of described P type top layer 5 outside described first field oxide 3 and the degree of depth in described channel region 4 are less than the degree of depth of the described P type top layer 5 be positioned at bottom described first field oxide 3.
Step 5, as shown in Figure 4 D, forms gate oxide in described silicon substrate 1 front, depositing polysilicon layer on described gate oxide.
Step 6, as shown in Figure 4 D, carry out chemical wet etching form grid polycrystalline silicon 6 and polysilicon resistance 7 simultaneously to described polysilicon, described polysilicon resistance 7 and described grid polycrystalline silicon 6 are separated by a segment distance.
Described grid polycrystalline silicon 6 is positioned at silicon substrate 1 surface of described channel region 4, the side autoregistration of described source region 8 and described grid polycrystalline silicon 6, the opposite side of described grid polycrystalline silicon 6 extends to above described first field oxide 3, and from described source region 8, to the direction in described drain region 9, described grid polycrystalline silicon 6 covers described channel region 4, described drift region described first field oxide 3 and described channel region 4 and described first field oxide 3 of part successively.
Described polysilicon resistance 7 is positioned on described first field oxide 3, can regulate the resistance value of described polysilicon resistance 7 by carrying out described polysilicon resistance 7 adulterating.
Step 7, as shown in Figure 4 D, the heavily doped region of N-type that the source and drain of carrying out N-type is infused in described channel region 4 and is formed in described drift region, described source region 8 is made up of the heavily doped region of the N-type be formed in described channel region 4; Described drain region 9 is made up of the heavily doped region of the N-type be formed in described drift region;
Described source and drain is injected and is utilized grid polycrystalline silicon 6 and field oxide 3 to do hardmask to inject, and the implanted dopant phosphorus that described source and drain is injected or arsenic, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.Because it is utilize grid polycrystalline silicon 6 and field oxide 3 to do hardmask that described source and drain is injected, thus the side autoregistration of described source region 8 and described grid polycrystalline silicon 6, the side autoregistration of described drain region 9 and described first field oxide 3.
Step 8, as shown in Figure 4 D, the heavy doping ion of carrying out P type is infused in the draw-out area 10 forming channel region in described channel region 4.The implanted dopant boron of the ion implantation of the draw-out area 10 of described channel region, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.
Namely the source electrode, the drain terminal electrode that finally do the described N-type LDMOS device that metal contact hole is drawn drain, grid, channel region extraction electrode and silicon substrate electrode.Source electrode and described source region 8 contact, and described grid and described grid polycrystalline silicon 6 contact, and the draw-out area 10 of described channel region extraction electrode and described channel region contacts, and silicon substrate electrode and described silicon substrate 1 contact.And form the resistance electrode of described polysilicon resistance 7.
As shown in Figure 2, to be length direction vertical with this length direction in direction from the source region 8 of described N-type LDMOS device to drain region 9 and be Width with parallel direction, described silicon substrate 1 surface, in the direction of the width, described resistance electrode comprises the first resistance electrode 7a and the second resistance electrode 7b that are formed at described polysilicon resistance 7 two ends respectively, and described drain terminal electrode comprises the first drain terminal electrode 9a and the second drain terminal electrode 9b that are formed at two ends, described drain region 9.Described first drain terminal electrode 9a and described first resistance electrode 7a is positioned on the line of same length direction, described second drain terminal electrode 9b and described second resistance electrode 7b is positioned on the line of same length direction, can find out, length between described first resistance electrode 7a and described second resistance electrode 7b equals the length between described first drain terminal electrode 9a and described second drain terminal electrode 9b, and the residing in the direction of the width position of described first drain terminal electrode 9a and described second drain terminal electrode 9b is also identical with the position of described second resistance electrode 7b with described first resistance electrode 7a.Described drain region 9 is not connected with described polysilicon resistance 7.In use, described first drain terminal electrode 9a is identical with the voltage added by described first resistance electrode 7a, and described second drain terminal electrode 9b is identical with the voltage added by described second resistance electrode 7b; On described source electrode, described grid, described channel region extraction electrode and described silicon substrate electrode, institute's making alive is zero.
All be described for N-type LDMOS device in the embodiment of the present invention, for P type LDMOS device, only need to do corresponding doped region to convert accordingly, as be N-type by the doping type of channel region, the doping type of drift region is P type, the doping type of source-drain area is N-type, other structure and N-type LDMOS device similar, the embodiment of the present invention is not just described in detail P type LDMOS device.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a polysilicon resistance, is characterized in that: be formed with field oxide on a silicon substrate, and polysilicon resistance is arranged on the field oxide of the drain terminal of LDMOS device, direction from the source region of described LDMOS device to drain region is length direction, vertical with this length direction and the direction parallel with described surface of silicon is Width, in the direction of the width, the two ends of described polysilicon resistance are formed with the first resistance electrode and the second resistance electrode respectively, the two ends in described drain region are formed with the first drain terminal electrode and the second drain terminal electrode respectively, described first drain terminal electrode and described first resistance electrode are positioned on the line of same length direction, described second drain terminal electrode and described second resistance electrode are positioned on the line of same length direction, described drain region is not connected with described polysilicon resistance, in use, described first drain terminal electrode is identical with the voltage added by described first resistance electrode, described second drain terminal electrode is identical with the voltage added by described second resistance electrode, and on the source electrode of described LDMOS device, grid, channel region extraction electrode and silicon substrate electrode, institute's making alive is zero.
2. polysilicon resistance as claimed in claim 1, is characterized in that: described LDMOS device comprises:
Channel region, is made up of the second conduction type well region;
Drift region, is made up of the first conduction type well region, in a lateral direction described drift region and described channel region adjacent;
Described source region is made up of the heavily doped region of the first conduction type be formed in described channel region;
Described drain region is made up of the heavily doped region of the first conduction type be formed in described drift region; Described drain region and described channel region are separated by a segment distance, the field oxide of drain terminal is made to be the first field oxide, described first field oxide is between described drain region and described channel region, the side autoregistration of described drain region and described first field oxide, the opposite side of described first field oxide and described channel region are separated by a segment distance;
The draw-out area of channel region, is made up of the heavily doped region of the second conduction type be formed in described channel region;
Grid polycrystalline silicon, above the surface of silicon being formed at described channel region, the side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to above described first field oxide, and from described source region, to the direction in described drain region, described grid polycrystalline silicon covers described channel region, described drift region described first field oxide and described channel region and described first field oxide of part successively; Between the described channel region of described grid polycrystalline silicon and its covering and described drift region, isolation has gate oxide;
Second conduction type top layer, to be formed in described drift region and near the lower surface of described first field oxide;
Described polysilicon resistance and described grid polycrystalline silicon are formed by same layer etching polysilicon, and described polysilicon resistance and described grid polycrystalline silicon are separated by a segment distance.
3. polysilicon resistance as claimed in claim 2, it is characterized in that: described LDMOS device is N-type LDMOS device, described first conduction type is N-type, described second conduction type is P type, described second conduction type well region is P type trap zone, described first conduction type well region is N-type well region, and described second conduction type top layer is P type top layer;
Or, described LDMOS device is P type LDMOS device, and described first conduction type is P type, and described second conduction type is N-type, described second conduction type well region is N-type well region, described first conduction type well region is P type trap zone, and described second conduction type top layer is N-type top layer.
4. a manufacture method for polysilicon resistance, is characterized in that, comprises the steps:
Form LDMOS device on a silicon substrate;
Polysilicon resistance is formed on the field oxide of the drain terminal of described LDMOS device;
Direction from the source region of described LDMOS device to drain region is length direction with this length direction is vertical and the direction parallel with described surface of silicon is Width; Two ends on the Width of described polysilicon resistance form the first resistance electrode and the second resistance electrode respectively, two ends on the Width in described drain region form the first drain terminal electrode and the second drain terminal electrode respectively, and described first drain terminal electrode and described first resistance electrode are positioned on the line of same length direction, described second drain terminal electrode and described second resistance electrode are positioned on the line of same length direction.
5. method as claimed in claim 4, is characterized in that: the step forming described LDMOS device is:
Step one, on described silicon substrate, form the first conduction type well region, form drift region by described first conduction type well region;
Step 2, form field oxide on a silicon substrate;
Step 3, on described silicon substrate, form the second conduction type well region, form channel region by described second conduction type well region; In a lateral direction described drift region and described channel region adjacent; Make the field oxide of drain terminal be the first field oxide, described first field oxide is between described drain region and described channel region;
Step 4, form the second conduction type top layer by ion implantation technology, described second conduction type top layer is arranged in described drift region and near the lower surface of described first field oxide;
Step 5, form gate oxide in described silicon substrate front, depositing polysilicon layer on described gate oxide;
Step 6, carry out chemical wet etching form grid polycrystalline silicon and described polysilicon resistance simultaneously to described polysilicon, described polysilicon resistance and described grid polycrystalline silicon are separated by a segment distance; Described grid polycrystalline silicon is positioned at above the surface of silicon of described channel region, the side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to above described first field oxide, and from described source region, to the direction in described drain region, described grid polycrystalline silicon covers described channel region, described drift region described first field oxide and described channel region and described first field oxide of part successively;
Step 7, the source and drain of carrying out the first conduction type are infused in the heavily doped region of the first conduction type formed in described channel region and in described drift region, and described source region is made up of the heavily doped region of the first conduction type be formed in described channel region; Described drain region is made up of the heavily doped region of the first conduction type be formed in described drift region; The side autoregistration of described source region and described grid polycrystalline silicon, the side autoregistration of described drain region and described first field oxide;
Step 8, the heavy doping ion of carrying out the second conduction type are infused in the draw-out area forming channel region in described channel region.
6. method as claimed in claim 5, it is characterized in that: described LDMOS device is N-type LDMOS device, described first conduction type is N-type, described second conduction type is P type, described second conduction type well region is P type trap zone, described first conduction type well region is N-type well region, and described second conduction type top layer is P type top layer.
7. method as claimed in claim 6, is characterized in that: in step one, N-type well region is increased temperature by ion implantation and pushes away trap and formed, and the implanted dopant of the ion implantation of described N-type well region is phosphorus, Implantation Energy is 100keV ~ 300keV, implantation dosage is 10
11cm
-2~ 10
14cm
-2, the temperature that the high temperature of described N-type well region pushes away trap is 1000 DEG C ~ 1200 DEG C, the time is 100 minutes ~ 500 minutes;
P type trap zone in step 3 is formed in described N-type well region by ion implantation, and the implanted dopant of the ion implantation of described P type trap zone is boron, Implantation Energy is 0keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2, inject number of times be one or many inject.
8. method as claimed in claim 6, is characterized in that: the implanted dopant of the ion implantation of the P type top layer in step 4 is boron, Implantation Energy is 100keV ~ 2000keV, implantation dosage is 10
11cm
-2~ 10
15cm
-2.
9. method as claimed in claim 6, is characterized in that: the implanted dopant phosphorus that the described source and drain of step 7 is injected or arsenic, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject;
The implanted dopant boron of the ion implantation of the draw-out area of described channel region, Implantation Energy are 0keV ~ 200keV, implantation dosage is 10
13cm
-2~ 10
16cm
-2, inject number of times be single or multiple inject.
10. method as claimed in claim 5, it is characterized in that: described LDMOS device is P type LDMOS device, described first conduction type is P type, described second conduction type is N-type, described second conduction type well region is N-type well region, described first conduction type well region is P type trap zone, and described second conduction type top layer is N-type top layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210297949.3A CN103633089B (en) | 2012-08-20 | 2012-08-20 | Polysilicon resistance and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210297949.3A CN103633089B (en) | 2012-08-20 | 2012-08-20 | Polysilicon resistance and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103633089A CN103633089A (en) | 2014-03-12 |
| CN103633089B true CN103633089B (en) | 2015-12-02 |
Family
ID=50213944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210297949.3A Active CN103633089B (en) | 2012-08-20 | 2012-08-20 | Polysilicon resistance and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103633089B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617149B (en) * | 2015-01-30 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Isolated form NLDMOS device and its manufacturing method |
| CN106206320B (en) * | 2016-08-16 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of LDMOS |
| CN108987572B (en) * | 2018-08-01 | 2024-05-17 | 深圳元顺微电子技术有限公司 | Semiconductor structure for forming resistor and forming method of resistor |
| CN109616511B (en) * | 2018-12-18 | 2021-11-26 | 深圳市威兆半导体有限公司 | Design method of VDMOS voltage division ring with multiple longitudinal PN junctions |
| CN110729402B (en) * | 2019-10-21 | 2023-03-07 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of polysilicon resistor |
| CN112151620B (en) * | 2020-10-27 | 2022-07-19 | 杰华特微电子股份有限公司 | Junction field effect transistor with ESD protection structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN102054785A (en) * | 2010-11-04 | 2011-05-11 | 电子科技大学 | Manufacturing method of high-voltage BCD semiconductor device |
| CN102623509A (en) * | 2012-04-19 | 2012-08-01 | 成都芯源系统有限公司 | High-voltage switch device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5005241B2 (en) * | 2006-03-23 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8207577B2 (en) * | 2009-09-29 | 2012-06-26 | Power Integrations, Inc. | High-voltage transistor structure with reduced gate capacitance |
-
2012
- 2012-08-20 CN CN201210297949.3A patent/CN103633089B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN102054785A (en) * | 2010-11-04 | 2011-05-11 | 电子科技大学 | Manufacturing method of high-voltage BCD semiconductor device |
| CN102623509A (en) * | 2012-04-19 | 2012-08-01 | 成都芯源系统有限公司 | High-voltage switch device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103633089A (en) | 2014-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103633089B (en) | Polysilicon resistance and manufacture method thereof | |
| CN103035721B (en) | Super junction device and manufacturing method thereof | |
| CN103035720B (en) | Super junction device and manufacturing method thereof | |
| CN104992977A (en) | Nldmos device and manufacturing method thereof | |
| CN105789311A (en) | Transverse diffusion field effect transistor and manufacturing method therefor | |
| CN106024894A (en) | Groove gate power MOSFET structure and manufacturing method thereof | |
| CN104659090B (en) | LDMOS device and manufacture method | |
| CN105428415A (en) | NLDMOS device and manufacturing method therefor | |
| CN102136494A (en) | High-voltage isolating LDNMOS (Lateral Diffusion N-channel Metal Oxide Semiconductor) and manufacture method thereof | |
| CN102136493A (en) | High-voltage insulation type LDNMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| CN105679820A (en) | Jfet and manufacturing method thereof | |
| CN105513971A (en) | Manufacturing method of trench gate power device with shield gate | |
| CN103545346B (en) | Isolated form N-type LDMOS device and manufacture method thereof | |
| CN104658913A (en) | Manufacturing method for NLDMOS | |
| CN106972047B (en) | LDMOS devices | |
| CN113659009A (en) | Power semiconductor device with internal anisotropic doping and manufacturing method thereof | |
| CN105140289A (en) | N-type LDMOS device and technical method thereof | |
| CN105514166A (en) | NLDMOS device and manufacture method thereof | |
| CN105206675A (en) | Nldmos device and manufacturing method thereof | |
| CN103035525A (en) | Manufacturing method of high voltage isolating N type laterally diffused metal oxide semiconductor (LDMOS) component | |
| CN105679831B (en) | Horizontal proliferation field-effect transistor and its manufacturing method | |
| CN101777584B (en) | P-channel laterally double diffused metal oxide semiconductor device | |
| CN103426760B (en) | The manufacturing process of P-type LDMOS surface channel component | |
| CN102694020B (en) | Semiconductor device | |
| CN108269841B (en) | Lateral diffusion metal oxide semiconductor field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |