CN105679820A - Jfet and manufacturing method thereof - Google Patents

Jfet and manufacturing method thereof Download PDF

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Publication number
CN105679820A
CN105679820A CN201610148098.4A CN201610148098A CN105679820A CN 105679820 A CN105679820 A CN 105679820A CN 201610148098 A CN201610148098 A CN 201610148098A CN 105679820 A CN105679820 A CN 105679820A
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jfet
ldmos
region
channel region
conduction type
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CN105679820B (en
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a JFET. The JFET is integrated into an LDMOS; a gate region of the JFET comprises a channel region of the LDMOS and a well region formed outside the first side of the channel region of the LDMOS; a buried layer formed in a drift region of the JFET and the gate region of the JFET are in a surrounding structure; a source region of the JFET is formed on the surface of the surrounding structure; a buried layer gap is formed in the bottom part of the surrounding structure; the channel region of the JFET is formed in the buried layer gap; and opening and closing of a channel in the channel region of the JFET are achieved by lateral depletion on the channel region through the buried layer. The invention further discloses a manufacturing method of the JFET. The JFET can achieve lateral pinch-off of the channel, so that the influence on the performance of the JFET caused by the doping concentration of a substrate can be eliminated; and accurate control on a pinch-off voltage and improvement of the device stability can also be achieved.

Description

JFET and manufacture method thereof
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of junction field effect transistor (JFET). The invention still further relates to the manufacture method of a kind of JFET.
Background technology
JFET adopts PN junction opening and ending as the gate control raceway groove of device, and when adding PN junction back bias voltage on grid, PN junction both sides exhaust, and when raceway groove is completely depleted, device is in raceway groove pinch off state, and device ends. Otherwise, break-over of device.
Supertension junction field effect transistor needs drain terminal can bear high pressure, the drift region of high pressure horizontal proliferation field-effect transistor (LDMOS) is generally utilized to bear high pressure as the drift region of JFET, the raceway groove of high-voltage LDMOS is as the grid of JFET, so can produce supertension JFET, reticle can be shared with high-voltage LDMOS again, save process costs.
JFET when raceway groove pinch off (for N-type JFET), it is necessary to add positive voltage at source electrode or add negative voltage at grid so that N-type channel region all exhausts, to stop the unlatching between source and drain, making raceway groove pinch off. There are two parts in the territory, p type island region exhausting N-type channel: one is P-type grid electrode part, and one is P type substrate part. The contribution that wherein P type substrate participates in exhausting accounts for leading, and therefore the doping content of P type substrate can significantly change pinch-off voltage and the On current of JFET.
Supertension JFET adopts super High resistivity substrate, and doping content is very low so that the change in resistance of substrate is very big, thus causing the unstable properties of JFET.
Summary of the invention
The technical problem to be solved is to provide a kind of JFET, can realize the horizontal pinch off on raceway groove it is thus possible to eliminate the substrate doping impact on JFET performance, moreover it is possible to realize the stability accurately controlling and improving device of pinch-off voltage. For this, the present invention also provides for the manufacture method of a kind of JFET.
For solving above-mentioned technical problem, JFET provided by the invention is integrated in LDMOS, the drift region of described JFET and the drift region of described LDMOS share and are the first conduction type doping, and the drain region of described JFET and the drain region of described LDMOS share and be the first conduction type doping.
The channel region of described LDMOS is made up of the second conduction type well region.
Second side of the channel region of described LDMOS is the side near described drain region, and the first side of the channel region of described LDMOS is located remotely from the side in the drain region of described LDMOS;The drift region of described JFET along the second side of the channel region of described LDMOS to the direction of the first side on extend to from described drain region end outside first side of channel region of described LDMOS.
The second conduction type well region that the gate regions of described JFET is added in the drift region of the described JFET outside the first side of the channel region being formed at described LDMOS by the channel region of described LDMOS forms.
The drift region of described JFET is formed the buried regions of the second conduction type doping.
Second side of the channel region at described LDMOS of described buried regions is used for reducing the surface field of the drift region of described LDMOS to the part between described drain region, improves the breakdown voltage of described LDMOS and reduces conducting resistance.
Described buried regions also includes the part outside the first side extending to the channel region of described LDMOS, and outside the first side of the channel region of described LDMOS, the gate regions of described buried regions and described JFET is enclosed structure.
The surface, drift region of the described JFET in described enclosed structure is formed with the source region of the described JFET being made up of the first conduction type heavily doped region.
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions, described channel region carried out having lateral depletion realization.
Further improving and be, regulate the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
Further improve and be, the described buried regions at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
Further improving and be, described buried regions adds ion implanting by photoetching and realizes, and described buried regions breach is defined by photoetching process.
Further improving is that described drift region is made up of deep trap.
Further improving is that described drift region is made up of epitaxial layer.
Further improving is be sequentially formed with gate dielectric layer and polysilicon gate on the channel region surface of described LDMOS, and the described channel region surface covered by described polysilicon gate is for forming the raceway groove of described LDMOS.
The source region of described LDMOS is formed from channel region surface the first conduction type heavily doped region composition of described LDMOS, the source region of described LDMOS and the first side autoregistration of described polysilicon gate.
The drain region of described LDMOS is made up of the first conduction type heavily doped region, and the drain region of described LDMOS is positioned at outside the second side of described polysilicon gate.
The grid draw-out area being made up of the second conduction type heavily doped region it is formed with on the surface, gate regions of described JFET.
The drain region of described LDMOS is connected to the described LDMOS formed by front metal layer and the described JFET drain electrode shared by contact hole.
The source region of described LDMOS is connected to the source electrode of the described LDMOS formed by front metal layer by contact hole.
The grid draw-out area of described JFET is connected to the source electrode of described LDMOS also by contact hole, and the source electrode of described LDMOS is as the grid of described JFET.
The source region of described JFET is connected to the source electrode of the described JFET formed by front metal layer by contact hole.
Described polysilicon gate is connected to the grid of the described LDMOS formed by front metal layer by contact hole.
Further improving is that described JFET also includes:
Field oxide, above the described drift region between the channel region and described drain region of described LDMOS, the second side of described field oxide and described drain region lateral contact, the first side of described field oxide and the channel region of described LDMOS are at a distance;Described polysilicon gate extends to above described field oxide.
Further improving is that described field oxide is local oxidation layer or shallow trench field oxide.
Further improving is be formed with polysilicon field plate on the surface of the side, drain region of the close described LDMOS of described field oxide, and described polysilicon field plate is connected to the drain electrode formed by front metal layer by contact hole.
Further improving is that described LDMOS and described JFET is N-type device, and the first conduction type is N-type, and the second conduction type is P type.
Further improving is that described LDMOS and described JFET is P-type device, and the first conduction type is P type, and the second conduction type is N-type.
For solving above-mentioned technical problem, the JFET of the manufacture method of JFET provided by the invention is integrated in LDMOS, comprises the steps:
Step one, formed in the second conductive type semiconductor substrate described JFET and described LDMOS share first conduction type doping drift region.
Step 2, employing photoetching add ion implantation technology and form the second conduction type well region.
The channel region of described LDMOS is made up of the second conduction type well region.
Second side of the channel region of described LDMOS is the side near described drain region, and the first side of the channel region of described LDMOS is located remotely from the side in the drain region of described LDMOS; The drift region of described JFET along the second side of the channel region of described LDMOS to the direction of the first side on extend to from described drain region end outside first side of channel region of described LDMOS.
The second conduction type well region that the gate regions of described JFET is added in the drift region of the described JFET outside the first side of the channel region being formed at described LDMOS by the channel region of described LDMOS forms.
Step 3, employing photoetching add ion implantation technology and form the buried regions of the second conduction type doping in the drift region of described JFET.
Second side of the channel region at described LDMOS of described buried regions is used for reducing the surface field of the drift region of described LDMOS to the part between described drain region, improves the breakdown voltage of described LDMOS and reduces conducting resistance.
Described buried regions also includes the part outside the first side extending to the channel region of described LDMOS, and outside the first side of the channel region of described LDMOS, the gate regions of described buried regions and described JFET is enclosed structure.
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions, described channel region carried out having lateral depletion realization.
Step 4, carry out the first conduction type heavily-doped implant and form source region and the drain region of described JFET.
The first conduction type doped region composition on the surface, drift region of the described JFET that the source region of described JFET is formed from described enclosed structure; Described JFET and described LDMOS shares drain region.
Further improving and be, regulate the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
Further improve and be, the described buried regions at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
Further improving and be, drift region described in step one adopts deep trap technique to be formed.
Further improving and be, drift region described in step one adopts epitaxial growth technology to be formed.
Further improving is after step 3 completes, further comprise the steps of: before step 4
Form field oxide, described field oxide is above the described drift region between the channel region and described drain region of described LDMOS, second side of described field oxide and described drain region lateral contact, the first side of described field oxide and the channel region of described LDMOS are at a distance.
Form gate dielectric layer and polysilicon gate, described polysilicon gate extends to above the drift region of described LDMOS from the channel region surface of described LDMOS to direction, described drain region in the horizontal, the channel region surface of the described LDMOS covered by described polysilicon gate is for forming raceway groove, and the first side of described polysilicon gate is positioned at above described channel region, the second side is positioned at above the described field oxide at top, drift region of described LDMOS.
First conduction type heavily-doped implant of step 4 concurrently forms the source region of described LDMOS, and the source region of described LDMOS is formed at the first side autoregistration of the channel region surface of described LDMOS and the source region of described LDMOS and described polysilicon gate; The drain region of described LDMOS is positioned at outside the second side of described polysilicon gate.
Also include after step 4:
Step 5, carry out the second conduction type heavily-doped implant the surface, gate regions of described JFET formed grid draw-out area.
Further improving and be, described field oxide adopts local oxidation technique to make or adopts shallow trench field oxidation technology to make.
Further improving is further comprise the steps of: after step 5
Form interlayer film;
Form the contact hole through described interlayer film;
Form front metal layer, described front metal layer metal lithographic etching is formed the source electrode of drain electrode, the grid of the source electrode of described LDMOS, described LDMOS and described JFET; The drain region of described LDMOS is connected to described LDMOS and the described JFET drain electrode shared by contact hole; The source region of described LDMOS is connected to the source electrode of described LDMOS by contact hole; The grid draw-out area of described JFET is connected to the source electrode of described LDMOS also by contact hole, and the source electrode of described LDMOS is as the grid of described JFET; The source region of described JFET is connected to the source electrode of described JFET by contact hole, and described polysilicon gate is connected to the grid of described LDMOS by contact hole.
Further improving is that the second side of described polysilicon gate extends to described field oxide surface.
Further improving is form polysilicon field plate on the surface of the side, drain region of the close described LDMOS of described field oxide while forming described polysilicon gate, and described polysilicon field plate is connected to the drain electrode formed by front metal layer by contact hole.
Gate regions and the buried regions encirclement formed in drift region of the JFET that the present invention is formed by well region by the source-end region of JFET are formed, the source region of JFET is formed at the surface of enclosed structure, the channel region of JFET is then realized by the buried regions breach of the bottom of enclosed structure, the raceway groove of the channel region of JFET opens and closes, by buried regions, channel region is carried out having lateral depletion realization, so the present invention can realize the horizontal pinch off to raceway groove; Owing to this horizontal pinch off and substrate are unrelated, so the substrate doping impact on JFET performance can be eliminated.
The transverse width of the channel region of the JFET of the present invention is realized by buried regions breach completely, buried regions breach can be controlled by photoetching process, and the pinch-off voltage of energy JFET is regulated by regulating the lateral dimension of buried regions breach, the lateral dimension of buried regions breach is more big, the pinch-off voltage of JFET is more big, so the present invention can realize the stability accurately controlling and improving device of pinch-off voltage.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing JFET;
Fig. 2 is the channel region of the existing JFET shown in Fig. 1 analogous diagram when exhausting;
Fig. 3 is the structural representation of embodiment of the present invention JFET.
Detailed description of the invention
As it is shown in figure 1, be the structural representation of existing JFET; JFET is integrated in LDMOS, for N-type device, is formed with N-type deep trap 102 in P-type semiconductor substrate such as P-type silicon substrate 101, is formed with field oxide 103 on P-type silicon substrate 101 surface being formed with N-type deep trap 102. P type trap zone 104 is formed in N-type deep trap 102, the gate regions of the P type trap zone 104 channel region simultaneously as LDMOS and JFET; It is formed with PTOP layer 105 on the surface of the N-type deep trap 102 of the bottom of field oxide 103. The N+ impure drain region 108 that JFET and LDMOS shares is formed at the surface of N-type deep trap 102, the drift region that JFET and LDMOS shares is made up of the N-type deep trap 102 between drain region 108 and P type trap zone 104, and wherein PTOP layer 105 is for reducing the surface field of the drift region of LDMOS. N-type deep trap 102 immediately below P type trap zone 104 forms the channel region of JFET, as shown in broken box 106.
The source region 111 of JFET is formed from the N+ district composition on the surface of N-type deep trap 102; Gate dielectric layer such as gate oxide and polysilicon gate 107 are formed at the surface of P type trap zone 104 and extend on the surface of field oxide 103. The source region 109 of LDMOS is formed from the N+ district composition on P type trap zone 104 surface, and raceway groove draw-out area 110 is formed from the P+ district composition on P type trap zone 104 surface; P-type silicon substrate 101 surface outside N-type deep trap 102 is formed with the substrate draw-out area 112 being made up of P+ district.
Interlayer film covers the front of device, realizes bottom doped region and the connection of front metal layer 114 at contact hole 113 through interlayer film, forms electrode structure after front metal layer 114 is graphical. Wherein, JFET and the LDMOS drain electrode shared is drawn by contact hole 113 in drain region 108, and meanwhile, the polysilicon field plate 107a being formed at field oxide 103 surface is connected to drain electrode also by contact hole 113; Polysilicon gate 107 is connected to the grid of LDMOS by contact hole 113; Source region 109 and the raceway groove draw-out area 110 of LDMOS are connected to the source electrode of LDMOS respectively through contact hole 113, and the source electrode of LDMOS is simultaneously as the grid of JFET; The source region 111 of JFET is connected to the source electrode of JFET by contact hole 113; Substrate draw-out area 112 is connected to underlayer electrode by contact hole 113.
As in figure 2 it is shown, be the channel region of the existing JFET shown in Fig. 1 analogous diagram when exhausting; Labelling 301 is corresponding to the interface between P-type semiconductor substrate 101 and N-type deep trap 102, broken box 302 is corresponding to the channel region depleted region of JFET, broken box 303 represents the depleted region that the channel region of P-type semiconductor substrate 101 whole JFET when the channel region of JFET is exhausted and the P-type semiconductor substrate 101 of bottom are formed, as shown in Figure 3, depleted region corresponding to broken box 302 and 303 is easily subject to the impact of P-type semiconductor substrate 101, the fluctuation meeting of the doping content of P-type semiconductor substrate 101 fluctuation exhausting generation to the channel region to JFET.
As shown in Figure 3, it it is the structural representation of embodiment of the present invention JFET, the embodiment of the present invention illustrates for N-type JFET, LDMOS is also N-type LDMOS, N-type is N-type, and P type is P type, and embodiment of the present invention JFET is integrated in LDMOS, the drift region 2 of the drift region 2 of described JFET and described LDMOS shares and be n-type doping, the drain region 8 of described JFET and the drain region 8 of described LDMOS is shared and be n-type doping.
In the embodiment of the present invention, described drift region 2 is formed from P-type semiconductor substrate such as silicon substrate 1 deep trap composition;In other embodiments, described drift region 2 also can for be made up of epitaxial layer.
The channel region 4a of described LDMOS is made up of P type trap zone.
Second side of the channel region 4a of described LDMOS is the side near described drain region 8, and first side of the channel region 4a of described LDMOS is located remotely from the side in the drain region 8 of described LDMOS; The drift region 2 of described JFET along second side of the channel region 4a of described LDMOS to the direction of the first side on extend to outside first side of channel region 4a of described LDMOS from described drain region 8 end.
The P type trap zone 4b that the gate regions of described JFET is added in the drift region 2 of the described JFET outside first side of the channel region 4a being formed at described LDMOS by the channel region 4a of described LDMOS forms, and namely the gate regions of JFET is made up of P type trap zone 4a and 4b.
The drift region 2 of described JFET is formed the buried regions 5 of P type doping.
Second side of the channel region 4a at described LDMOS of described buried regions 5 is used for reducing the surface field of the drift region 2 of described LDMOS to the part between described drain region 8, improves the breakdown voltage of described LDMOS and reduces conducting resistance.
Described buried regions 5 also includes the part outside the first side extending to the channel region 4a of described LDMOS, and outside first side of the channel region 4a of described LDMOS, gate regions 4a and the 4b of described buried regions 5 and described JFET is enclosed structure.
The surface, drift region 2 of the described JFET in described enclosed structure is formed with the source region 9 of the described JFET being made up of N-type heavily doped region.
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions 5, described channel region carried out having lateral depletion realization. The position of the channel region of described buried regions breach and described JFET is such as shown in broken box 201.
Regulate the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
The described buried regions 5 at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
Described buried regions 5 adds ion implanting by photoetching and realizes, and described buried regions breach is defined by photoetching process.
Embodiment of the present invention JFET also includes:
Being sequentially formed with gate dielectric layer such as gate dielectric layer and polysilicon gate 6 on the channel region 4a surface of described LDMOS, the described channel region surface covered by described polysilicon gate 6 is for forming the raceway groove of described LDMOS.
The source region 7 of described LDMOS is formed from the channel region 4a surface N-type heavily doped region composition of described LDMOS, the source region 7 of described LDMOS and the first side autoregistration of described polysilicon gate 6.
The drain region 8 of described LDMOS is made up of N-type heavily doped region, and the drain region 8 of described LDMOS is positioned at outside the second side of described polysilicon gate 6.
Grid draw-out area 10a and the 10b being made up of P type heavily doped region it is formed with on the surface, gate regions of described JFET, wherein grid draw-out area 10a is for being formed at part in described gate regions 4a, and grid draw-out area 10b is for being formed at part in described gate regions 4b, grid draw-out area 10a and 10b adopts same process to be formed.
The drain region 8 of described LDMOS is connected to the described LDMOS formed by the front metal layer 12 and described JFET drain electrode shared by contact hole 11.
The source region 7 of described LDMOS is connected to the source electrode of the described LDMOS formed by front metal layer 12 by contact hole 11.
Grid draw-out area 10a and the 10b of described JFET is connected to the source electrode of described LDMOS also by contact hole 11, and the source electrode of described LDMOS is as the grid of described JFET.
The source region 9 of described JFET is connected to the source electrode of the described JFET formed by front metal layer 12 by contact hole 11.
Described polysilicon gate 6 is connected to the grid of the described LDMOS formed by front metal layer 12 by contact hole 11.
Field oxide 3, above the described drift region 2 between the channel region 4a and described drain region 8 of described LDMOS, second side of described field oxide 3 and described drain region 8 lateral contact, the first side of described field oxide 3 and the channel region 4a of described LDMOS are at a distance; Described polysilicon gate 6 extends to above described field oxide 3. Described field oxide 3 is local oxidation layer or shallow trench field oxide.
It is formed with polysilicon field plate 6a, described polysilicon field plate 6a on the surface of the side, drain region 8 of the close described LDMOS of described field oxide 3 and is connected to, by contact hole 11, the drain electrode formed by front metal layer 12.
Known as shown in Figure 3, the embodiment of the present invention is surrounded formed by the gate regions of JFET formed by well region 4a and 4b in the source-end region of JFET and the buried regions 5 formed in drift region, the source region 9 of JFET is formed at the surface of enclosed structure, the channel region of JFET is then realized as shown in broken box 201 by the buried regions breach of the bottom of enclosed structure, the raceway groove of the channel region of JFET opens and closes, by buried regions 5, channel region is carried out having lateral depletion realization, so the embodiment of the present invention can realize the horizontal pinch off to raceway groove; Owing to this horizontal pinch off and substrate are unrelated, so the substrate doping impact on JFET performance can be eliminated.
The transverse width of the channel region of the JFET of the embodiment of the present invention is realized by buried regions breach completely, buried regions breach can be controlled by photoetching process, and the pinch-off voltage of energy JFET is regulated by regulating the lateral dimension of buried regions breach, the lateral dimension of buried regions breach is more big, the pinch-off voltage of JFET is more big, so the embodiment of the present invention can realize the stability accurately controlling and improving device of pinch-off voltage.
Illustrating for N-type device in the embodiment of the present invention, the first conduction type is changed to P type, the second conduction type is changed to N-type and just obtains the embodiment method corresponding to P type JFET, herein P-type device is no longer described in detail.
As it is shown on figure 3, embodiment of the present invention method illustrates for N-type JFET, LDMOS is also N-type LDMOS, and N-type is N-type, and P type is P type, and the JFET of the manufacture method of embodiment of the present invention JFET is integrated in LDMOS, comprises the steps:
Step one, in P-type semiconductor substrate such as silicon substrate 1, form the drift region 2 of described JFET and the described LDMOS n-type doping shared.
In the embodiment of the present invention, described drift region 2 adopts deep trap technique to be formed. Also can be in other embodiments: described drift region 2 adopts epitaxial growth technology to be formed.
Step 2, employing photoetching add ion implantation technology and form P type trap zone 4a and 4b.
The channel region 4a of described LDMOS is made up of P type trap zone.
Second side of the channel region 4a of described LDMOS is the side near described drain region 8, and first side of the channel region 4a of described LDMOS is located remotely from the side in the drain region 8 of described LDMOS; The drift region 2 of described JFET along second side of the channel region 4a of described LDMOS to the direction of the first side on extend to outside first side of channel region 4a of described LDMOS from described drain region 8 end.
The P type trap zone 4b that the gate regions of described JFET is added in the drift region 2 of the described JFET outside first side of the channel region 4a being formed at described LDMOS by the channel region 4a of described LDMOS forms.
Step 3, employing photoetching add ion implantation technology and form the buried regions 5 of P type doping in the drift region 2 of described JFET.
Second side of the channel region 4a at described LDMOS of described buried regions 5 is used for reducing the surface field of the drift region 2 of described LDMOS to the part between described drain region 8, improves the breakdown voltage of described LDMOS and reduces conducting resistance.
Described buried regions 5 also includes the part outside the first side extending to the channel region 4a of described LDMOS, and outside first side of the channel region 4a of described LDMOS, the gate regions of described buried regions 5 and described JFET is enclosed structure.
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions 5, described channel region carried out having lateral depletion realization.
In the embodiment of the present invention, regulating the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
The described buried regions 5 at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
Comprise the steps: afterwards
Forming field oxide 3, described field oxide 3 is above the described drift region 2 between the channel region 4a and drain region 8 of described LDMOS, and the first side of described field oxide 3 and the channel region 4a of described LDMOS are at a distance. Described field oxide 3 adopts local oxidation technique to make or adopts shallow trench field oxidation technology to make.
Form gate dielectric layer such as gate oxide and polysilicon gate 6, described polysilicon gate 6 extends to above the drift region 2 of described LDMOS from the channel region 4a surface of described LDMOS to direction, described drain region 8 in the horizontal, the channel region 4a surface of the described LDMOS covered by described polysilicon gate 6 is for forming raceway groove, and the first side of described polysilicon gate 6 is positioned at above described channel region, the second side is positioned at above the described field oxide 3 at top, drift region 2 of described LDMOS.
Second side of described polysilicon gate 6 extends to described field oxide 3 surface. Polysilicon field plate 6a is formed on the surface of the side, drain region 8 of the close described LDMOS of described field oxide 3 while forming described polysilicon gate 6.
Step 4, the N-type heavily-doped implant that carries out form the source region 7 of the source region 9 of described JFET, drain region 8 and described LDMOS.
The source region 7 of described LDMOS is formed at the first side autoregistration of the channel region 4a surface of described LDMOS and the source region 7 of described LDMOS and described polysilicon gate 6.
The drain region 8 of described LDMOS is positioned at the second side and the shared drain region 8 of described drain region 8 lateral contact, described JFET and described LDMOS of the outside and described field oxide 3 in the second side of described polysilicon gate 6.
The n-type doping district composition on the surface, drift region 2 of the described JFET that the source region 9 of described JFET is formed from described enclosed structure.
Step 5, carry out P type heavily-doped implant the surface, gate regions of described JFET formed grid draw-out area 10a and 10b.
Form interlayer film.
Form the contact hole 11 through described interlayer film.
Form front metal layer 12, described front metal layer 12 metal lithographic etching is formed the source electrode of drain electrode, the grid of the source electrode of described LDMOS, described LDMOS and described JFET;The drain region 8 of described LDMOS is connected to described LDMOS and the described JFET drain electrode shared by contact hole 11; The source region 7 of described LDMOS is connected to the source electrode of described LDMOS by contact hole 11; Grid draw-out area 10a and the 10b of described JFET is connected to the source electrode of described LDMOS also by contact hole 11, and the source electrode of described LDMOS is as the grid of described JFET; The source region 9 of described JFET is connected to the source electrode of described JFET by contact hole 11, and described polysilicon gate 6 is connected to the grid of described LDMOS by contact hole 11. Described polysilicon field plate 6a is connected to, by contact hole 11, the drain electrode formed by front metal layer 12.
Illustrating for N-type device in embodiment of the present invention method, the first conduction type is changed to P type, the second conduction type is changed to N-type and just obtains the embodiment method corresponding to P type JFET, herein the manufacture method of P-type device is no longer described in detail.
Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention. Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improvement, and these also should be regarded as protection scope of the present invention.

Claims (24)

1. a JFET, it is characterised in that: JFET is integrated in LDMOS, and the drift region of described JFET and the drift region of described LDMOS share and be the first conduction type doping, and the drain region of described JFET and the drain region of described LDMOS share and be the first conduction type doping;
The channel region of described LDMOS is made up of the second conduction type well region;
Second side of the channel region of described LDMOS is the side near described drain region, and the first side of the channel region of described LDMOS is located remotely from the side in the drain region of described LDMOS; The drift region of described JFET along the second side of the channel region of described LDMOS to the direction of the first side on extend to outside first side of channel region of described LDMOS from described drain region end;
The second conduction type well region that the gate regions of described JFET is added in the drift region of the described JFET outside the first side of the channel region being formed at described LDMOS by the channel region of described LDMOS forms;
The drift region of described JFET is formed the buried regions of the second conduction type doping;
Second side of the channel region at described LDMOS of described buried regions is used for reducing the surface field of the drift region of described LDMOS to the part between described drain region, improves the breakdown voltage of described LDMOS and reduces conducting resistance;
Described buried regions also includes the part outside the first side extending to the channel region of described LDMOS, and outside the first side of the channel region of described LDMOS, the gate regions of described buried regions and described JFET is enclosed structure;
The surface, drift region of the described JFET in described enclosed structure is formed with the source region of the described JFET being made up of the first conduction type heavily doped region;
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions, described channel region carried out having lateral depletion realization.
2. JFET as claimed in claim 1, it is characterised in that: regulate the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
3. JFET as claimed in claim 1, it is characterised in that: the described buried regions at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
4. JFET as claimed in claim 1, it is characterised in that: described buried regions adds ion implanting by photoetching and realizes, and described buried regions breach is defined by photoetching process.
5. JFET as claimed in claim 1, it is characterised in that: described drift region is made up of deep trap.
6. JFET as claimed in claim 1, it is characterised in that: described drift region is made up of epitaxial layer.
7. JFET as claimed in claim 1, it is characterised in that: being sequentially formed with gate dielectric layer and polysilicon gate on the channel region surface of described LDMOS, the described channel region surface covered by described polysilicon gate is for forming the raceway groove of described LDMOS;
The source region of described LDMOS is formed from channel region surface the first conduction type heavily doped region composition of described LDMOS, the source region of described LDMOS and the first side autoregistration of described polysilicon gate;
The drain region of described LDMOS is made up of the first conduction type heavily doped region, and the drain region of described LDMOS is positioned at outside the second side of described polysilicon gate;
The grid draw-out area being made up of the second conduction type heavily doped region it is formed with on the surface, gate regions of described JFET;
The drain region of described LDMOS is connected to the described LDMOS formed by front metal layer and the described JFET drain electrode shared by contact hole;
The source region of described LDMOS is connected to the source electrode of the described LDMOS formed by front metal layer by contact hole;
The grid draw-out area of described JFET is connected to the source electrode of described LDMOS also by contact hole, and the source electrode of described LDMOS is as the grid of described JFET;
The source region of described JFET is connected to the source electrode of the described JFET formed by front metal layer by contact hole;
Described polysilicon gate is connected to the grid of the described LDMOS formed by front metal layer by contact hole.
8. JFET as claimed in claim 7, it is characterised in that: described JFET also includes:
Field oxide, above the described drift region between the channel region and described drain region of described LDMOS, the second side of described field oxide and described drain region lateral contact, the first side of described field oxide and the channel region of described LDMOS are at a distance; Described polysilicon gate extends to above described field oxide.
9. JFET as claimed in claim 8, it is characterised in that: described field oxide is local oxidation layer or shallow trench field oxide.
10. JFET as claimed in claim 8, it is characterised in that: being formed with polysilicon field plate on the surface of the side, drain region of the close described LDMOS of described field oxide, described polysilicon field plate is connected to the drain electrode formed by front metal layer by contact hole.
11. the JFET as described in any claim in claim 1 to 10, it is characterised in that: described LDMOS and described JFET is N-type device, and the first conduction type is N-type, and the second conduction type is P type.
12. the JFET as described in any claim in claim 1 to 10, it is characterised in that: described LDMOS and described JFET is P-type device, and the first conduction type is P type, and the second conduction type is N-type.
13. the manufacture method of a JFET, it is characterised in that JFET is integrated in LDMOS, comprises the steps:
Step one, formed in the second conductive type semiconductor substrate described JFET and described LDMOS share first conduction type doping drift region;
Step 2, employing photoetching add ion implantation technology and form the second conduction type well region;
The channel region of described LDMOS is made up of the second conduction type well region;
Second side of the channel region of described LDMOS is the side near described drain region, and the first side of the channel region of described LDMOS is located remotely from the side in the drain region of described LDMOS; The drift region of described JFET along the second side of the channel region of described LDMOS to the direction of the first side on extend to outside first side of channel region of described LDMOS from described drain region end;
The second conduction type well region that the gate regions of described JFET is added in the drift region of the described JFET outside the first side of the channel region being formed at described LDMOS by the channel region of described LDMOS forms;
Step 3, employing photoetching add ion implantation technology and form the buried regions of the second conduction type doping in the drift region of described JFET;
Second side of the channel region at described LDMOS of described buried regions is used for reducing the surface field of the drift region of described LDMOS to the part between described drain region, improves the breakdown voltage of described LDMOS and reduces conducting resistance;
Described buried regions also includes the part outside the first side extending to the channel region of described LDMOS, and outside the first side of the channel region of described LDMOS, the gate regions of described buried regions and described JFET is enclosed structure;
The bottom of described enclosed structure has buried regions breach, forms the channel region of described JFET in described buried regions indentation, there, and the raceway groove of the channel region of described JFET opens and closes, by described buried regions, described channel region carried out having lateral depletion realization;
Step 4, carry out the first conduction type heavily-doped implant and form source region and the drain region of described JFET;
The first conduction type doped region composition on the surface, drift region of the described JFET that the source region of described JFET is formed from described enclosed structure; Described JFET and described LDMOS shares drain region.
14. the manufacture method of JFET as claimed in claim 13, it is characterised in that: regulate the pinch-off voltage of described JFET by regulating the lateral dimension of described buried regions breach, the lateral dimension of described buried regions breach is more big, and the pinch-off voltage of described JFET is more big.
15. the manufacture method of JFET as claimed in claim 13, it is characterised in that: the described buried regions at described enclosed locations of structures place and the gate regions of described JFET be fully overlapping make the channel region of described JFET when exhausting described JFET be pinched off entirely.
16. the manufacture method of JFET as claimed in claim 13, it is characterised in that: drift region described in step one adopts deep trap technique to be formed.
17. the manufacture method of JFET as claimed in claim 13, it is characterised in that: drift region described in step one adopts epitaxial growth technology to be formed.
18. the manufacture method of JFET as claimed in claim 13, it is characterised in that: after step 3 completes, further comprise the steps of: before step 4
Form field oxide, described field oxide is above the described drift region between the channel region and described drain region of described LDMOS, second side of described field oxide and described drain region lateral contact, the first side of described field oxide and the channel region of described LDMOS are at a distance;
Form gate dielectric layer and polysilicon gate, described polysilicon gate extends to above the drift region of described LDMOS from the channel region surface of described LDMOS to direction, described drain region in the horizontal, the channel region surface of the described LDMOS covered by described polysilicon gate is for forming raceway groove, and the first side of described polysilicon gate is positioned at above described channel region, the second side is positioned at above the described field oxide at top, drift region of described LDMOS;
First conduction type heavily-doped implant of step 4 concurrently forms the source region of described LDMOS, and the source region of described LDMOS is formed at the first side autoregistration of the channel region surface of described LDMOS and the source region of described LDMOS and described polysilicon gate; The drain region of described LDMOS is positioned at outside the second side of described polysilicon gate;
Also include after step 4:
Step 5, carry out the second conduction type heavily-doped implant the surface, gate regions of described JFET formed grid draw-out area.
19. the manufacture method of JFET as claimed in claim 18, it is characterised in that: described field oxide adopts local oxidation technique to make or adopts shallow trench field oxidation technology to make.
20. the manufacture method of JFET as claimed in claim 18, it is characterised in that: further comprise the steps of: after step 5
Form interlayer film;
Form the contact hole through described interlayer film;
Form front metal layer, described front metal layer metal lithographic etching is formed the source electrode of drain electrode, the grid of the source electrode of described LDMOS, described LDMOS and described JFET; The drain region of described LDMOS is connected to described LDMOS and the described JFET drain electrode shared by contact hole; The source region of described LDMOS is connected to the source electrode of described LDMOS by contact hole; The grid draw-out area of described JFET is connected to the source electrode of described LDMOS also by contact hole, and the source electrode of described LDMOS is as the grid of described JFET; The source region of described JFET is connected to the source electrode of described JFET by contact hole, and described polysilicon gate is connected to the grid of described LDMOS by contact hole.
21. the manufacture method of JFET as claimed in claim 18, it is characterised in that: the second side of described polysilicon gate extends to described field oxide surface.
22. the manufacture method of JFET as claimed in claim 18, it is characterized in that: forming polysilicon field plate on the surface of the side, drain region of the close described LDMOS of described field oxide while forming described polysilicon gate, described polysilicon field plate is connected to the drain electrode formed by front metal layer by contact hole.
23. the manufacture method of the JFET as described in any claim in claim 13 to 22, it is characterised in that: described LDMOS and described JFET is N-type device, and the first conduction type is N-type, and the second conduction type is P type.
24. the manufacture method of the JFET as described in any claim in claim 13 to 22, it is characterised in that: described LDMOS and described JFET is P-type device, and the first conduction type is P type, and the second conduction type is N-type.
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