CN105070759A - Nldmos device and manufacturing method thereof - Google Patents
Nldmos device and manufacturing method thereof Download PDFInfo
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- CN105070759A CN105070759A CN201510546703.9A CN201510546703A CN105070759A CN 105070759 A CN105070759 A CN 105070759A CN 201510546703 A CN201510546703 A CN 201510546703A CN 105070759 A CN105070759 A CN 105070759A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 110
- 239000007924 injection Substances 0.000 claims abstract description 110
- 102100035767 Adrenocortical dysplasia protein homolog Human genes 0.000 claims abstract description 34
- 101100433963 Homo sapiens ACD gene Proteins 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 66
- 229920005591 polysilicon Polymers 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 64
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 55
- 229910052760 oxygen Inorganic materials 0.000 claims description 55
- 239000001301 oxygen Substances 0.000 claims description 55
- 239000010410 layer Substances 0.000 claims description 45
- 239000011229 interlayer Substances 0.000 claims description 40
- 230000005516 deep trap Effects 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract 2
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an NLDMOS device. The NLDMOS device includes a drift region, a P trap, a PTOP layer formed in the drift region, and P-type doped injection regions and N-type doped injection regions formed on the surface of the front side of the drift region. Each of the P-type and N-type doped injection regions is of a strip structure parallel to channels along the length. The P-type doped injection regions and the N-type doped injection regions are configured in an alternate manner. The N-type doped injection regions are used for increase the doped concentration of the surface of the drift region so that conduction resistance is reduced. The P-type doped injection regions and the N-type doped injection regions exhaust each other, so the breakdown voltage of the device will not decrease due to the increase of the doped concentration of the surface of the drift region. The invention also discloses a manufacturing method of an NLDMOS device. According to the invention, the conduction resistance of the device can be reduced and then the performance of the device can be improved while the high breakdown voltage is kept.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of N-type Laterally Diffused Metal Oxide Semiconductor (NLDMOS) device; The invention still further relates to a kind of manufacture method of NLDMOS device.
Background technology
700V Laterally Diffused Metal Oxide Semiconductor (LDMOS) device had both had discrete device high-voltage great-current feature, draw again the advantage that low-voltage ic high density intelligent logical controls, single-chip realizes the function that original multiple chip just can complete, greatly reduce area, reduce cost, improve efficiency, meet Modern Power Electronic Devices miniaturization, intellectuality, the developing direction of low energy consumption.
Puncture voltage and conducting resistance weigh the key parameter of 700VLDMOS device.Prior art can increase exhausting of drift region by forming PTOP layer on the surface of drift region, and realizing reducing surface field (Resurf) effect, as shown in Figure 1, is the structural representation of existing NLDMOS device; Silicon substrate 1 is formed and is made up of N-type deep trap 2, P trap 4 and drift region separated by a distance, P trap 4 is also surrounded by a N-type deep trap 2, field oxygen 3 is formed at N-type deep trap 2 surface, grid structure is made up of gate oxide 6 and polysilicon gate 7, source region 8b to be formed in P trap 4 and and polysilicon gate 7 autoregistration, P trap draw-out area 9 is formed at P trap 4 surperficial Bing You P+ district composition, and drain region 8a is formed at surface, drift region also and the side autoregistration of field oxygen 3; The 8a side, close drain region of oxygen 3 on the scene is formed with polysilicon field plate 7a, and polysilicon field plate 7a and polysilicon gate 7 are all that same layer polysilicon chemical wet etching is formed.The device area of bottom covers by interlayer film 10, is drawn source electrode, the drain and gate of device by contact hole and front metal layer 11.Be formed with PTOP layer 5 on the surface of drift region, being also formed with PTOP layer 5, PTOP layer 5 in the bottom of the P trap 4 of 8b side, source region can increase exhausting of drift region, reduces surface field, the final puncture voltage improving device.
Because puncture voltage and conducting resistance weigh the key parameter of 700VLDMOS device, although the existing device described in Fig. 1 can improve the puncture voltage of device, if the conducting resistance of device further can be reduced, then the performance of device can be improved.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of NLDMOS device, under maintenance has the condition of higher puncture voltage, can reduce the conducting resistance of device, thus improve the performance of device.For this reason, the present invention also provides a kind of manufacture method of NLDMOS device.
For solving the problems of the technologies described above, NLDMOS device provided by the invention comprises:
The drift region of N-type doping, is formed in P type semiconductor substrate.
P trap, is formed in described P type semiconductor substrate, described P trap and described drift region contacts side surfaces or separated by a distance.
Be formed at the polysilicon gate of described semiconductor substrate, described polysilicon gate and the isolation of described semiconductor substrate surface have gate dielectric layer, described polysilicon gate extends to above described drift region from described P trap in the horizontal, and the described P trap covered by described polysilicon gate is for the formation of raceway groove; First side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above described drift region.
The source region be made up of N+ district and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region.
The substrate draw-out area be made up of P+ district, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap, described substrate draw-out area and described source region lateral contact.
Oxygen, above the described drift region between described P trap and described drain region, the second side of described field oxygen and described drain region lateral contact, the first side of described field oxygen and described P trap are separated by a segment distance; Described polysilicon gate extends to above the oxygen of described field.
PTOP layer, is formed in described drift region, has interval in the vertical between described PTOP layer and the front face surface of described drift region.
Be formed at P type doping injection region and the N-type doping injection region of described drift region front face surface, in the vertical, each described P type doping injection region is identical to the junction depth of inside extension injection region and each described P type doping injection region and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region, has interval between the bottom of each described P type doping injection region or each N-type doping injection region and the described PTOP layer of bottom, in the horizontal, the direction extended to described drain region from described source region is made to be orientation, vertical with described orientation is channel width dimension, each described P type doping injection region is all the list structure parallel with described orientation with each described N-type doping injection region, be arranged alternately along each described P type doping injection region of described channel width dimension and each described N-type doping injection region structure, each described N-type doping injection region for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region is for realizing adulterating with adjacent described N-type mutually exhausting of injection region, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region.
Further improvement is, described drift region is made up of the first N-type deep trap, described P trap and described drift region separated by a distance, described P trap is surrounded by the second N-type deep trap, and described first N-type deep trap is identical and separated by a distance with described second N-type deep trap process conditions.
Further improvement is, is also formed with described PTOP layer in the bottom of described P trap.
Further improvement is, described Semiconductor substrate is silicon substrate.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, described field oxygen is shallow trench field oxygen or local field oxygen.
Further improvement is, interlayer film is formed in described Semiconductor substrate front, the source electrode, the drain and gate that are formed by front metal layer is formed at the top of described interlayer film, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
Further improvement is, be formed with polysilicon field plate in the side, close described drain region at the top of described field oxygen, described polysilicon field plate is by connecting described drain electrode through the contact hole of described interlayer film.
Further improvement is, the operating voltage of NLDMOS device is 700V.
For solving the problems of the technologies described above, the manufacture method of NLDMOS device provided by the invention comprises the steps:
Step one, the drift region of adulterating in P type semiconductor substrate formation N-type.
Step 2, above described drift region, form field oxygen.
Step 3, photoetching are opened P trap injection region and are carried out P trap and be infused in described P type semiconductor substrate and form P trap, described P trap and described drift region contacts side surfaces or separated by a distance.
Step 4, photoetching open PTOP injection zone, carry out PTOP and are infused in described drift region and form PTOP layer, have interval in the vertical between described PTOP layer and the front face surface of described drift region.
Step 5, employing photoetching add ion implantation technology and form P type doping injection region and N-type doping injection region respectively in described drift region front face surface, in the vertical, each described P type doping injection region is identical to the junction depth of inside extension injection region and each described P type doping injection region and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region, has interval between the bottom of each described P type doping injection region or each N-type doping injection region and the described PTOP layer of bottom, in the horizontal, the direction extended to drain region from source region is made to be orientation, vertical with described orientation is channel width dimension, each described P type doping injection region is all the list structure parallel with described orientation with each described N-type doping injection region, be arranged alternately along each described P type doping injection region of described channel width dimension and each described N-type doping injection region structure, each described N-type doping injection region for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region is for realizing adulterating with adjacent described N-type mutually exhausting of injection region, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region.
Step 6, formation gate dielectric layer and polysilicon gate, described polysilicon gate extends to above described drift region from described P trap in the horizontal, the described P trap covered by described polysilicon gate for the formation of raceway groove, above the described field oxygen that the first side is positioned at above described P trap, the second side is positioned at top, described drift region of described polysilicon gate.
Step 7, carry out N+ and inject and form described source region and described drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region, the second side of described field oxygen and described drain region lateral contact.
Step 8, carry out P+ and inject and form substrate draw-out area, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap, described substrate draw-out area and described source region lateral contact.
Further improvement is, described drift region is made up of the first N-type deep trap, described P trap and described drift region separated by a distance, described P trap is surrounded by the second N-type deep trap, adopts photoetching process open the forming region of described first N-type deep trap and described second N-type deep trap simultaneously and carry out N-type ion implantation and form described first N-type deep trap and described second N-type deep trap simultaneously in step one.
Further improvement is, forms described PTOP layer in step 4 in the bottom of described P trap simultaneously.
Further improvement is, described Semiconductor substrate is silicon substrate.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, described field oxygen is the shallow trench field oxygen adopting shallow ditch groove separation process to be formed, or described field oxygen is the local field oxygen adopting local field oxygen technique to be formed.
Further improvement also comprises the steps:
Step 9, form interlayer film in described Semiconductor substrate front.
Step 10, form contact hole through described interlayer film, described contact hole contacts with described substrate draw-out area, described drain region and described polysilicon gate with the described source region of bottom correspondence.
Step 11, form front metal layer at described interlayer film top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
Further improvement is, while forming described polysilicon gate, form polysilicon field plate in the side, close described drain region at the top of described field oxygen in step 6, described polysilicon field plate is by connecting described drain electrode through the contact hole of described interlayer film.
Further improvement is, the operating voltage of NLDMOS device is 700V.
NLDMOS device of the present invention, by forming PTOP layer in drift region, can make the puncture voltage that device keeps higher, the present invention is simultaneously also by forming P type doping injection region and N-type doping injection region in the front face surface position of drift region, each P type is all the list structure parallel with orientation with N-type doping injection region, and to be arranged alternately structure along channel width dimension, each N-type doping injection region can increase the doping content on surface, drift region on source and drain passage thus the conducting resistance of reduction drift region, and P type doping injection region can exhaust adjacent N-type doping injection region, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of drift region, so the present invention can under maintenance has the condition of higher puncture voltage, reduce the conducting resistance of device, thus improve the performance of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing NLDMOS device;
Fig. 2 A is the domain of embodiment of the present invention NLDMOS device;
Fig. 2 B is the device profile structural representation of the tangent line AA along Fig. 2 A;
Fig. 2 C is the device profile structural representation of the tangent line BB along Fig. 2 A;
Fig. 3 A-Fig. 3 H is the device architecture schematic diagram in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 2 A, be the domain of embodiment of the present invention NLDMOS device; As shown in Figure 2 B, be the device profile structural representation of tangent line AA along Fig. 2 A; As shown in Figure 2 C, be the device profile structural representation of tangent line BB along Fig. 2 A; The operating voltage of embodiment of the present invention NLDMOS device is 700V, comprising:
The drift region of N-type doping, is formed in P type semiconductor substrate 101.Described Semiconductor substrate 101 is silicon substrate.
P trap 104, is formed in described P type semiconductor substrate 101, described P trap 104 and described drift region contacts side surfaces or separated by a distance.
Be preferably, described drift region is made up of the first N-type deep trap 102a, described P trap 104 and described drift region separated by a distance, described P trap 104 is surrounded by the second N-type deep trap 102b, and described first N-type deep trap 102a is identical and separated by a distance with described second N-type deep trap 102b process conditions.
Be formed at the polysilicon gate 107 above described Semiconductor substrate 101, described polysilicon gate 107 and the isolation of described Semiconductor substrate 101 surface have gate dielectric layer 106 as gate oxide, described polysilicon gate 107 extends to above described drift region from described P trap 104 in the horizontal, and the described P trap 104 covered by described polysilicon gate 107 is for the formation of raceway groove; First side of described polysilicon gate 107 is positioned at above described P trap 104, the second side is positioned at above described drift region.
The source region 108b be made up of N+ district and drain region 108a, described source region 108b to be formed in described P trap 104 and and the first side autoregistration of described polysilicon gate 107, described drain region 108a is formed in described drift region.
The substrate draw-out area 109 be made up of P+ district, described substrate draw-out area 109 to be formed in described P trap 104 and for being drawn by described P trap 104, described substrate draw-out area 109 and described source region 108b lateral contact.
Oxygen 103, above the described drift region between described P trap 104 and described drain region 108a, the second side of described field oxygen 103 and described drain region 108a lateral contact, the first side of described field oxygen 103 and described P trap 104 are separated by a segment distance; Described polysilicon gate 107 extends to above described field oxygen 103.Described field oxygen 103 is shallow trench field oxygen or local field oxygen.
PTOP layer 105, is formed in described drift region, has interval in the vertical between described PTOP layer 105 and the front face surface of described drift region.
Be formed at P type doping injection region 105a and the N-type doping injection region 105b of described drift region front face surface, in the vertical, each described P type doping injection region 105a is identical to the junction depth of inside extension injection region 105b and each described P type doping injection region 105a and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region 105b, has interval between the bottom of each described P type doping injection region 105a or each N-type doping injection region 105b and the described PTOP layer 105 of bottom, in the horizontal, order is orientation from described source region 108b to the direction that described drain region 108a extends, vertical with described orientation is channel width dimension, each described P type doping injection region 105a is the list structure parallel with described orientation with each described N-type doping injection region 105b, to be arranged alternately structure along described channel width dimension each described P type doping injection region 105a and each described N-type doping injection region 105b, each described N-type doping injection region 105b for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region 105a is for realizing adulterating with adjacent described N-type mutually exhausting of injection region 105b, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region.
Interlayer film 110 is formed in described Semiconductor substrate 101 front, the source electrode, the drain and gate that are formed by front metal layer 111 is formed at the top of described interlayer film 110, described source electrode is contacted with described source region 108b and described substrate draw-out area 109 by the contact hole through described interlayer film 110, described drain electrode is contacted with described drain region 108a by the contact hole through described interlayer film 110, and described grid is contacted with described polysilicon gate 107 by the contact hole through described interlayer film 110.
Be formed with polysilicon field plate 107a in the 108a side, close described drain region at the top of described field oxygen 103, described polysilicon field plate 107a is by connecting described drain electrode through the contact hole of described interlayer film 110.
As shown in Fig. 3 A to Fig. 3 H, be the device architecture schematic diagram in each step of embodiment of the present invention method, the operating voltage of the NLDMOS device of the manufacture method of embodiment of the present invention NLDMOS device is 700V, comprises the steps:
Step one, as shown in Figure 3A, forms the drift region of N-type doping at P type P type semiconductor substrate 101.Be preferably, described drift region is made up of the first N-type deep trap 102a, the second N-type deep trap 102b is formed while the described first N-type deep trap 102a of formation, described second N-type deep trap 102b and described first N-type deep trap 102a is separated by a distance, and the P trap 104 of follow-up formation is arranged in described second N-type deep trap 102b.
Described Semiconductor substrate 101 is silicon substrate.
Step 2, as shown in Figure 3 B, above described drift region, form field oxygen 103.Described field oxygen 103 is the shallow trench field oxygen adopting shallow ditch groove separation process (STI) to be formed, or described field oxygen 103 is the local field oxygen adopting local field oxygen technique (LOCOS) to be formed.
Step 3, as shown in Figure 3 C, photoetching is opened P trap 104 injection region and is carried out P trap 104 and is infused in described P type semiconductor substrate 101 and forms P trap 104, and the trap of P described in the embodiment of the present invention 104 is arranged in described second N-type deep trap 102b.
Step 4, as shown in Figure 3 D, PTOP injection zone is opened in photoetching, carries out PTOP and is infused in described drift region and forms PTOP layer 105, have interval in the vertical between described PTOP layer 105 and the front face surface of described drift region.
Step 5, is as shown in FIGURE 3 E the device profile structural representation of the tangent line AA along Fig. 2 A, as illustrated in Figure 3 F, be the device profile structural representation of tangent line BB along Fig. 2 A, adopt photoetching to add ion implantation technology and form P type doping injection region 105a and N-type doping injection region 105b respectively in described drift region front face surface, in the vertical, each described P type doping injection region 105a is identical to the junction depth of inside extension injection region 105b and each described P type doping injection region 105a and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region 105b, has interval between the bottom of each described P type doping injection region 105a or each N-type doping injection region 105b and the described PTOP layer 105 of bottom, in the horizontal, order is orientation from described source region 108b to the direction that described drain region 108a extends, vertical with described orientation is channel width dimension, each described P type doping injection region 105a is the list structure parallel with described orientation with each described N-type doping injection region 105b, to be arranged alternately structure along described channel width dimension each described P type doping injection region 105a and each described N-type doping injection region 105b, each described N-type doping injection region 105b for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region 105a is for realizing adulterating with adjacent described N-type mutually exhausting of injection region 105b, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region.
Step 6, as shown in Figure 3 G, form gate dielectric layer as gate oxide 106 and polysilicon gate 107, described polysilicon gate 107 extends to above described drift region from described P trap 104 in the horizontal, the described P trap 104 covered by described polysilicon gate 107 for the formation of raceway groove, above the described field oxygen 103 that the first side is positioned at above described P trap 104, the second side is positioned at top, described drift region of described polysilicon gate 107.
While forming described polysilicon gate 107, polysilicon field plate 107a is formed in the 108a side, close described drain region at the top of described field oxygen 103 in this step 6.
Step 7, as shown in figure 3h, carry out N+ and inject formation source region 108b and drain region 108a, described source region 108b to be formed in described P trap 104 and and the first side autoregistration of described polysilicon gate 107, described drain region 108a is formed in described drift region, second side of described field oxygen 103 and described drain region 108a lateral contact are also the second side autoregistration of described drain region 108a and described field oxygen 103.
Step 8, as shown in figure 3h, carries out P+ and injects and form substrate draw-out area 109, and described substrate draw-out area 109 to be formed in described P trap 104 and for being drawn by described P trap 104, described substrate draw-out area 109 and described source region 108b lateral contact.
Step 9, as shown in Figure 2 C, be formed with interlayer film 110 in described Semiconductor substrate 101 front.
Step 10, as shown in Figure 2 C, form the contact hole through described interlayer film 110, described contact hole contacts with described substrate draw-out area 109, described drain region 108a and described polysilicon gate 107 with the described source region 108b of bottom correspondence;
Step 11, as shown in Figure 2 C, form front metal layer 111 at described interlayer film 110 top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region 108b and described substrate draw-out area 109 by the contact hole through described interlayer film 110, described drain electrode is contacted with described drain region 108a by the contact hole through described interlayer film 110, and described grid is contacted with described polysilicon gate 107 by the contact hole through described interlayer film 110.Described polysilicon field plate 107a is by connecting described drain electrode through the contact hole of described interlayer film 110.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (18)
1. a NLDMOS device, is characterized in that, comprising:
The drift region of N-type doping, is formed in P type semiconductor substrate;
P trap, is formed in described P type semiconductor substrate, described P trap and described drift region contacts side surfaces or separated by a distance;
Be formed at the polysilicon gate of described semiconductor substrate, described polysilicon gate and the isolation of described semiconductor substrate surface have gate dielectric layer, described polysilicon gate extends to above described drift region from described P trap in the horizontal, and the described P trap covered by described polysilicon gate is for the formation of raceway groove; First side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above described drift region;
The source region be made up of N+ district and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region;
The substrate draw-out area be made up of P+ district, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap, described substrate draw-out area and described source region lateral contact;
Oxygen, above the described drift region between described P trap and described drain region, the second side of described field oxygen and described drain region lateral contact, the first side of described field oxygen and described P trap are separated by a segment distance; Described polysilicon gate extends to above the oxygen of described field;
PTOP layer, is formed in described drift region, has interval in the vertical between described PTOP layer and the front face surface of described drift region;
Be formed at P type doping injection region and the N-type doping injection region of described drift region front face surface, in the vertical, each described P type doping injection region is identical to the junction depth of inside extension injection region and each described P type doping injection region and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region, has interval between the bottom of each described P type doping injection region or each N-type doping injection region and the described PTOP layer of bottom, in the horizontal, the direction extended to described drain region from described source region is made to be orientation, vertical with described orientation is channel width dimension, each described P type doping injection region is all the list structure parallel with described orientation with each described N-type doping injection region, be arranged alternately along each described P type doping injection region of described channel width dimension and each described N-type doping injection region structure, each described N-type doping injection region for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region is for realizing adulterating with adjacent described N-type mutually exhausting of injection region, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region.
2. NLDMOS device as claimed in claim 1, it is characterized in that: described drift region is made up of the first N-type deep trap, described P trap and described drift region separated by a distance, described P trap is surrounded by the second N-type deep trap, and described first N-type deep trap is identical and separated by a distance with described second N-type deep trap process conditions.
3. NLDMOS device as claimed in claim 2, is characterized in that: be also formed with described PTOP layer in the bottom of described P trap.
4. NLDMOS device as claimed in claim 1, is characterized in that: described Semiconductor substrate is silicon substrate.
5. NLDMOS device as claimed in claim 1, is characterized in that: described gate dielectric layer is gate oxide.
6. NLDMOS device as claimed in claim 1, is characterized in that: described field oxygen is shallow trench field oxygen or local field oxygen.
7. NLDMOS device as claimed in claim 1, it is characterized in that: be formed with interlayer film in described Semiconductor substrate front, the source electrode, the drain and gate that are formed by front metal layer is formed at the top of described interlayer film, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
8. NLDMOS device as claimed in claim 7, is characterized in that: be formed with polysilicon field plate in the side, close described drain region at the top of described field oxygen, described polysilicon field plate is by connecting described drain electrode through the contact hole of described interlayer film.
9. the NLDMOS device as described in claim arbitrary in claim 1 to 8, is characterized in that: the operating voltage of NLDMOS device is 700V.
10. a manufacture method for NLDMOS device, is characterized in that, comprises the steps:
Step one, the drift region of adulterating in P type semiconductor substrate formation N-type;
Step 2, above described drift region, form field oxygen;
Step 3, photoetching are opened P trap injection region and are carried out P trap and be infused in described P type semiconductor substrate and form P trap, described P trap and described drift region contacts side surfaces or separated by a distance;
Step 4, photoetching open PTOP injection zone, carry out PTOP and are infused in described drift region and form PTOP layer, have interval in the vertical between described PTOP layer and the front face surface of described drift region;
Step 5, employing photoetching add ion implantation technology and form P type doping injection region and N-type doping injection region respectively in described drift region front face surface, in the vertical, each described P type doping injection region is identical to the junction depth of inside extension injection region and each described P type doping injection region and each described N-type are adulterated of described drift region from the front face surface of described drift region with each described N-type doping injection region, has interval between the bottom of each described P type doping injection region or each N-type doping injection region and the described PTOP layer of bottom, in the horizontal, the direction extended to drain region from source region is made to be orientation, vertical with described orientation is channel width dimension, each described P type doping injection region is all the list structure parallel with described orientation with each described N-type doping injection region, be arranged alternately along each described P type doping injection region of described channel width dimension and each described N-type doping injection region structure, each described N-type doping injection region for increasing surface, described drift region doping content thus reduce the conducting resistance of described drift region, each described P type doping injection region is for realizing adulterating with adjacent described N-type mutually exhausting of injection region, the puncture voltage of device can not be reduced because of the increase of the surface dopant concentration of described drift region,
Step 6, formation gate dielectric layer and polysilicon gate, described polysilicon gate extends to above described drift region from described P trap in the horizontal, the described P trap covered by described polysilicon gate for the formation of raceway groove, above the described field oxygen that the first side is positioned at above described P trap, the second side is positioned at top, described drift region of described polysilicon gate;
Step 7, carry out N+ and inject and form described source region and described drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region, the second side of described field oxygen and described drain region lateral contact;
Step 8, carry out P+ and inject and form substrate draw-out area, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap, described substrate draw-out area and described source region lateral contact.
11. methods as claimed in claim 10, it is characterized in that: described drift region is made up of the first N-type deep trap, described P trap and described drift region separated by a distance, described P trap is surrounded by the second N-type deep trap, adopts photoetching process open the forming region of described first N-type deep trap and described second N-type deep trap simultaneously and carry out N-type ion implantation and form described first N-type deep trap and described second N-type deep trap simultaneously in step one.
12. methods as claimed in claim 11, is characterized in that: form described PTOP layer in the bottom of described P trap in step 4 simultaneously.
13. methods as claimed in claim 10, is characterized in that: described Semiconductor substrate is silicon substrate.
14. methods as claimed in claim 10, is characterized in that: described gate dielectric layer is gate oxide.
15. methods as claimed in claim 10, is characterized in that: described field oxygen is the shallow trench field oxygen adopting shallow ditch groove separation process to be formed, or described field oxygen is the local field oxygen adopting local field oxygen technique to be formed.
16. methods as claimed in claim 10, is characterized in that: also comprise the steps:
Step 9, form interlayer film in described Semiconductor substrate front;
Step 10, form contact hole through described interlayer film, described contact hole contacts with described substrate draw-out area, described drain region and described polysilicon gate with the described source region of bottom correspondence;
Step 11, form front metal layer at described interlayer film top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
17. methods as claimed in claim 16, it is characterized in that: while forming described polysilicon gate, form polysilicon field plate in the side, close described drain region at the top of described field oxygen in step 6, described polysilicon field plate is by connecting described drain electrode through the contact hole of described interlayer film.
18. methods as described in claim arbitrary in claim 10 to 17, is characterized in that: the operating voltage of NLDMOS device is 700V.
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