CN104659091A - Ldmos device and manufacturing method thereof - Google Patents
Ldmos device and manufacturing method thereof Download PDFInfo
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- CN104659091A CN104659091A CN201310589117.3A CN201310589117A CN104659091A CN 104659091 A CN104659091 A CN 104659091A CN 201310589117 A CN201310589117 A CN 201310589117A CN 104659091 A CN104659091 A CN 104659091A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 52
- 238000002347 injection Methods 0.000 claims abstract description 17
- 239000007924 injection Substances 0.000 claims abstract description 17
- 230000005684 electric field Effects 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 47
- 229910052760 oxygen Inorganic materials 0.000 claims description 47
- 239000001301 oxygen Substances 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 37
- 238000000407 epitaxy Methods 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 158
- 238000000605 extraction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The invention discloses an LDMOS device. An N type injection layer formed by injecting high-dosage N type impurities is additionally arranged in a drift region formed by an N type epitaxial layer; a P type auxiliary depletion layer is formed on the surface of the N type injection layer at the bottom of a field oxide layer between a drain region and a P well; the junction depth and the doping amount of the P type auxiliary depletion layer are gradually reduced in the direction from the source terminal side to the drain terminal side. The invention further discloses a manufacturing method of the LDMOS device. The LDMOS device disclosed by the invention can reduce the on resistance of the device and increase the breakover current of the device, meanwhile lowers the surface electric field intensity in the drift region, increases the breakdown voltage of the device, and further can be integrated with a BCD technology without the extra process cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of lateral double diffusion metal oxide semiconductor field effect transistor (lateral double-dif fused MOSFET, LDMOS) device, the invention still further relates to this LDMOS device manufacture method.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor (DMOS) is high pressure resistant owing to having, and the feature such as high current drive capability and extremely low power dissipation, is widely adopted at present in electric power management circuit.In LDMOS device, conducting resistance is an important index.At BCD (Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductors (CMOS)-dual diffused metal oxide emiconductor) in technique, although DMOS with CMOS is integrated in same chip, but and requirement of low on-resistance withstand voltage due to height, under the prerequisite that the condition of DMOS in background region and drift region and the existing process conditions of CMOS are shared, its conducting resistance is higher, often cannot meet the requirement of switching tube application.Therefore, in order to make high performance LDMOS, need the conducting resistance adopting various method optimised devices.Usual needs increase by one extra N-type injection in the drift region of device, make device have lower conducting resistance, and adopt the puncture voltage that can reduce device in this way.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of LDMOS device, the conducting resistance of device can be reduced, increase the On current of device, the surface field intensity of drift region can be reduced simultaneously, increase the puncture voltage of device, can be integrated in BCD technique, not need to increase additional technology cost.For this reason, present invention also offers the manufacture method of LDMOS device.
For solving the problems of the technologies described above, LDMOS device provided by the invention comprises:
N-type epitaxy layer, is formed at P-type silicon substrate on the surface.
P trap, is formed in described N-type epitaxy layer.
N trap, is formed in described N-type epitaxy layer; Described N trap and described P trap are separated by a segment distance, are provided with a field oxygen layer between described N trap and described P trap, and the first side of described field oxygen layer and described P trap are separated by a segment distance, and the second side of described field oxygen layer extends to above described N trap.
N-type implanted layer, is formed in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, and N trap direction described in the second side direction of described N-type implanted layer extends and surrounded by described N trap.
P type assisted depletion layer, be formed at described N-type implanted layer surface and be positioned at the bottom of described field oxygen layer, the width of described P type assisted depletion layer is less than the bottom width of described field oxygen layer; First side of described P type assisted depletion layer near the second side of described P trap, described P type assisted depletion layer near described N trap, from the first side of described P type assisted depletion layer to the second side upwards, the junction depth of described P type assisted depletion layer reduces gradually, doping reduces gradually.
Grid structure, be made up of the gate dielectric layer and polysilicon gate that are formed at described N-type epitaxy layer surface, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove.
Source region, forms by being formed at described P trap Zhong N+ district, the first side autoregistration of described source region and described grid structure.
Drain region, forms by being formed at described N trap Zhong N+ district, described drain region and the oxygen layer autoregistration of described field.
P type substrate draw-out area, forms, for drawing described P trap by being formed at described P trap Zhong P+ district.
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer is used for exhausting described N-type implanted layer, the junction depth of described P type assisted depletion layer and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer exhausts rear surface electric field smooth.
Further improvement is, the implanted dopant of the ion implantation of described N-type implanted layer is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Further improvement is, described P type assisted depletion layer is combined after diffusion by a multiple P type ion implanted region separated by a distance, from the first side of described P type assisted depletion layer to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually, the implanted dopant of each described P type ion implanted region is boron, Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
For solving the problems of the technologies described above, the manufacture method of LDMOS device provided by the invention comprises the steps:
Step one, P-type silicon substrate surface formed N-type epitaxy layer.
Step 2, photoetching are opened P trap injection zone and are carried out P type ion implantation in this region and form P trap in described N-type epitaxy layer; Photoetching is opened N trap injection zone and is carried out N-type ion implantation in this region and form N trap in described N-type epitaxy layer, a segment distance of being separated by between described P trap and described N trap.
Step 3, photoetching are opened N-type implanted layer region and are carried out N-type ion implantation in this region and form N-type implanted layer in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, N trap direction described in the second side direction of described N-type implanted layer extends and is surrounded by described N trap.
Step 4, photoetching are opened the injection zone of the P type ion implanted region for forming P type assisted depletion layer and are carried out a P type ion implantation at this injection zone and form each described P type ion implanted region, first side of described P type assisted depletion layer near the second side of described P trap, described P type assisted depletion layer near described N trap, from the first side of described P type assisted depletion layer to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually.
Step 5, to each described P type ion implanted region pick into, each described P type ion implanted region combines described P type assisted depletion layer through picking after diffusion, from the first side of described P type assisted depletion layer to the second side upwards, the junction depth of described P type assisted depletion layer reduces gradually, doping reduces gradually.
Step 6, deposit field oxygen layer chemical wet etching is carried out to described field oxygen layer, between described N trap and described P trap, a described field oxygen layer is provided with after etching, first side of described field oxygen layer and described P trap are separated by a segment distance, and the second side of described field oxygen layer extends to above described N trap.
Step 7, on described N-type epitaxy layer surface successively deposit gate dielectric layer and polysilicon gate, chemical wet etching is carried out to described polysilicon gate and described gate dielectric layer and forms grid structure, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove.
Step 8, carry out N+ source and drain ion implantation and form source region and drain region, described source region is arranged in described P trap, the first side autoregistration of described source region and described grid structure; Described drain region is arranged in described N trap, described drain region and the oxygen layer autoregistration of described field; Carry out P+ ion implantation and form P type substrate draw-out area, described P type substrate draw-out area is arranged in described P trap, for drawing described P trap.
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer is used for exhausting described N-type implanted layer, the junction depth of described P type assisted depletion layer and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer exhausts rear surface electric field smooth.
Further improvement is, the implanted dopant of the ion implantation of the implanted layer of N-type described in step 3 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Further improvement is, in step 4, the implanted dopant of each described P type ion implanted region is boron, and Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Further improvement is, the resistivity of described P-type silicon substrate is 0.007 ohmcm ~ 0.013 ohmcm.
Further improvement is, the manufacturing process of described LDMOS device is integrated in BCD technique, described P trap in the manufacturing process of described LDMOS device is identical with the P trap technique of the cmos device in described BCD technique and synchronously formed, described N trap in the manufacturing process of described LDMOS device is identical with the N-well process of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ ion implantation of the described P type substrate draw-out area in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
The present invention has following beneficial effect:
1, LDMOS device of the present invention is injected by the doping of adjusting device, and the N-type impurity increasing high dose in drift region injects the conducting resistance that formation N-type implanted layer effectively can reduce device.
2, the present invention is by forming a non-homogeneous P type assisted depletion layer reduced gradually from P trap to N trap direction doping on the N-type implanted layer surface of the bottom being positioned at an oxygen layer, can realize utilizing P type assisted depletion layer to exhaust N-type implanted layer, thus the puncture voltage of device can be increased; It is smooth that the present invention can also utilize the non-uniform doping structure of P type assisted depletion layer to make N-type implanted layer exhaust rear surface electric field, thus further can improve the puncture voltage of device.
3, the present invention can be integrated in BCD technique, and not needing increases additional technology cost.As all process conditions of the present invention as source and drain injection technology can share with the CMOS technology in BCD technique platform.
4, have higher puncture voltage because device of the present invention has larger conducting resistance, all devices of the present invention can meet the operating characteristic of switching device and analogue device simultaneously simultaneously.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention LDMOS device;
Fig. 2 is the simulation architecture figure of embodiment of the present invention LDMOS device;
Fig. 3 is the electric field strength profile figure of the embodiment of the present invention LDMOS device along the tangent position place in Fig. 2;
Device architecture schematic diagram in each step of the manufacture method of Fig. 4 A-Fig. 4 J embodiment of the present invention LDMOS device.
Embodiment
Fig. 1 is the structural representation of embodiment of the present invention LDMOS device; Embodiment of the present invention LDMOS device is N-type LDMOS device, comprising:
N-type epitaxy layer 102, is formed at P-type silicon substrate 101 on the surface.
P trap 103, is formed in described N-type epitaxy layer 102.
N trap 104, is formed in described N-type epitaxy layer 102; Described N trap 104 and described P trap 103 are separated by a segment distance, a field oxygen layer 107 is provided with between described N trap 104 and described P trap 103, first side of described field oxygen layer 107 and described P trap 103 are separated by a segment distance, and the second side of described field oxygen layer 107 extends to above described N trap 104.
N-type implanted layer 105, is formed in described N-type epitaxy layer 102, the contacts side surfaces of described N-type implanted layer 105 first side and described P trap 103, and N trap 104 direction described in the second side direction of described N-type implanted layer 105 extends and surrounded by described N trap 104.Be preferably, the implanted dopant of the ion implantation of described N-type implanted layer 105 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
P type assisted depletion layer 106, be formed at described N-type implanted layer 105 surface and be positioned at the bottom of described field oxygen layer 107, the width of described P type assisted depletion layer 106 is less than the bottom width of described field oxygen layer 107; First side of described P type assisted depletion layer 106 near the second side of described P trap 103, described P type assisted depletion layer 106 near described N trap 104, from the first side of described P type assisted depletion layer 106 to the second side upwards, the junction depth of described P type assisted depletion layer 106 reduces gradually, doping reduces gradually.Be preferably, described P type assisted depletion layer 106 is combined after diffusion by a multiple P type ion implanted region separated by a distance, from the first side of described P type assisted depletion layer 106 to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually, the implanted dopant of each described P type ion implanted region is boron, Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Grid structure, is made up of the gate dielectric layer 108 and polysilicon gate 109 being formed at described N-type epitaxy layer 102 surface; Be preferably, described gate dielectric layer 108 is gate oxide, and the side of described polysilicon gate 109 is formed with side wall 110.P trap 103 surface described in described grid structure cover part also extends transverse to described N-type implanted layer 105 surface and described field oxygen layer 107 on the surface, described P trap 103 surface that covers by described grid structure for the formation of raceway groove.
Source region 111a, forms by being formed at described P trap 103 Zhong N+ district, the first side autoregistration of described source region 111a and described grid structure.
Drain region 111b, forms by being formed at described N trap 104 Zhong N+ district, described drain region 111b and oxygen layer 107 autoregistration of described field.
P type substrate draw-out area 112, forms, for drawing described P trap 103 by being formed at described P trap 103 Zhong P+ district.
The drift region of LDMOS device is made up of the described N-type implanted layer 105 between described N trap 104 and described P trap 103, described P type assisted depletion layer 106 and described N-type epitaxy layer 102; The doping content of described N-type implanted layer 105 is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer 106 for exhausting described N-type implanted layer 105, the junction depth of described P type assisted depletion layer 106 and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer 105 exhausts rear surface electric field smooth.
Described source region 111a, described drain region 111b, described P type substrate draw-out area 112 and described polysilicon gate 109 are connected respectively by contact hole 113 and top metal lead-in wire and realize the extraction of source electrode, drain electrode, P type substrate extraction electrode and grid respectively.
Embodiment of the present invention LDMOS device is not injected by means of only the N-type impurity increasing high dose in drift region and is formed the conducting resistance that N-type implanted layer effectively reduces device; The surface electric field distribution of P type assisted depletion layer to drift region also carrying out P type ion implantation formation non-uniform doping by being positioned at an oxygen layer bottom section on the surface of N-type implanted layer is optimized, thus the puncture voltage of device can be improved, so the problem that the puncture voltage caused when the embodiment of the present invention can avoid the N-type impurity of simple increase drift region in prior art to inject reduces.As shown in Figure 2, be the simulation architecture figure of embodiment of the present invention LDMOS device; Oxygen layer 107 bottom section on the scene is also be formed with P type assisted depletion layer in the tangent line 1 of Fig. 2; As shown in Figure 3, be the electric field strength profile figure of embodiment of the present invention LDMOS device along tangent line 1 position in Fig. 2; Known, as can be seen from electric field strength profile 2, the electric field strength of the embodiment of the present invention does not also concentrate the corner of the side, close source region of oxygen layer 107 on the scene, electric field strength compares the bottom being evenly distributed in whole field oxygen layer 107, do not have to occur obviously high and low region, when device breakdown, curve 2 enclose area and can greatly increase, also namely the puncture voltage of the embodiment of the present invention can increase greatly.
The manufacture method of embodiment of the present invention LDMOS device comprises the steps:
Step one, as shown in Figure 4 A, forms N-type epitaxy layer 102 on P-type silicon substrate 101 surface.The resistivity of described P-type silicon substrate 101 is 0.007 ohmcm ~ 0.013 ohmcm.
Step 2, as shown in Figure 4 B, photoetching is opened P trap 103 injection zone and is carried out P type ion implantation in this region and form P trap 103 in described N-type epitaxy layer 102; Photoetching is opened N trap 104 injection zone and is carried out N-type ion implantation in this region and in described N-type epitaxy layer 102, forms N trap 104, a segment distance of being separated by between described P trap 103 and described N trap 104.
Step 3, as shown in Figure 4 C, photoetching is opened N-type implanted layer 105 region and is carried out N-type ion implantation in this region and form N-type implanted layer 105 in described N-type epitaxy layer 102, the contacts side surfaces of described N-type implanted layer 105 first side and described P trap 103, N trap 104 direction described in the second side direction of described N-type implanted layer 105 extends and is surrounded by described N trap 104.Be preferably, the implanted dopant of the ion implantation of described N-type implanted layer 105 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Step 4, as shown in Figure 4 D, utilize active area photoetching to form photoetching offset plate figure 114 open the injection zone of the P type ion implanted region for forming P type assisted depletion layer 106 and carry out a P type ion implantation at this injection zone and form each described P type ion implanted region, first side of described P type assisted depletion layer 106 is near described P trap 103, second side of described P type assisted depletion layer 106 is near described N trap 104, from the first side of described P type assisted depletion layer 106 to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually.Be preferably, the implanted dopant of each described P type ion implanted region is boron, and Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
Step 5, as shown in Figure 4 E, remove described photoetching offset plate figure 114.As illustrated in figure 4f, to each described P type ion implanted region pick into, each described P type ion implanted region combines described P type assisted depletion layer 106 through picking after diffusion, from the first side of described P type assisted depletion layer 106 to the second side upwards, the junction depth of described P type assisted depletion layer 106 reduces gradually, doping reduces gradually.
Step 6, as shown in Figure 4 G, deposit field oxygen layer 107 also carries out chemical wet etching to described field oxygen layer 107, between described N trap 104 and described P trap 103, a described field oxygen layer 107 is provided with after etching, first side of described field oxygen layer 107 and described P trap 103 are separated by a segment distance, and the second side of described field oxygen layer 107 extends to above described N trap 104.
Step 7, as shown at figure 4h, on described N-type epitaxy layer 102 surface successively deposit gate dielectric layer 108 and polysilicon gate 109, chemical wet etching is carried out to described polysilicon gate 109 and described gate dielectric layer 108 and forms grid structure, P trap 103 surface described in described grid structure cover part also extends transverse to described N-type implanted layer 105 surface and described field oxygen layer 107 on the surface, described P trap 103 surface that covers by described grid structure for the formation of raceway groove.Be preferably, described gate dielectric layer 108 is gate oxide.
As shown in fig. 41, the silicon dioxide of deposit one deck 2500 dust ~ 3500 dust, forms side wall 110 in the side of described polysilicon gate 109 after dry etching.
Step 8, as shown in fig. 4j, carry out N+ source and drain ion implantation and form source region 111a and drain region 111b, described source region 111a is arranged in described P trap 103, the first side autoregistration of described source region 111a and described grid structure; Described drain region 111b is arranged in described N trap 104, described drain region 111b and oxygen layer 107 autoregistration of described field; Carry out P+ ion implantation and form P type substrate draw-out area 112, described P type substrate draw-out area 112 is arranged in described P trap 103, for drawing described P trap 103.
The drift region of LDMOS device is made up of the described N-type implanted layer 105 between described N trap 104 and described P trap 103, described P type assisted depletion layer 106 and described N-type epitaxy layer 102; The doping content of described N-type implanted layer 105 is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer 106 for exhausting described N-type implanted layer 105, the junction depth of described P type assisted depletion layer 106 and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer 105 exhausts rear surface electric field smooth.
As shown in Figure 1, finally also comprise step: form interlayer film, form contact hole 113 by contact hole technique and connect; Formation top metal goes between, and described source region 111a, described drain region 111b, described P type substrate draw-out area 112 and described polysilicon gate 109 are connected respectively by contact hole 113 and top metal lead-in wire and realize the extraction of source electrode, drain electrode, P type substrate extraction electrode and grid respectively.
The manufacturing process of described LDMOS device is integrated in BCD technique, described P trap 103 in the manufacturing process of described LDMOS device is identical with P trap 103 technique of the cmos device in described BCD technique and synchronously formed, described N trap 104 in the manufacturing process of described LDMOS device is identical with N trap 104 technique of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ ion implantation of the described P type substrate draw-out area 112 in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
Embodiment of the present invention method utilizes original process conditions in BCD platform, when additionally not increasing reticle and when utilizing original injection condition, by means of only the litho pattern that adjusting device doping is injected, the assisted depletion region of uneven doping is increased in drift region, utilize territory, p type island region assisted depletion, change surface electric field distribution, while avoiding On current to increase, puncture voltage declines, under making device keep the prerequisite of better characteristic, puncture voltage remains unchanged.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. a LDMOS device, is characterized in that, comprising:
N-type epitaxy layer, is formed at P-type silicon substrate on the surface;
P trap, is formed in described N-type epitaxy layer;
N trap, is formed in described N-type epitaxy layer; Described N trap and described P trap are separated by a segment distance, are provided with a field oxygen layer between described N trap and described P trap, and the first side of described field oxygen layer and described P trap are separated by a segment distance, and the second side of described field oxygen layer extends to above described N trap;
N-type implanted layer, is formed in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, and N trap direction described in the second side direction of described N-type implanted layer extends and surrounded by described N trap;
P type assisted depletion layer, be formed at described N-type implanted layer surface and be positioned at the bottom of described field oxygen layer, the width of described P type assisted depletion layer is less than the bottom width of described field oxygen layer; First side of described P type assisted depletion layer near the second side of described P trap, described P type assisted depletion layer near described N trap, from the first side of described P type assisted depletion layer to the second side upwards, the junction depth of described P type assisted depletion layer reduces gradually, doping reduces gradually;
Grid structure, be made up of the gate dielectric layer and polysilicon gate that are formed at described N-type epitaxy layer surface, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove;
Source region, forms by being formed at described P trap Zhong N+ district, the first side autoregistration of described source region and described grid structure:
Drain region, forms by being formed at described N trap Zhong N+ district, described drain region and the oxygen layer autoregistration of described field;
P type substrate draw-out area, forms, for drawing described P trap by being formed at described P trap Zhong P+ district;
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer is used for exhausting described N-type implanted layer, the junction depth of described P type assisted depletion layer and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer exhausts rear surface electric field smooth.
2. LDMOS device as claimed in claim 1, is characterized in that: the implanted dopant of the ion implantation of described N-type implanted layer is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
3. LDMOS device as claimed in claim 1, it is characterized in that: described P type assisted depletion layer is combined after diffusion by a multiple P type ion implanted region separated by a distance, from the first side of described P type assisted depletion layer to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually, the implanted dopant of each described P type ion implanted region is boron, Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
4. a manufacture method for LDMOS device, is characterized in that, comprises the steps:
Step one, P-type silicon substrate surface formed N-type epitaxy layer;
Step 2, photoetching are opened P trap injection zone and are carried out P type ion implantation in this region and form P trap in described N-type epitaxy layer; Photoetching is opened N trap injection zone and is carried out N-type ion implantation in this region and form N trap in described N-type epitaxy layer, a segment distance of being separated by between described P trap and described N trap;
Step 3, photoetching are opened N-type implanted layer region and are carried out N-type ion implantation in this region and form N-type implanted layer in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, N trap direction described in the second side direction of described N-type implanted layer extends and is surrounded by described N trap;
Step 4, photoetching are opened the injection zone of the P type ion implanted region for forming P type assisted depletion layer and are carried out a P type ion implantation at this injection zone and form each described P type ion implanted region, first side of described P type assisted depletion layer near the second side of described P trap, described P type assisted depletion layer near described N trap, from the first side of described P type assisted depletion layer to the second side upwards, the width of each described P type ion implanted region reduces gradually, spacing increases gradually;
Step 5, to each described P type ion implanted region pick into, each described P type ion implanted region combines described P type assisted depletion layer through picking after diffusion, from the first side of described P type assisted depletion layer to the second side upwards, the junction depth of described P type assisted depletion layer reduces gradually, doping reduces gradually;
Step 6, deposit field oxygen layer chemical wet etching is carried out to described field oxygen layer, between described N trap and described P trap, a described field oxygen layer is provided with after etching, first side of described field oxygen layer and described P trap are separated by a segment distance, and the second side of described field oxygen layer extends to above described N trap;
Step 7, on described N-type epitaxy layer surface successively deposit gate dielectric layer and polysilicon gate, chemical wet etching is carried out to described polysilicon gate and described gate dielectric layer and forms grid structure, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove;
Step 8, carry out N+ source and drain ion implantation and form source region and drain region, described source region is arranged in described P trap, the first side autoregistration of described source region and described grid structure; Described drain region is arranged in described N trap, described drain region and the oxygen layer autoregistration of described field; Carry out P+ ion implantation and form P type substrate draw-out area, described P type substrate draw-out area is arranged in described P trap, for drawing described P trap;
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer is used for exhausting described N-type implanted layer, the junction depth of described P type assisted depletion layer and doping upwards reduce gradually from the first side to the second side to be arranged so that described N-type implanted layer exhausts rear surface electric field smooth.
5. method as claimed in claim 4, is characterized in that: the implanted dopant of the ion implantation of the implanted layer of N-type described in step 3 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
6. method as claimed in claim 4, is characterized in that: in step 4, the implanted dopant of each described P type ion implanted region is boron, and Implantation Energy is 50KeV ~ 500KeV, and implantation dosage scope is le11cm
-2~ le13cm
-2.
7. method as claimed in claim 4, is characterized in that: the resistivity of described P-type silicon substrate is 0.007 ohmcm ~ 0.013 ohmcm.
8. method as claimed in claim 4, it is characterized in that: the manufacturing process of described LDMOS device is integrated in BCD technique, described P trap in the manufacturing process of described LDMOS device is identical with the P trap technique of the cmos device in described BCD technique and synchronously formed, described N trap in the manufacturing process of described LDMOS device is identical with the N-well process of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ ion implantation of the described P type substrate draw-out area in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301975A (en) * | 2016-04-14 | 2017-10-27 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacture method |
| CN108122780A (en) * | 2018-01-12 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | Ldmos transistor and preparation method thereof |
| CN111540785A (en) * | 2020-05-13 | 2020-08-14 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacturing method thereof |
| CN112397568A (en) * | 2019-08-16 | 2021-02-23 | 天津大学 | High-voltage RESURF LDMOS device with N-type and P-type dual variable doping top layer regions |
| CN112397567A (en) * | 2019-08-16 | 2021-02-23 | 天津大学 | High-voltage RESURF LDMOS device with P-type transverse variable doping area |
| CN113690233A (en) * | 2021-09-22 | 2021-11-23 | 成都吉莱芯科技有限公司 | Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020030225A1 (en) * | 1999-06-30 | 2002-03-14 | Kazutoshi Nakamura | Field effect transistor |
| CN101546781A (en) * | 2008-03-27 | 2009-09-30 | 三洋电机株式会社 | Semiconductor device |
-
2013
- 2013-11-20 CN CN201310589117.3A patent/CN104659091A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020030225A1 (en) * | 1999-06-30 | 2002-03-14 | Kazutoshi Nakamura | Field effect transistor |
| CN101546781A (en) * | 2008-03-27 | 2009-09-30 | 三洋电机株式会社 | Semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301975A (en) * | 2016-04-14 | 2017-10-27 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacture method |
| CN107301975B (en) * | 2016-04-14 | 2020-06-26 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN108122780A (en) * | 2018-01-12 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | Ldmos transistor and preparation method thereof |
| CN112397568A (en) * | 2019-08-16 | 2021-02-23 | 天津大学 | High-voltage RESURF LDMOS device with N-type and P-type dual variable doping top layer regions |
| CN112397567A (en) * | 2019-08-16 | 2021-02-23 | 天津大学 | High-voltage RESURF LDMOS device with P-type transverse variable doping area |
| CN111540785A (en) * | 2020-05-13 | 2020-08-14 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacturing method thereof |
| CN113690233A (en) * | 2021-09-22 | 2021-11-23 | 成都吉莱芯科技有限公司 | Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof |
| CN113690233B (en) * | 2021-09-22 | 2024-03-08 | 江苏吉莱微电子股份有限公司 | Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof |
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