CN111540785A

CN111540785A - LDMOS device and manufacturing method thereof

Info

Publication number: CN111540785A
Application number: CN202010404899.9A
Authority: CN
Inventors: 许昭昭
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-05-13
Filing date: 2020-05-13
Publication date: 2020-08-14

Abstract

The application discloses an LDMOS device and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The LDMOS device comprises a substrate, a body region, a drift region, an insulating dielectric layer, a grid structure, a polycrystalline silicon field plate, a dielectric isolation layer and a metal layer; a first type heavily doped region and a second type heavily doped region are arranged in the body region, and the top of the body region and the bottom of the insulating medium layer are on the same horizontal plane; a second type heavily doped region is arranged in the drift region; the insulating medium layer is positioned above the drift region and is surrounded by the drift region, and the insulating medium layer comprises a step structure; the polysilicon field plate is positioned above the step structure of the insulating medium layer; the polysilicon gate extends to the upper part of the polysilicon field plate; the problem that the existing LDMOS device occupies a large chip area when large current transmission is realized is solved, the breakdown voltage of the device is not reduced when the size of the device is reduced, the linear current of the device is improved, and the on-resistance of the device is reduced.

Description

LDMOS device and manufacturing method thereof

Technical Field

The application relates to the field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof.

Background

DMOS (Double-Diffused MOSFET, Double-Diffused metal oxide semiconductor field effect transistor) is widely used in power management chips at present due to its characteristics of high voltage resistance, large current driving capability, and extremely low power consumption. DMOS are mainly of two types, LDMOS (Lateral Double-Diffused MOSFET) and VDMOS (Vertical Double-Diffused MOSFET). In the LDMOS device, breakdown voltage and on-resistance are important indexes for measuring the performance thereof, and the LDMOS device pursues high breakdown voltage and low on-resistance.

In a BCD (Bipolar-CMOS-DMOS) process, although LDMOS and CMOS are integrated in the same chip, the requirements of the application of a switch tube cannot be met due to the contradiction between high breakdown voltage and low characteristic on-resistance. In addition, in order to transmit a large current, the LDMOS generally needs to occupy a large chip area.

Disclosure of Invention

In order to solve the problems in the related art, the present application provides an LDMOS device and a method of manufacturing the same. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides an LDMOS device, which includes a substrate, a body region and a drift region located in the substrate, an insulating dielectric layer, a gate structure, a polysilicon field plate, a dielectric isolation layer located on the substrate, and a metal layer;

a first type heavily doped region and a second type heavily doped region are arranged in the body region, and the top of the body region and the bottom of the insulating medium layer are on the same horizontal plane;

a second type heavily doped region is arranged in the drift region;

the insulating medium layer is positioned above the drift region and is surrounded by the drift region, and the insulating medium layer comprises a step structure;

the polysilicon field plate is positioned above the step structure of the insulating medium layer;

the grid structure is positioned above one end of the body region and one end of the drift region and comprises a grid dielectric layer and a polysilicon grid, and the polysilicon grid extends above the polysilicon field plate;

after the first type heavily doped region and the second type heavily doped region in the body region are led out through a contact hole in the medium isolation layer, a source electrode of the LDMOS device is formed through short circuit of the metal layer;

after the polysilicon gate and the polysilicon field plate are led out through the contact hole in the medium isolation layer, the gate of the LDMOS device is formed by short circuit of a metal layer;

and the second type heavily doped region in the drift region is led out through a contact hole in the medium isolation layer and is connected with the metal layer to form a drain electrode of the LDMOS device.

Optionally, the insulating medium layer is a shallow trench isolation structure.

Optionally, the insulating dielectric layer is a local silicon oxide structure.

Optionally, the insulating dielectric layer includes at least 2 steps.

Optionally, the outer side of the polysilicon gate and the outer side of the polysilicon field plate are respectively provided with a side wall.

Optionally, the dielectric isolation layer includes a first dielectric layer, a second dielectric layer and an interlayer dielectric layer, the second dielectric layer is located below the interlayer dielectric layer, and the first dielectric layer is located below the second dielectric layer.

Optionally, the first dielectric layer is a silicon oxide layer;

the second dielectric layer is a silicon nitride layer;

the interlayer dielectric layer is a silicon oxide layer.

Optionally, an additional drift region located within the substrate;

the bottom of the additional drift region is higher than that of the drift region, the additional drift region surrounds an accumulation region, and the accumulation region is a region, which is overlapped with the gate structure, of a region, which is not covered by the insulating medium layer, in the drift region.

Optionally, a CMOS device is further fabricated on the substrate, and the CMOS device includes a well region disposed in the substrate, a CMOS device gate structure disposed on the surface of the substrate, and a source region and a drain region disposed in the well region;

and the grid electrode, the source region and the drain region of the CMOS device are respectively led out through the contact holes in the medium isolation layer and are connected with the metal layer.

Optionally, the substrate is P-type or N-type.

In a second aspect, an embodiment of the present application provides a method for manufacturing an LDMOS device, where the method includes:

forming an insulating medium layer in the substrate;

forming a drift region of the LDMOS device in the substrate, wherein the insulating medium layer is positioned above the drift region;

etching the insulating medium layer to form a step structure, forming a polysilicon field plate above the step structure, and surrounding the etched insulating medium layer by the drift region;

forming a grid structure of the LDMOS device, wherein the grid structure of the LDMOS device comprises a grid oxide layer and a polysilicon grid, and the polysilicon grid extends to the upper part of the polysilicon field plate;

forming a body region of the LDMOS device in the substrate, wherein the body region is adjacent to the drift region, and the top of the body region and the bottom of the insulating medium layer are on the same horizontal plane;

forming a first type heavily doped region and a second type heavily doped region in a body region of the LDMOS device, and forming a second type heavily doped region in a drift region of the LDMOS device;

forming a dielectric isolation layer, and forming contact holes in the dielectric isolation layer, wherein the contact holes correspond to a polysilicon gate of the LDMOS device, a polysilicon field plate, a first type heavily doped region and a second type heavily doped region in the substrate;

and leading out a grid electrode, a source electrode and a drain electrode of the LDMOS device through the filled contact hole and the metal layer above the dielectric isolation layer.

Optionally, etching the insulating dielectric layer to form a step structure, and forming a polysilicon field plate above the step structure, including:

depositing a first polysilicon layer;

depositing a hard mask layer;

etching the hard mask layer, wherein the etched hard mask layer covers a part of the drift region;

etching the first polysilicon layer by using the etched hard mask layer as a mask;

and etching the insulating dielectric layer and the deposited polycrystalline silicon layer in a grading manner according to the number of steps in the step structure to form the insulating dielectric layer comprising the step structure and the polycrystalline silicon field plate positioned above the step structure.

Optionally, when the number of the steps is 2, the insulating dielectric layer and the deposited polysilicon layer are etched in a graded manner according to the number of the steps in the step structure, so as to form an insulating dielectric layer including the step structure and a polysilicon field plate located above the step structure, including:

etching the insulating medium layer by taking the hard mask layer as a mask to form a first step of the insulating medium layer, wherein the etching thickness is 1/2 of the thickness of the insulating medium layer;

depositing a second polysilicon layer;

etching the second polycrystalline silicon layer, wherein the etched second polycrystalline silicon layer is positioned above the first step of the insulating medium layer;

etching the insulating medium layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating medium layer, wherein the etching thickness is 1/2 of the thickness of the insulating medium layer;

the first polycrystalline silicon layer and the second polycrystalline silicon layer jointly form a polycrystalline silicon field plate of the LDMOS device.

Optionally, the insulating dielectric layer and the deposited polysilicon layer are etched in a graded manner according to the number of steps in the step structure to form an insulating dielectric layer including the step structure and a polysilicon field plate located above the step structure, including:

etching the insulating medium layer by taking the hard mask layer as a mask to form a first step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer;

depositing a second polysilicon layer;

etching the insulating medium layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating medium layer, wherein the etching thickness is 1/3 of the insulating medium layer;

depositing a third polysilicon layer;

etching the third polycrystalline silicon layer, wherein the etched third polycrystalline silicon layer is positioned above the second step of the insulating medium layer;

etching the insulating medium layer by taking the hard mask layer, the second polycrystalline silicon layer and the third polycrystalline silicon layer as masks to form a third step of the insulating medium layer, wherein the etching thickness is 1/3 the thickness of the insulating medium layer;

the first polysilicon layer, the second polysilicon layer and the third polysilicon layer jointly form a polysilicon field plate of the LDMOS device.

Optionally, the insulating dielectric layer is a local silicon oxide structure.

Optionally, before forming the gate structure of the LDMOS device, the method further includes:

and forming an additional drift region in the substrate, wherein the bottom of the additional drift region is higher than that of the drift region, the additional drift region is used for surrounding an accumulation region, and the accumulation region is a region, which is overlapped with a gate structure of the LDMOS device, of a region, which is not covered by the insulating dielectric layer, in the drift region.

Optionally, the forming of the polysilicon gate structure of the LDMOS device includes:

forming a gate dielectric layer of the LDMOS device;

depositing a grid polycrystalline silicon layer of the LDMOS device;

defining a body region of the LDMOS device through a photoetching process;

and etching the grid polysilicon layer of the LDMOS device, and performing CMP to form the polysilicon grid of the LDMOS device.

Optionally, forming a dielectric isolation layer includes:

and depositing a first dielectric layer, a second dielectric layer and an interlayer dielectric layer in sequence.

Optionally, the first dielectric layer is a silicon oxide layer, the second dielectric layer is a silicon nitride layer, and the interlayer dielectric layer is a silicon oxide layer.

Optionally, forming a drift region of the LDMOS device in the substrate includes:

a drift region of the LDMOS device is formed in the substrate, and a well region of the CMOS device is formed in a CMOS region in the substrate.

Optionally, before forming the first heavily doped region in the drift region of the LDMOS device and forming the first heavily doped region and the second heavily doped region in the body region of the LDMOS device, the method further includes:

removing the hard mask layer above the first polysilicon layer;

defining a grid electrode area of the CMOS device through a photoetching process, etching a first polysilicon layer according to the grid electrode area of the CMOS device, and forming a grid electrode of the CMOS device above a well region of the CMOS device;

carrying out lightly doped drain injection of the CMOS device;

and forming the side wall of the LDMOS device and the side wall of the CMOS device.

Optionally, the method further includes:

forming a second type heavily doped region in a well region of the CMOS device;

and leading out the source electrode and the drain electrode of the CMOS device through the contact hole in the medium isolation layer and the metal layer above the medium isolation layer.

Optionally, the substrate is P-type or N-type.

The technical scheme at least comprises the following advantages:

the LDMOS device provided by the embodiment of the application has the advantages that the channel, the bottom of the insulating medium layer and the silicon interface are positioned on the same horizontal plane, the minimum conduction current path of the LDMOS device is shortened, the size of the accumulation region of the LDMOS device is favorably shortened, the area of a chip is reduced, the breakdown voltage of the device is not reduced when the size of the device is reduced, the linear current of the device is improved, and the conduction resistance of the device is reduced.

In addition, the insulating medium layer comprises a step structure, the polycrystalline silicon field plate is positioned above the step structure of the insulating medium layer, and the polycrystalline silicon field plate is provided with a plurality of field oxide thicknesses, so that the transverse electric field distribution of the LDMOS device is further optimized, and the relationship between the breakdown voltage and the on-resistance is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a conventional LDMOS device;

fig. 2 is a schematic structural diagram of an LDMOS device provided in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another LDMOS device provided in the embodiments of the present application;

FIG. 4 is a schematic structural diagram of another LDMOS device provided in the embodiments of the present application;

FIG. 5 is a schematic structural diagram of another LDMOS device provided in the embodiments of the present application;

fig. 6 is a schematic structural diagram of an LDMOS device and a CMOS device provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of the linear region currents of the LDMOS device of FIG. 2 and the LDMOS device of FIG. 1;

FIG. 8 is a schematic diagram of breakdown voltages of the LDMOS device of FIG. 2 and the LDMOS device of FIG. 1;

fig. 9 is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of the present disclosure;

fig. 10 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 11 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 12 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 13 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 14 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 15 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 16 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 17 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 18 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 19 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 20 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 21 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 22 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

fig. 23 is an implementation schematic diagram of a method for manufacturing an LDMOS device according to an embodiment of the present application;

wherein: 101, a P-type substrate; 102, a drift region; 103, a P-type body region; 104, a P-type heavily doped region; 105, an N-type heavily doped region; 106, a gate oxide layer; 107, a field oxide layer; 108, polysilicon gate; 109, side walls; 113, a contact hole; 114, a metal layer;

11, a substrate; 12, a body region; 13, a drift region; 14, an insulating medium layer; 15, a dielectric isolation layer; 16, a metal layer; 17, a first type heavily doped region; 18, a second type heavily doped region; 19, a polysilicon field plate; 20, a gate dielectric layer; 21, polysilicon gate; 22, a contact hole; 23, side walls; 24, an additional drift region; 141, a first dielectric layer; 142, a second dielectric layer; 143, interlayer dielectric layer; 25, polysilicon gate of CMOS device; 26, source region of CMOS device; 27, a drain region of the CMOS device; 28, well region of CMOS device;

210, a gate oxide layer; 211, a first polysilicon layer; 212, a hard mask layer; 213, a second polysilicon layer; 214; 215, photoresist; 216 a photoresist; s2, the shortest on current path indicates an arrow.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 shows a cross-sectional structure of a conventional LDMOS device. Taking the LDMOS device as an NLDMOS device as an example, a drift region 102, a P-type body region 103 are arranged in a P-type substrate 101, a field oxide layer 107 is arranged in the drift region 102, a P-type heavily doped region 104 and an N-type heavily doped region 105 are arranged in the P-type body region 103, an N-type heavily doped region 105 is arranged in the drift region 102, and a gate structure of the LDMOS device comprises a gate oxide layer 106, a polysilicon gate 108 and a side wall 109; the P-type heavily doped region 104 and the N-type heavily doped region 105 are led out through corresponding contact holes 113 and connected with a metal layer 114 to form a source electrode of the LDMOS device; the N-type heavily doped region 105 is led out through the corresponding contact hole 113 and connected with the metal layer 114 to form the drain of the LDMOS device.

In the LDMOS device shown in fig. 1, arrow S1 shows the shortest on-current path, and in order to reduce the on-resistance of the LDMOS device, the size of the accumulation region of the device needs to be increased, resulting in a larger chip area occupied by the LDMOS device. The accumulation region is an overlapping region of the field-free oxide layer region in the drift region 102 and the gate structure.

The present embodiment provides an LDMOS device, as shown in fig. 2, which includes a substrate 11, a body region 12 and a drift region 13 located in the substrate 11, an insulating dielectric layer 14, a gate structure, a dielectric isolation layer 15 and a metal layer 16 located on the substrate, and a polysilicon field plate 19.

A first type heavily doped region 17 and a second type heavily doped region 18 are arranged in the body region 12, and the top of the body region 12 and the bottom of the insulating medium layer 14 are on the same horizontal plane.

A second type heavily doped region 18 is disposed in the drift region 13.

The first type heavily doped region 17 and the second type heavily doped region 18 have different doping types, for example, when the substrate is a P-type substrate, the first type heavily doped region is P-type and the second type heavily doped region is N-type, or when the substrate is N-type, the first type heavily doped region is N-type and the second type heavily doped region is P-type.

An insulating dielectric layer 14 is located above the drift region 13 and is surrounded by the drift region 13, the insulating dielectric layer 14 including a step structure.

The polysilicon field plate 19 is located above the step structure of the insulating dielectric layer 14.

A gate structure is located over one end of the body region 12 and one end of the drift region 13, the gate structure including a gate dielectric layer 20 and a polysilicon gate 21, the polysilicon gate 21 extending over the polysilicon field plate 19.

Optionally, the gate dielectric layer is a gate oxide layer.

After the first type heavily doped region 17 and the second type heavily doped region 18 in the body region 12 are respectively led out through the contact hole 22 in the dielectric isolation layer 15, the source electrode of the LDMOS device is formed by short circuit through the metal layer 16.

A metal layer 16 is located over the dielectric isolation layer 15.

The polysilicon gate 21 and the polysilicon field plate 19 are respectively led out through the contact hole 22 in the dielectric isolation layer 15, and then are shorted through the metal layer 16 to form the gate of the LDMOS device.

The second type heavily doped region 18 in the drift region 13 is led out through the contact hole 22 in the dielectric isolation layer 15 and is connected with the metal layer 16 to form the drain of the LDMOS device.

As can be seen from fig. 2, the channel, the bottom of the insulating dielectric layer, and the silicon interface of the LDMOS device are located on the same horizontal plane, and arrow S2 shows that the shortest on-current path is linear, which shortens the minimum on-current path of the LDMOS device, and is beneficial to shortening the size of the accumulation region of the LDMOS device and reducing the chip area.

To sum up, the LDMOS device provided by the embodiment of the application solves the problem that the existing LDMOS device occupies a large chip area when realizing large-current transmission, achieves the effects of not reducing the breakdown voltage of the device when reducing the size of the device, improving the linear current of the device and reducing the on-resistance of the device.

In an alternative embodiment of the present application, the insulating dielectric layer is a shallow trench structure.

Taking the LDMOS device shown in fig. 2 as an example, the insulating dielectric layer 14 is a shallow trench isolation structure.

In an alternative embodiment of the present application, the insulating dielectric layer is a local silicon oxide structure.

As shown in fig. 3, the insulating dielectric layer 14 is a local silicon oxide structure.

It should be noted that the LDMOS device structure shown in fig. 2 and 3 is only an exemplary structure.

In an alternative embodiment of the present application, the insulating dielectric layer comprises at least 2 steps.

Taking fig. 2 as an example, there are 3 steps from the bottom to the top of the insulating dielectric layer 14.

Taking fig. 3 as an example, there are 2 steps from the bottom to the top of the insulating dielectric layer 14.

The structure of the LDMOS device shown in fig. 2 and 3 does not limit the number of steps in the insulating dielectric layer, the number of steps in the insulating dielectric layer of the LDMOS device is determined according to practical situations, and the invention does not limit this.

In one example, the insulating dielectric layer 14 of the shallow trench isolation structure may also include 2 steps, as shown in fig. 4. In another example, the insulating dielectric layer 14 of the local silicon oxide structure may also include 3 steps, as shown in fig. 5.

In an alternative embodiment of the present application, the outer side of the polysilicon gate and the outer side of the polysilicon field plate are respectively provided with a sidewall.

Taking fig. 2 or fig. 3 as an example, the outer side of the polysilicon gate 21 and the outer side of the polysilicon field plate 19 are respectively provided with a sidewall 23.

Optionally, an oxide layer is arranged between the side wall and the polysilicon gate, and an oxide layer is arranged between the side wall and the polysilicon field plate.

In an alternative embodiment of the present application, the dielectric isolation layer includes a first dielectric layer, a second dielectric layer and an interlayer dielectric layer, the second dielectric layer is located below the interlayer dielectric layer, and the first dielectric layer is located below the second dielectric layer.

Optionally, the first dielectric layer is a silicon oxide layer, the second dielectric layer is a silicon nitride layer, and the interlayer dielectric layer is an oxide layer.

In an alternative embodiment of the present application, the LDMOS device further comprises an additional drift region located within the substrate, the bottom of the additional drift region being higher than the bottom of the drift region, the additional drift region surrounding the accumulation region.

The accumulation region is a region of the drift region, which is not covered by the insulating dielectric layer, and is overlapped with the gate structure.

As shown in fig. 4 or fig. 5, an additional drift region 24 is further disposed in the substrate 11, the bottom of the additional drift region 24 is higher than the bottom of the drift region 13, a region of the drift region 13, which is not covered by the insulating dielectric layer 14, overlapping the gate structure is an accumulation region of the LDMOS device, and the additional drift region 24 surrounds the accumulation region.

The additional drift region helps to optimize the relationship between the breakdown voltage and the on-resistance of the LDMOS device.

In an alternative embodiment of the present application, a CMOS device is further fabricated on the substrate, and the LDMOS device and the CMOS device are integrated on the same chip.

As shown in fig. 6, the CMOS device includes a well region 28 disposed within the substrate 11, a CMOS device gate structure disposed at the substrate surface, and source and drain

regions

26 and 27 disposed within the well region 28.

The gate structure of the CMOS device comprises a polysilicon gate 25 and a side wall 23 of the CMOS device, and a gate oxide layer is arranged below the polysilicon gate 25 of the CMOS device.

The polysilicon gate 25, the source region 26 and the drain region 27 in the gate structure of the CMOS device are led out through the contact hole 22 in the dielectric isolation layer and connected with the metal layer 16.

As shown in fig. 6, the dielectric isolation layer includes a first dielectric layer 141, a second dielectric layer 142 and an interlayer dielectric layer 143, the second dielectric layer 142 is located below the interlayer dielectric layer 143, and the first dielectric layer 141 is located below the second dielectric layer 142.

In alternative embodiments of the present application, the substrate is P-type or N-type.

Taking the LDMOS device structure shown in fig. 2 and the LDMOS device structure shown in fig. 1 as examples, simulations were performed to obtain the linear region current schematic diagram shown in fig. 7 and the breakdown voltage schematic diagram shown in fig. 8, where a curve 71 in fig. 7 corresponds to the LDMOS device shown in fig. 2 and a curve 72 corresponds to the LDMOS device shown in fig. 1; in fig. 8 curve 81 corresponds to the LDMOS device shown in fig. 2 and curve 82 corresponds to the LDMOS device shown in fig. 1.

As can be seen from fig. 7 and 8, by using the LDMOS device provided by the embodiment of the present application, the linear current can be increased under the condition of ensuring the same breakdown voltage; in this example, the linear current of the LDMOS device increased by 11.2% and the on-resistance decreased by 17.3%.

Referring to fig. 9, an embodiment of the present application provides a flowchart of a method for manufacturing an LDMOS device, where the method for manufacturing the LDMOS device at least includes the following steps:

step 901, forming an insulating dielectric layer in a substrate.

A substrate is provided, and an insulating dielectric layer is formed in the substrate.

And 902, forming a drift region of the LDMOS device in the substrate, wherein the insulating medium layer is positioned above the drift region.

And step 903, etching the insulating dielectric layer to form a step structure, forming a polysilicon field plate above the step structure, and surrounding the etched insulating dielectric layer by the drift region.

Optionally, the etched insulating dielectric layer at least includes 2 steps.

And 904, forming a grid electrode structure of the LDMOS device, wherein the grid electrode structure of the LDMOS device comprises a grid oxide layer and a polysilicon grid, and the polysilicon grid extends to the upper part of the polysilicon field plate.

A gate oxide layer is arranged below the polysilicon gate, and a substrate is arranged below the gate oxide layer.

Step 905, forming a body region of the LDMOS device in the substrate, wherein the body region is adjacent to the drift region, and the top of the body region and the bottom of the insulating dielectric layer are on the same horizontal plane.

And carrying out ion implantation according to the body region defined by the photoetching process, and forming the body region of the LDMOS device in the substrate.

One end of the body region and one end of the drift region are located below the gate structure of the LDMOS device.

Step 906, forming a first type heavily doped region and a second type heavily doped region in the body region of the LDMOS device, and forming a second type heavily doped region in the drift region of the LDMOS device.

Step 907, forming a dielectric isolation layer, and forming contact holes in the dielectric isolation layer, wherein the contact holes correspond to the polysilicon gate of the LDMOS device, the polysilicon field plate, the first heavily doped region and the second heavily doped region in the substrate.

The first type heavily doped region and the second type heavily doped region are of different types.

And forming a contact hole in the medium isolation layer through a photoetching process and an etching process.

And 908, leading out the grid electrode, the source electrode and the drain electrode of the LDMOS device through the filled contact hole and the metal layer above the dielectric isolation layer.

And filling the contact hole in the medium isolation layer with metal, and forming a metal layer on the surface of the medium isolation layer.

And after the first type heavily doped region and the second type heavily doped region in the body region are respectively led out through the contact holes, the first type heavily doped region and the second type heavily doped region are connected through the metal layer to form a source electrode of the LDMOS device. And after the polysilicon gate and the polysilicon field plate are respectively led out through the contact holes, the polysilicon gate and the polysilicon field plate are connected through the metal layer to form a gate of the LDMOS device. And the second type heavily doped region in the drift region is connected with the metal layer through the contact hole and is led out to form the drain electrode of the LDMOS device.

The LDMOS device obtained by the manufacturing method of the LDMOS device provided by the embodiment of the application takes the FIG. 2 or the FIG. 3 as an example, the channel of the LDMOS device, the bottom of the insulating medium layer and the silicon interface are positioned on the same horizontal plane, so that the minimum conduction current path of the LDMOS device is shortened, the size of the accumulation region of the LDMOS device is favorably shortened, and the chip area is reduced.

In summary, in the method for manufacturing the LDMOS device provided by the embodiment of the present application, the insulating dielectric layer is formed in the substrate, the drift region of the LDMOS device is formed in the substrate, the insulating dielectric layer is located above the drift region, the insulating dielectric layer is etched to form the step structure, the polysilicon field plate is formed on the step structure, the etched insulating dielectric layer is surrounded by the drift region to form the gate structure, the body region and the heavily doped region of the LDMOS device, the dielectric isolation layer is formed, and the gate, the source and the drain of the LDMOS device are led out through the contact hole; the problem that the existing LDMOS device occupies a large chip area when large current transmission is realized is solved, the breakdown voltage of the device is not reduced when the size of the device is reduced, the linear current of the device is improved, and the on-resistance of the device is reduced.

In an alternative embodiment to the embodiment shown in fig. 9, the insulating dielectric layer is a shallow trench structure.

In an alternative embodiment to the embodiment shown in fig. 9, the insulating dielectric layer is a local silicon oxide structure.

In an alternative embodiment based on the embodiment shown in fig. 9, the substrate is either N-type or P-type. When the substrate is a P-type substrate, the first type heavily doped region is P-type, and the second type heavily doped region is N-type; when the substrate is N-type, the first heavily doped region is N-type, and the second heavily doped region is P-type.

In an alternative embodiment based on the embodiment shown in fig. 9, in order to better optimize the relation between the breakdown voltage and the on-resistance of the LDMOS device, an additional drift region is also formed within the substrate, i.e. the method of manufacturing the LDMOS device further comprises step 904a before step 904 described above.

Step 904a forms an additional drift region within the substrate, the bottom of the additional drift region being higher than the bottom of the drift region.

The additional drift region is used for surrounding an accumulation region, and the accumulation region is a region, which is overlapped with a gate structure of the LDMOS device, of a region, which is not covered by the insulating dielectric layer, in the drift region.

Optionally, an additional drift region is formed in the substrate by an ion implantation process.

Taking fig. 4 or fig. 5 as an example, an additional drift region 24 is formed in the substrate 11.

In an alternative embodiment based on the embodiment shown in fig. 9, the step "etching the insulating dielectric layer to form a step structure, and forming a polysilicon field plate above the step structure, where the etched insulating dielectric layer is surrounded by the drift region" is performed in step 903, which may be implemented by:

step 9031, a first polysilicon layer is deposited.

Step 9032, a hard mask layer is deposited.

Step 9033, the hard mask layer is etched, and the etched hard mask layer covers a part of the drift region.

Defining the hard mask layer region to be removed through a photoetching process, etching the hard mask layer which is not covered by the photoresist, and covering a part of the drift region by the etched hard mask layer.

And 9034, etching the first polysilicon layer by using the etched hard mask layer as a mask.

And removing the photoresist, and etching the first polycrystalline silicon layer by taking the etched hard mask layer as a mask, wherein the etched first polycrystalline silicon layer also covers a part of the drift region.

Step 9035, etching the insulating dielectric layer and the deposited polycrystalline silicon layer in a graded manner according to the number of steps in the step structure, and forming an insulating dielectric layer comprising a step structure and a polycrystalline silicon field plate located above the step structure.

The etched insulating medium layer is surrounded by the drift region.

And if the step structure comprises n steps, etching the insulating medium layer for n times, wherein the thickness of etching the insulating medium layer every time is 1/n, and a step is formed every time. n is an integer, n is greater than or equal to 2.

Aiming at the first n-1 times of etching of the insulating medium layer, after each time of etching, depositing a layer of polycrystalline silicon and etching the deposited polycrystalline silicon layer, wherein the etched polycrystalline silicon layer covers the step formed on the insulating medium layer, and the etched polycrystalline silicon layer is positioned above the insulating medium layer.

When the first type heavily doped region and the second type heavily doped region are formed in the subsequent step, the first polycrystalline silicon layer above the region for forming the second type heavily doped region is etched and removed; the etched first polycrystalline silicon layer and the polycrystalline silicon layer above the step structure in the insulating medium layer jointly form a polycrystalline silicon field plate of the LDMOS device.

Taking the number of steps in the insulating dielectric layer as 2 as an example, the step 9035 is specifically realized by the following steps:

step 9035a, the insulating medium layer is etched by taking the hard mask layer as a mask to form a first step of the insulating medium layer, and the etching thickness is 1/2 equal to the thickness of the insulating medium layer.

Step 9035b, a second polysilicon layer is deposited.

And 9035c, etching the second polycrystalline silicon layer, wherein the etched second polycrystalline silicon layer is located above the first step of the insulating medium layer.

And 9035d, etching the insulating medium layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating medium layer, wherein the etching thickness is 1/2 equal to the thickness of the insulating medium layer.

At this time, the etched insulating dielectric layer is as shown in fig. 3 or fig. 4 as the insulating dielectric layer 14, and the first polysilicon layer and the second polysilicon layer together form a polysilicon field plate of the LDMOS device.

Taking the number of steps in the insulating medium layer as 3 as an example, the step 9035 is specifically realized by the following steps:

and 90351, etching the insulating medium layer by taking the hard mask layer as a mask to form a first step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer.

At step 90352, a second polysilicon layer is deposited.

And 90353, etching the second polysilicon layer, wherein the etched second polysilicon layer is located above the first step of the insulating medium layer.

And 90354, etching the insulating medium layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer.

Step 90355 deposits a third polysilicon layer.

And 90356, etching the third polysilicon layer, wherein the etched third polysilicon layer is located above the second step of the insulating medium layer.

And 90357, etching the insulating medium layer by taking the hard mask layer, the second polycrystalline silicon layer and the third polycrystalline silicon layer as masks to form a third step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer.

At this time, the etched insulating dielectric layer is as shown in fig. 2 or fig. 5 as the insulating dielectric layer 14, and the first polysilicon layer, the second polysilicon layer and the third polysilicon layer together form a polysilicon field plate of the LDMOS device.

In an alternative embodiment based on the embodiment shown in fig. 9, "forming the gate structure of the LDMOS", i.e., step 904 can be implemented by:

and step 9041, forming a gate oxide layer of the LDMOS device.

The gate oxide layer of the LDMOS device is positioned above the substrate.

Step 9042, a gate polysilicon layer of the LDMOS device is deposited.

The grid polycrystalline silicon layer is used for forming a polycrystalline silicon grid of the LDMOS device.

The deposited gate polysilicon layer covers the polysilicon field plate of the LDMOS device.

In step 9043, a body region of the LDMOS device is defined by a photolithography process.

And 9044, etching the grid polysilicon layer of the LDMOS device, and performing CMP to form the polysilicon grid structure of the LDMOS device.

And etching the grid polycrystalline silicon layer of the LDMOS device according to the defined body region of the LDMOS device, and removing the grid polycrystalline silicon layer corresponding to the body region.

Then, CMP (Chemical-Mechanical Planarization) is performed, and the top of the polysilicon gate and the top of the polysilicon field plate are on the same level after the CMP.

In an alternative embodiment based on the embodiment shown in fig. 9, "forming a dielectric isolation layer" may be achieved by:

step 9071, a first dielectric layer, a second dielectric layer and an interlayer dielectric layer are sequentially deposited.

The first dielectric layer is positioned below the second dielectric layer, and the second dielectric layer is positioned below the interlayer dielectric layer.

In an alternative embodiment based on the embodiment shown in fig. 9, a CMOS device may also be fabricated simultaneously when the LDMOS device is fabricated. A drift region of the LDMOS device is formed in the substrate, and a well region of the CMOS device is formed in a CMOS region in the substrate. After the well region of the CMOS device is formed, a gate oxide layer is deposited on the substrate, and the gate oxide layer is used as a gate oxide layer of the CMOS device.

In an alternative embodiment based on the embodiment shown in fig. 9, a CMOS device may also be fabricated simultaneously when the LDMOS device is fabricated. After the body region of the LDMOS device is formed and before the first heavily doped region and the second heavily doped region of the LDMOS device are formed, the gate structure of the CMOS device is formed, that is, between step 905 and step 906, the following steps may be further included:

step 9051, the hard mask layer above the first polysilicon layer is removed.

After the polysilicon gate of the LDMOS device, a hard mask layer is also present above the first polysilicon layer, and the hard mask layer needs to be removed.

9052, defining a gate region of the CMOS device through a photolithography process, etching the first polysilicon layer according to the gate region of the CMOS device, and forming a gate of the CMOS device above the well region of the CMOS device.

Covering a photoresist in an area which does not need to be etched by a photoetching process, etching a first polysilicon layer by an etching process to form a grid electrode of the CMOS device above a well region of the CMOS device, wherein the grid electrode area of the CMOS device is not covered by the photoresist; and removing the photoresist on the substrate.

Step 9053, lightly doped drain implantation of the CMOS device is performed.

Optionally, forming a sidewall oxide layer on the outer sides of the polysilicon gate of the LDMOS device and the gate of the CMOS device by using a conventional oxidation process; and then carrying out lightly doped drain implantation of the CMOS device.

And 9054, forming a side wall of the LDMOS device and a side wall of the CMOS device.

In an alternative embodiment based on the embodiment shown in fig. 9, a CMOS device may also be fabricated simultaneously when the LDMOS device is fabricated. When a first type heavily doped region and a second type heavily doped region are formed in the body region of the LDMOS device and a second type heavily doped region is formed in the drift region of the LDMOS device, the second type heavily doped region is formed in the well region of the CMOS device. And leading out the source electrode and the drain electrode of the CMOS device through the contact hole in the medium isolation layer and the metal layer above the medium isolation layer.

In one example, an LDMOS device and a CMOS device are fabricated on the same substrate, an insulating dielectric layer in the LDMOS device includes 3 steps, and an additional drift region is provided in the LDMOS device, and the method for fabricating the LDMOS device provided in the embodiment of the present application may include the following steps:

step 1001, an insulating dielectric layer is formed within the substrate.

As shown in fig. 10, an insulating dielectric layer 14 of a shallow trench isolation structure is formed in a substrate 11.

It should be noted that the insulating dielectric layer is a shallow trench isolation structure or a local field oxide structure, and in this embodiment, the insulating dielectric layer is taken as a shallow trench isolation structure for illustration, and the structure of the insulating dielectric layer is not limited.

Step 1002, forming a drift region of the LDMOS device in the substrate, forming a well region of the CMOS device in the CMOS region in the substrate, and positioning the insulating medium layer above the drift region.

And defining a region corresponding to the drift region of the LDMOS device and a region corresponding to the well region of the CMOS device through a photoetching process, and performing an ion implantation process to form the drift region of the LDMOS device and the well region of the CMOS device.

As shown in fig. 11, a drift region 13 of the LDMOS device and a well region 28 of the CMOS device are formed in the substrate 11.

Step 1003, forming a gate oxide layer on the substrate.

Optionally, a gate oxide layer is formed by a thermal oxidation process, and the gate oxide layer is used as a gate oxide layer of the CMOS device.

At step 1004, a first polysilicon layer is deposited.

Step 1005, a hard mask layer is deposited.

As shown in fig. 12, a gate oxide layer 210, a first polysilicon layer 211, and a hard mask layer 212 are sequentially formed on a substrate 11.

Step 1006, the hard mask layer is etched, and the etched hard mask layer covers a part of the drift region.

As shown in fig. 13, the hard mask layer 212 is etched away in part.

Step 1007, etching the first polysilicon layer by using the etched hard mask layer as a mask.

As shown in fig. 14, the first polysilicon layer 211 is etched.

Step 1008, the insulating dielectric layer is etched by using the hard mask layer as a mask to form a first step of the insulating dielectric layer, and the etching thickness is 1/3 the thickness of the insulating dielectric layer.

As shown in fig. 15, after the insulating dielectric layer 14 is etched for the first time, a first step is formed.

Step 1009, a second polysilicon layer is deposited.

As shown in fig. 16, a second polysilicon layer 213 is deposited on the substrate 11.

Step 1010, etching the second polysilicon layer, wherein the etched second polysilicon layer is located above the first step of the insulating dielectric layer.

And step 1011, etching the insulating dielectric layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating dielectric layer, wherein the etching thickness is 1/3 of the insulating dielectric layer.

As shown in fig. 17, the etched second polysilicon layer 213 is located above the first step of the insulating dielectric layer 14, and the second polysilicon layer 213 covers the first step of the insulating dielectric layer 14; and etching the insulating dielectric layer 14 for the second time by using the second polysilicon layer 213 and the hard mask layer 212 as masks to obtain a second step of the insulating dielectric layer 14.

Step 1012, a third polysilicon layer is deposited.

And 1013, etching the third polysilicon layer, wherein the etched third polysilicon layer is positioned above the second step of the insulating medium layer.

The etched third polysilicon layer is positioned above the second step of the insulating medium layer and covers the second step of the insulating medium layer.

And 1014, etching the insulating medium layer by taking the hard mask layer, the second polycrystalline silicon layer and the third polycrystalline silicon layer as masks to form a third step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer.

As shown in fig. 18, the insulating dielectric layer 14 includes 3 steps, the etched insulating dielectric layer 14 is surrounded by the drift region 13, and the silicon surface under the insulating dielectric layer 14 is exposed.

The first polysilicon layer, the second polysilicon layer and the third polysilicon layer together form a polysilicon field plate 19 of the LDMOS device.

An additional drift region is formed in the substrate, with a bottom of the additional drift region being higher than a bottom of the drift region, step 1015.

The additional drift region surrounds an accumulation region, and the accumulation region is a region, which is overlapped with a gate structure of the LDMOS device, of a region, which is not covered by the insulating dielectric layer, in the drift region.

A low energy drift region is added once to the accumulation region to form an additional drift region 24 as shown in figure 19.

In one example, the process parameters for forming the additional drift region are: implanting phosphorus ions at 40-100 KeV, 1e 12-1 e13 cm^-2。

And step 1016, forming a gate dielectric layer of the LDMOS device.

Optionally, the gate dielectric layer is a gate oxide layer; the gate oxide layer is formed by a deposition or thermal oxidation process.

Step 1017, a grid polycrystalline silicon layer of the LDMOS device is deposited.

In step 1018, a body region of the LDMOS device is defined by a photolithography process.

The part of the LDMOS device outside the body region is covered by the photoresist.

Step 1019, etching the grid polysilicon layer of the LDMOS device according to the body region of the LDMOS device, and forming the body region of the LDMOS device through an ion implantation process.

As shown in fig. 20, a gate polysilicon layer 214 is over the substrate 11; covering the part which does not need to be etched by the photoresist 215, etching the gate polysilicon layer 214 by taking the photoresist 215 as a mask, and then carrying out an ion implantation process to form the body region 12 of the LDMOS device in the substrate 11.

Step 1020, removing the photoresist, and performing CMP on the hard mask layer 212 as a reference to form a polysilicon gate of the LDMOS device.

As shown in fig. 21, after the CMP process, the polysilicon gate 21 of the LDMOS device is formed, the top of the polysilicon gate 21 and the top of the polysilicon field plate 19 are on the same horizontal plane, the thickness of the polysilicon field plate 19 is reduced, and the hard mask layer 212 remains above the first polysilicon layer 211.

Step 1021, removing the hard mask layer above the first polysilicon layer.

Optionally, the hard mask layer above the first polysilicon layer is removed by a wet etching process.

And 1022, defining a gate region of the CMOS device through a photolithography process, etching the first polysilicon layer according to the gate region of the CMOS device, and forming a gate of the CMOS device above the well region of the CMOS device.

As shown in fig. 22, the gate region of the CMOS device is defined by a photolithography process, and the portion to be etched does not cover the photoresist, and the portion not to be etched covers the photoresist 216. And etching the first polysilicon layer according to the defined gate region of the CMOS device to obtain the polysilicon gate 25 of the CMOS device.

As shown in fig. 22, the etched first polysilicon layer is part of the polysilicon field plate 19.

After the etching is completed, the photoresist 216 is removed.

At 1023, a polysilicon gate sidewall oxide layer is formed.

Optionally, a sidewall oxide layer is formed on the outer sides of the polysilicon gate silicon of the LDMOS device, the polysilicon field plate, and the polysilicon gate of the CMOS device by an oxidation process.

And step 1024, performing lightly doped drain implantation of the CMOS device.

And 1025, forming the side walls of the LDMOS device and the CMOS device.

And step 1026, forming a first heavily doped region in the body region of the LDMOS device, forming a second heavily doped region in the drift region of the LDMOS device, and forming a second heavily doped region in the well region of the CMOS device.

And respectively forming a first type heavily doped region and a second type heavily doped region in the substrate through a photoetching process and an ion implantation process.

As shown in fig. 23, a side wall 23 is formed outside a polysilicon gate 21 of the LDMOS device, a side wall 23 is formed outside a polysilicon gate 25 of the CMOS device, a first heavily doped region 17 and a second heavily doped region 18 are formed in a body region 12 of the LDMOS device, a second heavily doped region 18 is formed in a drift region 13 of the LDMOS device, and a second heavily doped region 18 is formed in a well region of the CMOS device.

At 1027, a first dielectric layer is deposited.

Optionally, the first dielectric layer is a silicon oxide layer.

Optionally, the thickness of the first dielectric layer is 200A.

Step 1028, a second dielectric layer is deposited.

Optionally, the second dielectric layer is a silicon nitride layer.

Optionally, the thickness of the second dielectric layer is 200A.

At 1029, an interlevel dielectric layer is deposited.

Optionally, the interlayer dielectric layer is a silicon oxide layer.

And after the interlayer dielectric layer is deposited, performing CMP.

And step 1030, forming a contact hole penetrating through the first dielectric layer, the second dielectric layer and the interlayer dielectric layer.

The contact hole corresponds to the first heavily doped region, the second heavily doped region, the polysilicon gate electrode and the polysilicon field plate of the LDMOS device, and the second heavily doped region and the polysilicon gate electrode of the CMOS device.

And forming a contact hole through an etching process, and filling the contact hole with metal.

And step 1031, depositing a metal layer on the surface of the interlayer dielectric layer, and etching the metal layer.

The etched metal layer is connected with the contact hole.

As shown in fig. 6, after the first heavily doped region 17 and the second heavily doped region 18 in the body region 12 are led out through the contact holes, the source of the LDMOS device is formed by short-circuiting through the metal layer 16; after the polysilicon gate 21 and the polysilicon field plate 19 of the LDMOS device are led out through the contact hole, the gate of the LDMOS device is formed by short circuit through the metal layer 16; a second type heavily doped region in the drift region 13 is led out through the contact hole and is connected with the metal layer 16 to form a drain electrode of the LDMOS device; the source region 26 of the CMOS device is connected with the metal layer 16 through a contact hole to form a source electrode of the CMOS device, the drain region 27 of the CMOS device is connected with the metal layer 16 through a contact hole to form a drain electrode of the CMOS device, and the polysilicon gate 25 of the CMOS device is connected with the metal layer 16 through a contact hole to form a gate electrode of the CMOS device.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. The LDMOS device is characterized by comprising a substrate, a body region, a drift region, an insulating dielectric layer, a grid structure, a polycrystalline silicon field plate, a dielectric isolation layer and a metal layer, wherein the body region and the drift region are positioned in the substrate;

a second type heavily doped region is arranged in the drift region;

the polycrystalline silicon field plate is positioned above the step structure of the insulating medium layer;

the gate structure is positioned above one end of the body region and one end of the drift region, the gate structure comprises a gate dielectric layer and a polysilicon gate, and the polysilicon gate extends to the position above the polysilicon field plate;

after the first heavily doped region and the second heavily doped region in the body region are led out through the contact hole in the medium isolation layer, the source electrode of the LDMOS device is formed through short circuit of the metal layer;

after the polysilicon gate and the polysilicon field plate are led out through the contact hole in the medium isolation layer, the gate of the LDMOS device is formed by short-circuit of the metal layer;

and the second type heavily doped region in the drift region is led out through the contact hole in the medium isolation layer and is connected with the metal layer to form the drain electrode of the LDMOS device.

2. The LDMOS device of claim 1, wherein the layer of insulating dielectric is a shallow trench isolation structure.

3. The LDMOS device set forth in claim 1 wherein said insulating dielectric layer is a local silicon oxide structure.

4. The LDMOS device of claim 2 or 3, wherein the insulating dielectric layer comprises at least 2 steps.

5. The LDMOS device of claim 1, wherein a sidewall is respectively disposed on an outer side of the polysilicon gate and an outer side of the polysilicon field plate.

6. The LDMOS device of claim 1, wherein the dielectric isolation layer comprises a first dielectric layer, a second dielectric layer and an interlayer dielectric layer, the second dielectric layer being located below the interlayer dielectric layer, the first dielectric layer being located below the second dielectric layer.

7. The LDMOS device of claim 6, wherein the first dielectric layer is a silicon oxide layer;

the second dielectric layer is a silicon nitride layer;

the interlayer dielectric layer is a silicon oxide layer.

8. The LDMOS device of claim 1, further comprising an additional drift region located within the substrate;

the bottom of the additional drift region is higher than that of the drift region, the additional drift region surrounds an accumulation region, and the accumulation region is a region, which is overlapped with the gate structure, of the drift region and is not covered by the insulating medium layer.

9. The LDMOS device of any one of claims 1 to 8, wherein a CMOS device is further fabricated on the substrate, the CMOS device comprising a well region disposed in the substrate, a CMOS device gate structure disposed on a surface of the substrate, and a source region and a drain region disposed in the well region;

10. The LDMOS device of claim 1, wherein the substrate is P-type or N-type.

11. A method of fabricating an LDMOS device, the method comprising:

forming an insulating medium layer in the substrate;

etching the insulating dielectric layer to form a step structure, forming a polysilicon field plate above the step structure, and surrounding the etched insulating dielectric layer by the drift region;

forming a first type heavily doped region and a second type heavily doped region in the body region of the LDMOS device, and forming a second type heavily doped region in the drift region of the LDMOS device;

forming an isolation dielectric layer, and forming contact holes in the isolation dielectric layer, wherein the contact holes correspond to the polysilicon gate of the LDMOS device, the polysilicon field plate, and the first type heavily doped region and the second type heavily doped region in the substrate;

and leading out the grid electrode, the source electrode and the drain electrode of the LDMOS device through the filled contact hole and the metal layer above the isolation dielectric layer.

12. The method of claim 11, wherein said etching said insulating dielectric layer to form a step structure and a polysilicon field plate over said step structure comprises:

depositing a first polysilicon layer;

depositing a hard mask layer;

and etching the insulating medium layer and the deposited polycrystalline silicon layer in a grading manner according to the number of steps in the step structure to form the insulating medium layer comprising the step structure and a polycrystalline silicon field plate positioned above the step structure.

13. The method of claim 12, wherein when the number of steps is 2, the etching the insulating dielectric layer and the deposited polysilicon layer in a plurality of times according to the number of steps in the step structure to form an insulating dielectric layer including a step structure and a polysilicon field plate over the step structure comprises:

depositing a second polysilicon layer;

etching the insulating medium layer by taking the hard mask layer and the second polycrystalline silicon layer as masks to form a second step of the insulating medium layer, wherein the etching thickness is 1/2 equal to the thickness of the insulating medium layer;

the first polysilicon layer and the second polysilicon layer jointly form a polysilicon field plate of the LDMOS device.

14. The method of claim 12, wherein when the number of steps is 3, the etching the insulating dielectric layer and the deposited polysilicon layer in steps according to the number of steps in the step structure to form an insulating dielectric layer including a step structure and a polysilicon field plate over the step structure comprises:

depositing a second polysilicon layer;

depositing a third polysilicon layer;

etching the insulating medium layer by taking the hard mask layer, the second polycrystalline silicon layer and the third polycrystalline silicon layer as masks to form a third step of the insulating medium layer, wherein the etching thickness is 1/3 of the thickness of the insulating medium layer;

15. The method of any of claims 11 to 14, wherein the dielectric layer is a shallow trench isolation structure.

16. The method according to any of claims 11 to 14, wherein the insulating dielectric layer is a partial silicon oxide structure.

17. The method of any of claims 11 to 14, further comprising, prior to forming the gate structure of the LDMOS device:

18. The method of any of claims 11 to 14, wherein the forming the polysilicon gate structure of the LDMOS device comprises:

forming a gate dielectric layer of the LDMOS device;

depositing a grid polycrystalline silicon layer of the LDMOS device;

defining a body region of the LDMOS device through a photoetching process;

19. The method of any of claims 11 to 14, wherein the forming an isolation dielectric layer comprises:

20. The method of claim 19, wherein the first dielectric layer is a silicon oxide layer, the second dielectric layer is a silicon nitride layer, and the interlayer dielectric layer is a silicon oxide layer.

21. The method of claim 11, wherein forming a drift region of an LDMOS device within a substrate comprises:

and forming a drift region of the LDMOS device in the substrate, and forming a well region of the CMOS device in a CMOS region in the substrate.

22. The method of claim 12, wherein forming the first heavily doped region in the drift region of the LDMOS device and before forming the first heavily doped region and the second heavily doped region in the body region of the LDMOS device, further comprises:

removing the hard mask layer above the first polycrystalline silicon layer;

defining a grid electrode area of a CMOS device through a photoetching process, etching the first polycrystalline silicon layer according to the grid electrode area of the CMOS device, and forming a grid electrode of the CMOS device above a well region of the CMOS device;

carrying out lightly doped drain injection of the CMOS device;

23. The method of claim 11, further comprising:

forming a second type heavily doped region in the well region of the CMOS device;

and leading out the source electrode and the drain electrode of the CMOS device through the contact hole in the isolation dielectric layer and the metal layer above the isolation dielectric layer.

24. The method of claim 11, wherein the substrate is P-type or N-type.