CN116169175A - LDMOS layout structure - Google Patents
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- CN116169175A CN116169175A CN202310133649.XA CN202310133649A CN116169175A CN 116169175 A CN116169175 A CN 116169175A CN 202310133649 A CN202310133649 A CN 202310133649A CN 116169175 A CN116169175 A CN 116169175A
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- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 150000002500 ions Chemical class 0.000 claims description 19
- 238000000605 extraction Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000003071 parasitic effect Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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Abstract
The invention provides an LDMOS layout structure, which comprises: the polygonal LDMOS device of a plurality of array arrangements, polygonal LDMOS device includes: the LDMOS device comprises a substrate, a buried layer, a drift region, a first shallow trench isolation structure, a first well region, a grid electrode, a source doping region, a second shallow trench isolation structure, a substrate leading-out structure and a second well region.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to an LDMOS layout structure.
Background
With the rapid development of microelectronic technology, BCD (Bipolar-CMOS-DMOS) technology has been widely used in the field of analog circuits such as driving and switching power supplies. The power tube mainly adopts an LDMOS (Lateral Double-diffused MOSFET) device, and reduces the specific on-resistance (on-resistance multiplied by area) of the device on the premise of meeting the voltage-withstanding requirement of the device, so that the device becomes the main direction of development of the medium-high voltage device.
The traditional LDMOS layout adopts strip-shaped layout, and the specific on-resistance cannot be effectively improved. In addition, the conventional high-Power Power LDMOS design also adopts stripe array distribution, so that the chip area cannot be effectively utilized.
Disclosure of Invention
The LDMOS layout structure can solve at least one of the problems that the specific on-resistance of the existing LDMOS device is large, the chip area of the LDMOS device is not effectively utilized, and the like.
In one aspect, an embodiment of the present application provides an LDMOS layout structure, including: a plurality of polygonal LDMOS devices arranged in an array, wherein,
the polygonal LDMOS device comprises:
a substrate;
a buried layer in the substrate;
a drift region having a polygonal shape, the drift region being located in the substrate and near the substrate surface;
the first shallow trench isolation structure is in a polygonal ring shape and is positioned on the surface of the drift region;
the first well region is in a polygonal ring shape, is positioned in the substrate and is arranged around the drift region;
a gate electrode with a polygonal ring shape, wherein the gate electrode is positioned on the substrate between the drift region and the first well region;
the source doping region is in a polygonal ring shape and is positioned on the surface of the first well region;
the second shallow trench isolation structure is in a polygonal ring shape, is positioned in the substrate and is arranged around the first well region;
a plurality of substrate extraction structures, each substrate extraction structure being correspondingly located in the source doped region between each side of the gate and each side of the second shallow trench isolation structure; the method comprises the steps of,
the second well region is located in the substrate and surrounds the second shallow trench isolation structure, and the second well region is connected with the buried layer.
Optionally, in the LDMOS layout structure, two substrate extraction structures on opposite sides and outer sides of the gate are located on the same straight line, and the straight line passes through the center of the LDMOS device.
Optionally, in the LDMOS layout structure, the polygonal LDMOS device further includes: and the polygonal drain doped region is positioned on the surface of the drift region inside the first shallow trench isolation structure.
Optionally, in the LDMOS layout structure, the polygonal LDMOS device further includes: the deep trench isolation structure is in a polygonal ring shape, is positioned in the substrate and is arranged around the second well region.
Optionally, in the LDMOS layout structure, the LDMOS device is in a 2 n-sided shape, where n is an integer greater than or equal to 2.
Optionally, in the LDMOS layout structure, the polygonal LDMOS device further includes: and the annular heavily doped region is positioned on the surface of the second well region.
Optionally, in the LDMOS layout structure, the conductivity types of doped ions in the substrate, the first well region, and the substrate lead-out structure are the same, and the conductivity types of doped ions in the substrate, the first well region, and the substrate lead-out structure are P-type or N-type.
Optionally, in the LDMOS layout structure, the conductivity types of doped ions in the source doped region, the drain doped region, the buried layer, the second well region, and the annular heavily doped region are the same, and the conductivity types of doped ions in the source doped region, the drain doped region, the buried layer, the second well region, and the annular heavily doped region are P-type or N-type.
Optionally, in the LDMOS layout structure, the gate is in overlapping contact with the second well region and the first shallow trench isolation structure.
Optionally, in the LDMOS layout structure, a conductivity type of the doped ions in the substrate is different from a conductivity type of the doped ions in the buried layer.
The technical scheme of the application at least comprises the following advantages:
according to the LDMOS device, the area of a chip is effectively utilized, the substrate extraction structures are arranged in the source doping area outside each side of the grid electrode so as to extract the first well area (substrate/bulk end), so that current channels are arranged in each direction, the width of a conduction channel is increased, the on-resistance of the LDMOS device is reduced by at least one time compared with that of a traditional LDMOS device, the specific on-resistance of the device is reduced, and the current resistance of the device is increased.
Furthermore, the buried layer in the substrate can be led out to the surface of the device by connecting the second well region with the buried layer in the substrate, and High-end (HS) application can be realized by the buried layer.
Furthermore, the device region and the peripheral circuit can be separated by arranging the deep groove isolation structure with the polygonal ring shape at the periphery of the second well region, so that the parasitic effect of the LDMOS device is effectively solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic top view of an LDMOS layout structure according to an embodiment of the present invention;
fig. 2 is a schematic top view of an LDMOS device according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of an LDMOS device taken along line AA' of an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of an LDMOS device under BB' tangent in accordance with an embodiment of the present invention;
wherein reference numerals are as follows:
100-substrate, 200-buried layer;
10-LDMOS devices, 11-drain doped regions, 12-first shallow trench isolation structures, 13-gates, 14-substrate lead-out structures, 15-second shallow trench isolation structures, 16-annular heavily doped regions, 17-deep trench isolation structures and 18-source doped regions;
21-drift region, 22-first well region, 23-second well region, 24-deep well region.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
An embodiment of the present application provides an LDMOS layout structure, referring to fig. 1, fig. 1 is a schematic top view of the LDMOS layout structure according to an embodiment of the present invention, where the LDMOS layout structure includes: a plurality of polygonal LDMOS devices 10 arranged in an array.
Specifically, referring to fig. 2-4, fig. 2 is a schematic top view of an LDMOS device according to an embodiment of the invention, fig. 3 is a schematic cross-sectional view of the LDMOS device under line AA 'of the embodiment of the invention, and fig. 4 is a schematic cross-sectional view of the LDMOS device under line BB' of the embodiment of the invention.
In the application, the LDMOS device is in a shape of 2n sides, wherein n is an integer greater than or equal to 2. For example, n=3, and the LDMOS device is hexagonal; n=4, and the LDMOS device is octagonal; n=5, the LDMOS device is decagonal, etc.
Preferably, n is an integer between 2 and 8. When n is more than or equal to 3, the array distribution of the hexagonal LDMOS devices and the more polygonal LDMOS devices can optimize the utilization of the chip area, and the array distribution of the hexagonal LDMOS devices is obviously superior to that of the bar-shaped LDMOS devices.
In this embodiment, n=3, and the LDMOS device is a hexagonal device, and the polygonal LDMOS device provided in this application is described in detail below.
Referring to fig. 1, 2 and 3, the polygonal LDMOS device includes: the semiconductor device comprises a substrate 100, a buried layer 200, a drift region 21, a first shallow trench isolation structure 12, a first well region 22, a gate 13, a source doping region 18, a second shallow trench isolation structure 15, a substrate lead-out structure 14 and a second well region 23.
Wherein the substrate 100 may be a substrate having an epitaxial layer;
the buried layer 200 is located in the substrate 100 and at a distance from the surface of the substrate 100;
the drift region 21 is polygonal, and the drift region 21 is located in the substrate 100 and is close to the surface of the substrate 100;
the first shallow trench isolation structure 12 is in a polygonal ring shape, and the first shallow trench isolation structure 12 is located on the surface of the drift region 21, wherein the width L of the first shallow trench isolation structure 12 determines the voltage withstand specification of the LDMOS device, and the larger the size, the higher the lateral voltage withstand of the drift region 21 region;
the first well region 22 is in a polygonal ring shape, the first well region 22 is located in the substrate 100 and is arranged around the drift region 21, and a certain interval is formed between the first well region 22 and the drift region 21;
the gate 13 is in a polygonal ring shape, and the gate 13 is positioned on the substrate 100 between the drift region 21 and the first well region 22;
the source doped region 18 is in a polygonal ring shape, and the source doped region 18 is located on the surface of the first well region 22;
the second shallow trench isolation structure 15 is in a polygonal ring shape, and the second shallow trench isolation structure 15 is located in the substrate 100 and is disposed around the first well region 22;
as shown in fig. 2, a plurality of substrate extraction structures 14 are located in the source doped region 18 between each side of the gate 13 and each side of the second shallow trench isolation structure 15, where the substrate extraction structures 14 are used to extract the substrate 100 and its conductive type to the device surface, and the number of substrate extraction structures 14 is the same as the number of sides of the LDMOS device. In this embodiment, six substrate extraction structures 14 are located in the source doped region 18 between each side of the gate 13 and each side of the second shallow trench isolation structure 15;
the second well region 23 is in a polygonal ring shape, the second well region 23 is located in the substrate 100 and is disposed around the second shallow trench isolation structure 15, the second well region 23 may further include a deep well region 24 at the bottom thereof, and the second well region 23 is connected to the buried layer 200 through the deep well region 24. The second well region 23 is connected with the buried layer 200 in the substrate, so that the buried layer 200 can be led out to the surface of the device, and High-end (HS) application can be realized by the buried layer.
Preferably, the polygonal LDMOS device may further include: the drain doped region 11 is polygonal, and the drain doped region 11 is located on the surface of the drift region 21 inside the first shallow trench isolation structure 12.
Preferably, the polygonal LDMOS device may further include: a deep trench isolation structure 17 having a polygonal ring shape, wherein the deep trench isolation structure 17 is located in the substrate 100 and is disposed around the second well region 23. According to the LDMOS device, the deep groove isolation structure 17 which is in the polygonal ring shape is arranged on the periphery of the second well region 23, so that the device region and a peripheral circuit can be separated, and the parasitic effect of the LDMOS device is effectively solved.
Further, the polygonal LDMOS device further comprises: an annular heavily doped region 16 (pick up), the annular heavily doped region 16 being located on the surface of the second well region 23.
The polygonal profiles of the drift region 21, the first shallow trench isolation structure 12, the first well region 22, the gate 13, the source doped region 18, the second shallow trench isolation structure 15, the second well region 23, the drain doped region 11, the deep trench isolation structure 17, and the annular heavily doped region 16 are all consistent with the polygonal profile of the LDMOS device.
Preferably, the gate 13 has overlapping contact with the second well region 23 and the first shallow trench isolation structure 12. In top-down projection, the gate 13 and the second well region 23 have an overlapping region, and the gate 13 and the first shallow trench isolation structure 12 also have an overlapping region. The length of the overlapping area between the gate 13 and the first shallow trench isolation structure 12 is one of the key parameters for measuring the electrical performance of the device, the area (overlapping area) of the gate 13 covering the first shallow trench isolation structure 12 may be referred to as a field plate, and the width of the field plate directly affects the electric field distribution, so as to determine the withstand voltage level of the device.
Wherein the two substrate extraction structures 14 on the opposite sides of the gate 13 are located on the same straight line, and the straight line passes through the center of the LDMOS device.
Preferably, the conductivity types of the doped ions in the substrate 100, the first well region 22 and the substrate extraction structure 14 are the same, and the conductivity types of the doped ions in the substrate 100, the first well region 22 and the substrate extraction structure 14 may be P-type or N-type.
Further, the conductivity types of the doped ions in the source doped region 18, the drain doped region 11, the buried layer 200, the second well region 23, the annular heavily doped region 16, and the deep well region 24 are the same, and the conductivity types of the doped ions in the source doped region 18, the drain doped region 11, the buried layer 200, the second well region 23, the annular heavily doped region 16, and the deep well region 24 may be P-type or N-type.
It should be noted that the conductivity type of the doped ions in the substrate 100, the first well region 22, the substrate extraction structure 14 needs to be ensured to be different from the conductivity type of the doped ions in the source doped region 18, the drain doped region 11, the buried layer 200, the second well region 23, the annular heavily doped region 16, and the deep well region 24.
In this embodiment, the source doped region 18, the drain doped region 11, the buried layer 200, the second well region 23, the annular heavily doped region 16, and the deep well region 24 are P-type, and the conductivity types of the doped ions in the source doped region 18, the drain doped region 11, the buried layer 200, the second well region 23, the annular heavily doped region 16, and the deep well region 24 may be N-type.
In this embodiment, the ring-shaped heavily doped region 16, the drain doped region 11 and the source doped region 18 are all n+ heavily doped regions.
In summary, the present invention provides an LDMOS layout structure, including: a plurality of array-arranged polygonal LDMOS devices 10, the polygonal LDMOS devices comprising: the LDMOS device comprises a substrate 100, a buried layer 200, a drift region 21, a first shallow trench isolation structure 12, a first well region 22, a grid electrode 13, a source doping region 18, a second shallow trench isolation structure 15, a substrate leading-out structure 14 and a second well region 23.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (10)
1. An LDMOS layout structure, comprising: a plurality of polygonal LDMOS devices arranged in an array, wherein,
the polygonal LDMOS device comprises:
a substrate;
a buried layer in the substrate;
a drift region having a polygonal shape, the drift region being located in the substrate and near the substrate surface;
the first shallow trench isolation structure is in a polygonal ring shape and is positioned on the surface of the drift region;
the first well region is in a polygonal ring shape, is positioned in the substrate and is arranged around the drift region;
a gate electrode with a polygonal ring shape, wherein the gate electrode is positioned on the substrate between the drift region and the first well region;
the source doping region is in a polygonal ring shape and is positioned on the surface of the first well region;
the second shallow trench isolation structure is in a polygonal ring shape, is positioned in the substrate and is arranged around the first well region;
a plurality of substrate extraction structures, each substrate extraction structure being correspondingly located in the source doped region between each side of the gate and each side of the second shallow trench isolation structure; the method comprises the steps of,
the second well region is located in the substrate and surrounds the second shallow trench isolation structure, and the second well region is connected with the buried layer.
2. The LDMOS layout structure of claim 1 wherein two of the substrate exit structures outside opposite sides of the gate are on a same straight line and the straight line passes through a center of the LDMOS device.
3. The LDMOS layout structure of claim 1 wherein the polygonal LDMOS device further comprises: and the polygonal drain doped region is positioned on the surface of the drift region inside the first shallow trench isolation structure.
4. The LDMOS layout structure of claim 1 wherein the polygonal LDMOS device further comprises: the deep trench isolation structure is in a polygonal ring shape, is positioned in the substrate and is arranged around the second well region.
5. The LDMOS layout structure of claim 1 wherein the LDMOS device is 2 n-sided, wherein n is an integer greater than or equal to 2.
6. The LDMOS layout structure of claim 3 wherein the polygonal LDMOS device further comprises: and the annular heavily doped region is positioned on the surface of the second well region.
7. The LDMOS layout structure of claim 1, wherein the conductivity types of the doped ions in the substrate, the first well region, and the substrate extraction structure are the same, and the conductivity types of the doped ions in the substrate, the first well region, and the substrate extraction structure are P-type or N-type.
8. The LDMOS layout structure of claim 6, wherein the conductivity types of the doped ions in the source doped region, the drain doped region, the buried layer, the second well region, and the ring-shaped heavily doped region are the same, and the conductivity types of the doped ions in the source doped region, the drain doped region, the buried layer, the second well region, and the ring-shaped heavily doped region are P-type or N-type.
9. The LDMOS layout structure of claim 1 wherein the gate is in overlapping contact with both the second well region and the first shallow trench isolation structure.
10. The LDMOS layout structure of claim 1 wherein the conductivity type of the dopant ions in the substrate is different from the conductivity type of the dopant ions in the buried layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310133649.XA CN116169175A (en) | 2023-02-20 | 2023-02-20 | LDMOS layout structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310133649.XA CN116169175A (en) | 2023-02-20 | 2023-02-20 | LDMOS layout structure |
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| CN116169175A true CN116169175A (en) | 2023-05-26 |
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