CN116960183B - Semiconductor device including LDMOS transistor - Google Patents

Semiconductor device including LDMOS transistor Download PDF

Info

Publication number
CN116960183B
CN116960183B CN202310937332.1A CN202310937332A CN116960183B CN 116960183 B CN116960183 B CN 116960183B CN 202310937332 A CN202310937332 A CN 202310937332A CN 116960183 B CN116960183 B CN 116960183B
Authority
CN
China
Prior art keywords
semiconductor device
polysilicon
gate
metal contact
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310937332.1A
Other languages
Chinese (zh)
Other versions
CN116960183A (en
Inventor
肖莉红
司伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rongxin Semiconductor Huai'an Co ltd
Original Assignee
Rongxin Semiconductor Huai'an Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rongxin Semiconductor Huai'an Co ltd filed Critical Rongxin Semiconductor Huai'an Co ltd
Priority to CN202310937332.1A priority Critical patent/CN116960183B/en
Publication of CN116960183A publication Critical patent/CN116960183A/en
Application granted granted Critical
Publication of CN116960183B publication Critical patent/CN116960183B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a semiconductor device comprising an LDMOS transistor. In the semiconductor device, the LDMOS transistor comprises a field plate formed by expanding a polysilicon strip forming a polysilicon gate to the surface of a field oxide layer of a drift region along the width direction, and a first gate metal contact is formed on the top surface of the polysilicon strip corresponding to the field plate, gate voltage is applied to the field plate and the polysilicon gate through the first gate metal contact, so that the control capability of the polysilicon gate and the field plate is stronger, the surface electric field of the drift region below the field plate can be effectively controlled, the surface electric field of the drift region is effectively weakened, the surface electric field distribution can be optimized, the breakdown voltage of the LDMOS transistor is improved, the on resistance is reduced, and the comprehensive performance of the LDMOS transistor is improved.

Description

Semiconductor device including LDMOS transistor
Technical Field
The present invention relates to the field of integrated circuit fabrication, and more particularly, to a semiconductor device including an LDMOS transistor.
Background
The LDMOS (LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR ) transistor is a power device with a double-diffusion structure, compared with a common MOS transistor, a low-doped drift region is added in the LDMOS transistor, the drift region plays a role in buffering between a channel and a drain region, short-channel effect is weakened, most of drain-source voltage (V DS) can fall on the drift region, after the channel is clamped, the length modulation effect of the channel is basically avoided, when the drain-source voltage is further increased, output resistance is not reduced, the channel region is not easy to pass through, and therefore the Breakdown Voltage (BV) of the LDMOS transistor is basically not limited by the length and doping level of the channel, and independent design can be carried out. The LDMOS transistor is easy to realize the channel length of 0.4-2 mu m in the process, so that the transconductance gm, the drain current (I D), the highest working frequency and the highest working speed are greatly improved compared with the common MOS transistor. The LDMOS transistor is widely applied in the field of medium and high voltages.
For LDMOS transistors, increasing the length of the drift region increases the breakdown voltage, but increases the chip area and on-resistance (R dson), requiring proper structural design to achieve a larger breakdown voltage and smaller on-resistance. Currently, for a semiconductor device including an LDMOS transistor, improvement is still required in terms of increasing the breakdown voltage and reducing the on-resistance of the LDMOS transistor.
Disclosure of Invention
In order to improve the breakdown voltage and reduce the on-resistance of an LDMOS transistor, the invention provides a semiconductor device comprising the LDMOS transistor.
The invention provides a semiconductor device comprising an LDMOS transistor, which comprises a semiconductor substrate with a first conductivity type and the LDMOS transistor formed based on the semiconductor substrate, wherein the LDMOS transistor comprises:
A drift region, a source region and a drain region formed in the semiconductor substrate and having a second conductivity type;
A polysilicon gate formed on the semiconductor substrate, the polysilicon gate crossing from the source region to the drift region;
a drift region field oxide layer formed on the surface of the drift region and adjacent to the drain region;
The field polar plate is formed by expanding polysilicon strips forming the polysilicon grid electrode to the surface of the drift region field oxide layer along the width direction; and
A first gate metal contact is formed on the top surface of the polysilicon strip corresponding to the field plate.
Optionally, the semiconductor device includes a plurality of the LDMOS transistors, the polysilicon gates of at least two of the LDMOS transistors share the polysilicon strip, and the source region and the drain region of at least two of the LDMOS transistors are respectively located at two sides of the polysilicon strip.
Optionally, the LDMOS transistor further includes a source metal contact and a drain metal contact, which are formed on the top surface of the source and the top surface of the drain, respectively.
Optionally, a plurality of the first gate metal contacts are formed on the top surface of the polysilicon strip in a scattered manner corresponding to the field plate.
Optionally, a cross-sectional area of the first gate metal contact formed on the top surface of the polysilicon strip is greater than a cross-sectional area of the source region metal contact and/or the drain region metal contact.
Optionally, the number of the first gate metal contacts formed on the top surface of the polysilicon strip is greater than or equal to the number of the source region metal contacts or the drain region metal contacts located on the side surface of the polysilicon strip.
Optionally, the semiconductor device includes at least one pair of the LDMOS transistors arranged in mirror image, and the LDMOS transistors of each pair of the LDMOS transistors arranged in mirror image share the source region.
Optionally, the LDMOS transistor further comprises a second gate metal contact formed at an end of the polysilicon strip in a length direction.
Optionally, the semiconductor device further includes a metal silicide layer formed on a top surface of the field plate and an interlayer dielectric layer, the interlayer dielectric layer covers the semiconductor substrate and each of the LDMOS transistors, the first gate metal contact is filled in a via hole penetrating through the interlayer dielectric layer, and the via hole exposes the metal silicide layer.
Optionally, the semiconductor device is a BCD device, and the BCD device includes the LDMOS transistor, the bipolar transistor, and the CMOS transistor formed based on the semiconductor substrate.
In the semiconductor device comprising the LDMOS transistor, the LDMOS transistor is provided with the field plate formed by expanding the polysilicon strip forming the polysilicon gate to the surface of the field oxide layer of the drift region along the width direction, the first gate metal contact is formed on the top surface of the polysilicon strip corresponding to the field plate, the gate voltage is applied to the field plate and the polysilicon gate through the first gate metal contact, the control capability on the polysilicon gate and the field plate is higher, the surface electric field of the drift region below the field plate can be effectively controlled, the surface electric field of the drift region is effectively weakened, the surface electric field distribution can be optimized, the breakdown voltage of the LDMOS transistor is improved, the on resistance is reduced, and the comprehensive performance of the LDMOS transistor is improved.
Drawings
Fig. 1 is a schematic diagram of a contact layer layout of a semiconductor device comprising an LDMOS transistor.
Fig. 2 is a schematic cross-sectional view of the semiconductor device shown in fig. 1.
Fig. 3 is a schematic cross-sectional view of a semiconductor device including an LDMOS transistor according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a contact layer layout of a semiconductor device including an LDMOS transistor according to an embodiment of the present invention.
Reference numerals illustrate:
100-a semiconductor substrate; 101-a drift region; 102-body region; 103-drift region field oxide layer.
Detailed Description
The semiconductor device comprising an LDMOS transistor according to the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be understood that the drawings in the specification are in a very simplified form and are all to a non-precise scale, simply to facilitate a clear and thorough description of the embodiments of the invention. It should be noted that the order of steps in the methods presented herein is not necessarily the only order in which the steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "on … …" may also include "under … …" and other orientations.
Fig. 1 and 2 illustrate a contact layer layout and cross-sectional structure, respectively, of a semiconductor device comprising an LDMOS transistor. Referring to fig. 1 and 2, a semiconductor device includes a semiconductor substrate 100 and a plurality of LDMOS transistors formed based on the semiconductor substrate 100. The plurality of LDMOS transistors are arranged in a column and share a polysilicon strip to form a polysilicon gate (such as polysilicon gate G1 or polysilicon gate G2), wherein the source region S and the drain region (such as drain region D1 or drain region D2) of each LDMOS transistor are respectively located at two sides of the corresponding polysilicon strip. The polysilicon gate is connected with a gate metal contact C G, the source region S is connected with a source region metal contact C S, the drain region D1 is connected with a drain region metal contact C D1, and the drain region D2 is connected with a drain region metal contact C D2.
Taking the LDMOS transistors located on the right side in fig. 2 as an example, each LDMOS transistor may further include a drift region 101 and a body region 102 formed in the semiconductor substrate 100, a drift region field oxide layer 103 formed on the surface of the drift region 101 and adjacent to the drain region D1, and a field plate FP1 formed by extending a polysilicon strip constituting the polysilicon gate G1 in a width direction (herein, the width direction of the polysilicon strip) to the surface of the drift region field oxide layer 103, a source region S of the LDMOS transistor is formed on top of the body region 102, a drain region D1 is formed on top of the drift region 101, and further, a source region metal contact C S, a drain region metal contact C D1, and a gate metal contact C G are formed on the top surface of the source region S, the top surface of the drain region D1, and the top surface of the polysilicon gate G1, respectively.
As shown in fig. 1, in the semiconductor device, the gate metal contact C G for controlling the polysilicon gate G1 and the field plate FP1 is located at the end of the polysilicon strip forming the polysilicon gate G1, and a schottky barrier (SchottkyBarrier) is formed between the gate metal contact C G and the polysilicon strip, although the contact resistance can be reduced by forming a metal silicide layer on the surface of the polysilicon strip and the polysilicon strip has a high doping concentration to improve the electron tunneling probability, since the gate metal contact C G is located at the end of the polysilicon strip, the pressurizing path of the gate voltage is longer, the voltage loss is caused by the voltage division of the impedance of the polysilicon strip, and then the control capability of the gate metal contact C G on the polysilicon gate G1 and the field plate FP1 is poor, so that the surface electric field of the drift region 101 cannot be effectively weakened, the breakdown voltage of the LDMOS transistor is smaller, the on resistance is higher, and the comprehensive performance of the LDMOS transistor is poor.
The semiconductor device including the LDMOS transistor according to the embodiments of the present invention described below can effectively improve the problems of the semiconductor devices shown in fig. 1 and 2.
The following description mainly uses LDMOS transistors as n-channel transistors. In this case, the first conductivity type described below is p-type, and the second conductivity type opposite to the first conductivity type is n-type. However, the LDMOS transistor is not limited to an n-channel, but may be a p-channel, in which case the first conductivity type is n-type and the second conductivity type opposite to the first conductivity type is p-type. The n-type dopant used to form the n-type doping includes, for example, phosphorus (P) or arsenic (As), and the P-type dopant used to form the P-type doping includes, for example, boron (B).
Fig. 3 is a schematic cross-sectional view of a semiconductor device including an LDMOS transistor according to an embodiment of the present invention. Fig. 4 is a schematic diagram of a contact layer layout of a semiconductor device including an LDMOS transistor according to an embodiment of the present invention. Referring to fig. 3 and 4, an embodiment of the present invention relates to a semiconductor device including an LDMOS transistor, the semiconductor device including a semiconductor substrate 100 having a first conductivity type and the LDMOS transistor formed based on the semiconductor substrate 100. Alternatively, the semiconductor device is a BCD device including, for example, at least one of the LDMOS transistor, at least one bipolar transistor, and at least one CMOS transistor formed based on the semiconductor substrate 100.
The semiconductor substrate 100 is used to form a semiconductor device including an LDMOS transistor. The material of the semiconductor substrate 100 may be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or the like, or may be Silicon On Insulator (SOI) or Germanium On Insulator (GOI), or may be other materials, such as GaAsP, alInAs, alGaAs, gaInAs, gaInP or GaInAsP, or the like, or may be a combination of the foregoing materials. The semiconductor substrate 100 may include doped epitaxial layers, graded semiconductor layers, and semiconductor layers (e.g., silicon layers on silicon germanium layers) overlying other semiconductor layers of different types. The semiconductor substrate 100 is here, for example, a silicon epitaxial substrate, which has a first conductivity type (e.g. p-) doping.
As an example, as shown in fig. 3, the semiconductor device includes a plurality of the LDMOS transistors. At least one pair of the LDMOS transistors, for example, are arranged in a mirror image, and the LDMOS transistors of each pair of the mirror image are arranged to share a source region S. The LDMOS transistor on the left side in fig. 3 is mirror symmetric with the LDMOS transistor on the right side.
Taking the LDMOS transistor located on the right side in fig. 3 as an example, at least one LDMOS transistor in the semiconductor device includes a drift region 101, a source region S, and a drain region D1 formed in a semiconductor substrate 100, and further includes a polysilicon gate G1, a field plate FP1, a source region metal contact C S, a drain region metal contact C D1, and a first gate metal contact C G formed on the semiconductor substrate 100. For the LDMOS transistor on the left side in fig. 3, it includes a polysilicon gate G2, a source region S, a drain region D2, and corresponding drift regions, a first gate metal contact C G, a source metal contact C S, and a drain metal contact C D2. The first gate metal contacts C G of the LDMOS transistors on the left and right in fig. 3 may be connected over the semiconductor substrate 100 by an interconnect layer.
The LDMOS transistor on the right side in fig. 3 is further described below as an example.
The drift region 101 is used to drift carriers by forming a depletion electric field when the LDMOS transistor is in operation, the drift region 101 is opposite to the doping type of the semiconductor substrate 100, and the drift region 101 has, for example, a second conductivity type (e.g., n-) doping.
A source region S and a drain region D1 are formed on top of the semiconductor substrate 100. In this embodiment, the semiconductor substrate 100 has the body region 102 therein, and the body region 102 extends from the semiconductor substrate 100 to the surface of the semiconductor substrate 100 at a position different from the drift region 101 (i.e., not overlapping with the drift region 101). The body region 102 has a conductivity type opposite to the drift region 101 and is of the first conductivity type. The source region S is surrounded by the body region 102. The drain region D1 is disposed on top of the semiconductor substrate 100 and surrounded by the drift region 101. The source region S and the drain region D1 have a second conductivity type doping, and the second conductivity type doping concentration of the source region S and the drain region D1 is, for example, larger than the second conductivity type doping concentration of the drift region 101.
A gate dielectric layer (not shown) and a polysilicon gate G1 are sequentially stacked on the surface of the semiconductor substrate 100, and the polysilicon gate G1 spans from the source region S to the drift region 101. The source region S and the drain region D1 are asymmetrically disposed at two sides of the polysilicon gate G1, wherein the drain region D1 is disposed at a certain distance from the polysilicon gate G1, and the drift region 101 is disposed at a side of the polysilicon gate G1 facing the drain region D1. When the polysilicon gate G1 of the LDMOS transistor is properly biased, a conductive channel (e.g., n-type) is formed at the surface of the active region below the gate dielectric layer. The LDMOS transistor of this structure has a high voltage applied to the drain region D1 at the time of blocking.
A drift region field oxide layer 103 is formed on the surface of the drift region 101 and abuts the drain region D1 of the respective LDMOS transistor. The drift region field oxide layer 103 has an effect of relaxing an electric field. The drift region field oxide layer 103 may be formed using a Shallow Trench Isolation (STI) process, a local oxidation of silicon isolation (LOCOS) process, or a Low Pressure Chemical Vapor Deposition (LPCVD) process. The drift region field oxide layer 103 may include a silicon oxide layer (SiO 2), a silicon nitride layer (Si 3N4), or other suitable material.
The field plate FP1 is formed by extending a polysilicon stripe constituting the polysilicon gate G1 in the width direction (herein, the width direction of the polysilicon stripe) to the surface of the drift region field oxide layer 103, and by applying an appropriate voltage to the field plate FP1, the concentration of the depletion electric field formed in the surface region of the drift region 101 in the blocking state can be relaxed, the surface electric field of the drift region 101 can be weakened, and by optimizing the surface electric field distribution, the withstand voltage value of the drift region per unit length can be increased, the drift region length can be shortened, and the on-resistance can be reduced.
In the LDMOS transistor, for example, an active region metal contact C S, a drain region metal contact C D1, and a first gate metal contact C G are formed on the top surface of the source region S, the top surface of the drain region D1, and the top surface of the field plate FP1, respectively. A first gate metal contact C G is formed on the top surface of the polysilicon strip that forms the polysilicon gate G1, corresponding to the field plate FP 1. As shown in fig. 4, the LDMOS transistor may optionally further include a second gate metal contact C G', the second gate metal contact C G' being formed at an end portion of the respective polysilicon strip in a length direction.
The semiconductor device may further include an interlayer dielectric layer (not shown), where the interlayer dielectric layer covers the semiconductor substrate 100 and each of the LDMOS transistors, and the source metal contact C S, the drain metal contact C D1, and the first gate metal contact C G and the second gate metal contact C G' are respectively filled in, for example, a via hole penetrating the interlayer dielectric layer, that may be implemented by using a contact plug.
The semiconductor device may further include a metal silicide layer (not shown), which is formed on, for example, the top surface of the source region S, the top surface of the drain region D1, and the top surface of the field plate FP1 (or the polysilicon strip), and is exposed by the above-mentioned via holes. The metal silicide layer may include at least one of titanium silicide, cobalt silicide, nickel silicide, and tantalum silicide. The metal silicide layer may be formed before the interlayer dielectric layer is deposited on the semiconductor substrate 100, or may be formed on the bottom surface of the via after the via is formed in the interlayer dielectric layer.
The sides of the via may be covered with a metal migration barrier layer and/or an adhesion layer, for example, the sides of the via are covered with a stack of titanium nitride (TiN) and Titanium (TiN). The source region metal contact C S, the drain region metal contact C D1, the first gate metal contact C G, and the second gate metal contact C G' may include at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, cobalt, copper alloy, and aluminum alloy filled in the respective through holes.
In the semiconductor device including the LDMOS transistor in the embodiment of the invention, each LDMOS transistor has the field plate FP1 formed by expanding the polysilicon strip forming the polysilicon gate G1 to the surface of the drift region field oxide layer 103 along the width direction, and the first gate metal contact C G is formed on the top surface of the polysilicon strip corresponding to the field plate FP1, compared with the manner that the gate metal contact is only provided at the end of the polysilicon strip as shown in fig. 1 and 2, the embodiment of the invention can improve the control capability of the gate voltage on the polysilicon gate G1 and the field plate FP1 by using the first gate metal contact C G, can effectively control the surface electric field of the drift region under the field plate FP1, effectively weaken the surface electric field of the drift region 101, optimize the surface electric field distribution, and is beneficial to improving the breakdown voltage and reducing the on-resistance of the LDMOS transistor.
As shown in fig. 4, alternatively, the polysilicon gates of at least two of the LDMOS transistors are connected to share a polysilicon stripe as the polysilicon gate. Further, in the semiconductor device, a plurality of LDMOS transistors are arranged in a plurality of columns, for example, the polysilicon gates of each column of LDMOS transistors share a polysilicon stripe to form a polysilicon gate (such as polysilicon gate G1 or polysilicon gate G2), and the source region S and the drain region (such as drain region D1 or drain region D2) of each LDMOS transistor are respectively located at two sides of the corresponding polysilicon stripe.
In order to shorten the pressurizing path of the gate voltage and reduce the voltage loss caused by the impedance voltage division of the polysilicon strip, a plurality of first gate metal contacts C G are formed on the top surface of the polysilicon strip in a scattered manner in the area corresponding to the field plate. In addition, the end portion of the polycrystalline body bar in the length direction may be further formed with a second gate metal contact C G'. Thus, the voltages applied to the polysilicon gate and the field plate of each LDMOS transistor may be applied through the plurality of first gate metal contacts C G and second gate metal contacts C G' formed on the top surface of the corresponding polysilicon strip, which may significantly improve the control capability of the gate voltage to the field plate and the polysilicon gate as compared to the manner in which the gate metal contacts are provided only at the ends of the polysilicon strip as shown in fig. 1.
In the semiconductor device, the top surface of the field plate FP1 is formed with the first gate metal contact C G, the drift region field oxide layer 103 is spaced between the field plate FP1 and the drain region D1, and the polysilicon gate G1 is spaced between the field plate FP1 and the source region S, so that the distances between the field plate FP1 and the drain region metal contact C D1 and between the field plate FP1 and the source region metal contact C S are not too close, and the arrangement of the first gate metal contact C G on the top surface of the field plate FP1 does not affect the performance of the source region metal contact C S and the drain region metal contact C D1, and does not significantly increase the process difficulty. The cross-sectional area of the first gate metal contact C G may be set larger to reduce contact resistance. Optionally, the cross-sectional area of the first gate metal contact C G formed on the top surface of the polysilicon strip is greater than the cross-sectional area of the source region metal contact C S and/or the drain region metal contact C D1.
Since at least two of the LDMOS transistors share a polysilicon strip as a polysilicon gate, the gate metal contacts C G disposed on the polysilicon strip are shared by the LDMOS transistors sharing the polysilicon strip, and the number of gate metal contacts C G may be set as desired, for example, may be greater than, less than, or equal to the number of the LDMOS transistors in the semiconductor device (i.e., the number of corresponding source metal contacts C S or drain metal contacts C D1). In view of maintaining a suitable spacing between gate metal contacts C G and avoiding an increase in process costs, the number of gate metal contacts C G formed on the top surface of the polysilicon strip is optionally less than or equal to the number of source metal contacts C S or drain metal contacts C D1 located on the sides of the polysilicon strip.
In the semiconductor device including the LDMOS transistor described in the embodiment of the present invention, the LDMOS transistor has the field plate FP1 formed by expanding the polysilicon strip forming the polysilicon gate G1 to the surface of the drift region field oxide layer 103 along the width direction, and the top surface of the field plate FP1 is formed with the first gate metal contact C G, compared with the manner that the gate metal contact (the structure shown in fig. 1) is only provided at the end of the polysilicon strip forming the polysilicon gate G1, the control capability of the gate voltage to the field plate FP1 and the polysilicon gate G1 can be improved, the surface electric field of the drift region 101 can be effectively weakened, the surface electric field distribution is optimized, the breakdown voltage of the LDMOS transistor is improved, the on resistance is reduced, and the comprehensive performance of the LDMOS transistor is improved.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (8)

1. A semiconductor device comprising an LDMOS transistor, the semiconductor device comprising a semiconductor substrate having a first conductivity type and a plurality of LDMOS transistors formed based on the semiconductor substrate, the LDMOS transistor comprising:
A drift region, a source region and a drain region formed in the semiconductor substrate and having a second conductivity type;
A polysilicon gate formed on the semiconductor substrate, the polysilicon gate crossing from the source region to the drift region;
a drift region field oxide layer formed on the surface of the drift region and adjacent to the drain region;
the field plate is formed by expanding polysilicon strips forming the polysilicon gate to the surface of the drift region field oxide layer along the width direction, and the field plate and the polysilicon gate are integrally formed along the width direction; and
A first gate metal contact formed on the top surface of the polysilicon strip corresponding to the field plate;
The polysilicon gates of at least two LDMOS transistors share the same polysilicon strip, a plurality of first gate metal contacts are distributed between two end parts of the same polysilicon strip, and the semiconductor device further comprises second gate metal contacts formed at the end parts of the same polysilicon strip.
2. The semiconductor device of claim 1, wherein source and drain regions of at least two of said LDMOS transistors are located on opposite sides of said polysilicon strip, respectively.
3. The semiconductor device of claim 2, wherein the LDMOS transistor further comprises:
And the source region metal contact and the drain region metal contact are respectively formed on the top surface of the source region and the top surface of the drain region.
4. The semiconductor device of claim 3, wherein a cross-sectional area of the first gate metal contact formed by the top surface of the polysilicon strip is greater than a cross-sectional area of the source metal contact and/or the drain metal contact.
5. The semiconductor device of claim 3, wherein a number of the first gate metal contacts formed on the top surface of the polysilicon strip is greater than or equal to a number of the source metal contacts or the drain metal contacts located on the sides of the polysilicon strip.
6. The semiconductor device of claim 2, wherein the semiconductor device comprises at least one pair of the LDMOS transistors arranged in mirror image, the LDMOS transistors of each pair of the LDMOS transistors arranged in mirror image sharing the source region.
7. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
a metal silicide layer formed on the top surface of the field plate; and
And the interlayer dielectric layer covers the semiconductor substrate and the LDMOS transistor, the first gate metal contact is filled in a through hole penetrating through the interlayer dielectric layer, and the through hole exposes the metal silicide layer.
8. The semiconductor device of claim 1, wherein the semiconductor device is a BCD device comprising the LDMOS transistor, a bipolar transistor, and a CMOS transistor formed based on the semiconductor substrate.
CN202310937332.1A 2023-07-27 2023-07-27 Semiconductor device including LDMOS transistor Active CN116960183B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310937332.1A CN116960183B (en) 2023-07-27 2023-07-27 Semiconductor device including LDMOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310937332.1A CN116960183B (en) 2023-07-27 2023-07-27 Semiconductor device including LDMOS transistor

Publications (2)

Publication Number Publication Date
CN116960183A CN116960183A (en) 2023-10-27
CN116960183B true CN116960183B (en) 2024-05-17

Family

ID=88457986

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310937332.1A Active CN116960183B (en) 2023-07-27 2023-07-27 Semiconductor device including LDMOS transistor

Country Status (1)

Country Link
CN (1) CN116960183B (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2743978Y (en) * 2004-06-24 2005-11-30 东南大学 Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate
CN104377244A (en) * 2013-08-15 2015-02-25 无锡华润上华半导体有限公司 Device structure lowering LDMOS on resistance
US9450074B1 (en) * 2011-07-29 2016-09-20 Maxim Integrated Products, Inc. LDMOS with field plate connected to gate
CN106935647A (en) * 2015-12-31 2017-07-07 爱思开海力士有限公司 Lateral direction power integrated device with low on-resistance
CN208385412U (en) * 2018-05-25 2019-01-15 矽力杰半导体技术(杭州)有限公司 Transverse diffusion metal oxide semiconductor device
CN110350032A (en) * 2018-04-04 2019-10-18 无锡华润上华科技有限公司 A kind of semiconductor devices
CN111180504A (en) * 2018-11-13 2020-05-19 无锡华润上华科技有限公司 Lateral diffusion metal oxide semiconductor device and manufacturing method thereof
CN111540785A (en) * 2020-05-13 2020-08-14 上海华虹宏力半导体制造有限公司 LDMOS device and manufacturing method thereof
CN111883594A (en) * 2020-08-14 2020-11-03 华虹半导体(无锡)有限公司 Lateral diffusion high-voltage device and manufacturing method thereof
CN114464602A (en) * 2022-01-26 2022-05-10 力来托半导体(上海)有限公司 Enhancement mode capacitor for integration with metal oxide semiconductor field effect transistor
CN115064596A (en) * 2022-08-18 2022-09-16 广州粤芯半导体技术有限公司 Semiconductor device and method for manufacturing the same
CN115424932A (en) * 2022-08-19 2022-12-02 上海华虹宏力半导体制造有限公司 LDMOS device and technological method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7847351B2 (en) * 2008-04-11 2010-12-07 Texas Instruments Incorporated Lateral metal oxide semiconductor drain extension design
US8610206B2 (en) * 2011-02-18 2013-12-17 Macronix International Co., Ltd. Split-gate lateral diffused metal oxide semiconductor device
KR101864889B1 (en) * 2012-01-20 2018-06-05 에스케이하이닉스 시스템아이씨 주식회사 Lateral DMOS transistor and method of fabricating the same
US9590053B2 (en) * 2014-11-25 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Methodology and structure for field plate design
US20200194583A1 (en) * 2018-12-14 2020-06-18 AZ Power, Inc Metal source ldmos semiconductor device and manufacturing method thereof
US20210074851A1 (en) * 2019-09-05 2021-03-11 Richtek Technology Corporation High voltage device and manufacturing method thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2743978Y (en) * 2004-06-24 2005-11-30 东南大学 Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate
US9450074B1 (en) * 2011-07-29 2016-09-20 Maxim Integrated Products, Inc. LDMOS with field plate connected to gate
CN104377244A (en) * 2013-08-15 2015-02-25 无锡华润上华半导体有限公司 Device structure lowering LDMOS on resistance
CN106935647A (en) * 2015-12-31 2017-07-07 爱思开海力士有限公司 Lateral direction power integrated device with low on-resistance
CN110350032A (en) * 2018-04-04 2019-10-18 无锡华润上华科技有限公司 A kind of semiconductor devices
CN208385412U (en) * 2018-05-25 2019-01-15 矽力杰半导体技术(杭州)有限公司 Transverse diffusion metal oxide semiconductor device
CN111180504A (en) * 2018-11-13 2020-05-19 无锡华润上华科技有限公司 Lateral diffusion metal oxide semiconductor device and manufacturing method thereof
CN111540785A (en) * 2020-05-13 2020-08-14 上海华虹宏力半导体制造有限公司 LDMOS device and manufacturing method thereof
CN111883594A (en) * 2020-08-14 2020-11-03 华虹半导体(无锡)有限公司 Lateral diffusion high-voltage device and manufacturing method thereof
CN114464602A (en) * 2022-01-26 2022-05-10 力来托半导体(上海)有限公司 Enhancement mode capacitor for integration with metal oxide semiconductor field effect transistor
CN115064596A (en) * 2022-08-18 2022-09-16 广州粤芯半导体技术有限公司 Semiconductor device and method for manufacturing the same
CN115424932A (en) * 2022-08-19 2022-12-02 上海华虹宏力半导体制造有限公司 LDMOS device and technological method

Also Published As

Publication number Publication date
CN116960183A (en) 2023-10-27

Similar Documents

Publication Publication Date Title
US9947787B2 (en) Devices and methods for a power transistor having a schottky or schottky-like contact
US9450091B2 (en) Semiconductor device with enhanced mobility and method
US5831320A (en) High voltage metal oxide silicon field effect transistor
US6753574B2 (en) Semiconductor device and method for fabricating the same
KR100652449B1 (en) Lateral thin-film silicon-on-insulator soi jfet device
US8704304B1 (en) Semiconductor structure
US9985028B2 (en) Diluted drift layer with variable stripe widths for power transistors
US10510869B2 (en) Devices and methods for a power transistor having a Schottky or Schottky-like contact
US7446354B2 (en) Power semiconductor device having improved performance and method
US7151296B2 (en) High voltage lateral diffused MOSFET device
US6160288A (en) Vertical type misfet having improved pressure resistance
US20240274707A1 (en) Manufacturing method of semiconductor device
CN115332324A (en) Semiconductor device and method for manufacturing the same
US11430885B2 (en) Semiconductor device
US11145718B2 (en) Semiconductor device with separate active region and method of fabricating the same
US9530884B2 (en) Method of manufacturing a semiconductor device and semiconductor device
US9070768B2 (en) DMOS transistor having an increased breakdown voltage and method for production
CN116960183B (en) Semiconductor device including LDMOS transistor
US11757034B2 (en) High voltage device
US11101384B1 (en) Power semiconductor device
US20180277677A1 (en) Transistor structure and manufacturing method of the same
CN111446245B (en) Semiconductor structure
CN109524450B (en) Semiconductor device with a plurality of semiconductor chips
EP0654827A1 (en) Integrated power cascode
CN111725319B (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant