CN2743978Y - Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate - Google Patents
Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate Download PDFInfo
- Publication number
- CN2743978Y CN2743978Y CNU200420062099XU CN200420062099U CN2743978Y CN 2743978 Y CN2743978 Y CN 2743978Y CN U200420062099X U CNU200420062099X U CN U200420062099XU CN 200420062099 U CN200420062099 U CN 200420062099U CN 2743978 Y CN2743978 Y CN 2743978Y
- Authority
- CN
- China
- Prior art keywords
- leak
- field
- type
- polycrystalline silicon
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 26
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model discloses a high-voltage N-type metal oxide semiconductor transistor with multiple electric potential field pole plate, which relates to high-voltage devices. The high-voltage N-type metal oxide semiconductor transistor is composed of an N-type substrate, a P-type epitaxial layer, a source, a leak, a polycrystalline silicon gate, a field oxide layer and an oxide layer. A polycrystalline silicon field pole plate is equipped above the field oxide layer and between the leak and the polycrystalline silicon gate, and the polycrystalline silicon field pole plate connects to the leak. The polycrystalline silicon field pole plate which has equal potential with the leak end is introduced, so as to make a drift region surface positioned below the polycrystalline silicon field pole plate stay at the state of carrier accumulation, and thus the peak value electric field of the leak end and the polycrystalline silicon field pole plate is greatly reduced at the starting state, so that the collision ionization of the carrier of the leak end is decreased, and a Kirk effect is greatly reduced (an effect that a breakdown voltage is reduced by the high accumulation of leak end electric field under great current), and the breakdown voltage and the safe operating area of the device are enhanced.
Description
Technical field
The utility model is a kind of MOS (metal-oxide-semiconductor) transistor, especially many current potentials field plate high-pressure N-type metal oxide semiconductor tube.
Background technology
It is good that the MOS type high tension apparatus has switching characteristic, advantages such as power consumption is little, what is more important MOS type high tension apparatus is easy to compatibility standard low pressure metal oxide semiconductor technology, reduce production cost of chip, therefore MOS type high pressure integrated device has absolute predominance in the range of application of 10V-600V, in the 100V operating voltage, adopt the body silicon materials to have advantages such as cost is low, but more than 100V, the body silicon materials can't meet design requirement, therefore epitaxial material will become first-selection, adopt epitaxial material can satisfy 1000V with interior operating voltage requirement.In the application of many high pressure integrated chips, require the power output of chip very big, this just requires chip to have bigger output current.Continuous expansion just because of the related application field, multiple structure has appearred in high-pressure N-type metal oxide semi-conductor type device, particularly the field plate structure has obtained using widely, but the field plate structure has also been brought a problem, be exactly very high at the electric field of field plate end, limited the further raising of high-pressure N-type metal oxide semiconductor device puncture voltage, many field plates structure can be extenuated this phenomenon, but this also can increase the peak value electric field in drain region, cause the safety operation area of reduction high-pressure N-type metal oxide semi-conductor type device when big electric current is exported, reduce chip reliability.The utility model will provide a kind of peak value electric field that both can reduce high-pressure N-type metal oxide semiconductor device field plate end and drain region peak value electric field, improve puncture voltage and and the compatible fully high-pressure N-type metal oxide semiconductor tube of standard low pressure metal oxide semiconductor processing, be easy to be integrated in the extensive high-voltage power integrated chip, reduced the cost of large-scale production.
Summary of the invention
The utility model provide a kind of puncture voltage more than the 100V, operating current is more than 100mA and the many current potential field plate high-pressure N-type metal oxide semiconductor tube compatible mutually with standard epitaxial metal oxide semiconductor technology.
The utility model adopts following technical scheme:
A kind of many current potentials field plate high-pressure N-type metal oxide semiconductor tube that relates to high tension apparatus, by N type substrate 1, P type epitaxial loayer 2, source 3, leak 4, polysilicon gate 5, field oxide 6 and oxide layer 8 are formed, P type epitaxial loayer 2 is located at the top of N type substrate 1, field oxide 6 is in the source 3 and leak between 4, source 3, leak 4, polysilicon gate 5 and field oxide 6 are positioned at the top of P type epitaxial loayer 2, between polysilicon gate 5 and P type epitaxial loayer 2, be provided with gate oxide 7, oxide layer 8 is positioned at source 3, leak 4, the top of polysilicon gate 5 and field oxide 6, above P type epitaxial loayer 2, the below of oxide layer 8 and between source 3 and field oxide 6, be provided with P type contact hole 9, at polysilicon gate 5, be respectively equipped with the metallic aluminium lead-in wire in source 3 and the leakage 4, it is characterized in that being provided with polysilicon field plate 10 above the field oxide 6 and between leakage 4 and polysilicon gate 5, this polysilicon field plate 10 is connected with leakage 4.
Compared with prior art, the utlity model has following advantage:
(1) the utility model has been introduced and the equipotential polysilicon field plate of drain terminal, like this can be so that the surface, drift region below the polysilicon field plate is in the accumulated state of charge carrier, thereby the peak value electric field when reducing the unlatching attitude greatly between drain terminal and the polysilicon field plate, thereby reduce the ionization by collision of drain terminal charge carrier, reduce the Kirk effect greatly (under the big current conditions, drain terminal electric field height is assembled and effect that the puncture voltage that causes reduces), the puncture voltage and the safety operation area of having improved device.
(2) because polysilicon field plate and drain terminal equipotential, the drift region of so much crystal silicon field plate below just is in the coherent condition of charge carrier, like this electric current will be below pressing close to the polysilicon field plate surface current mistake of drift region, thereby reduce the resistance of drift region greatly, reduce the power consumption of device.
(3) the utility model has been introduced a plurality of polysilicon field plates, a plurality of field plates can less effectively single field plate end peak value electric field, thereby reduced the peak value electric field on the surface, drift region of high-pressure N-type metal oxide semiconductor tube, improved the puncture voltage when high-pressure N-type metal oxide semiconductor tube closes closed state.
(4) the utility model introduce simultaneously a plurality of float field plate and with the equipotential polysilicon field plate of drain terminal, breakdown characteristics, safety operation area, reduction conducting resistance in the time of so not only can improving the unlatching attitude of high-pressure N-type metal oxide semiconductor tube, and can improve puncture bulk voltage when closing closed state, thereby the performance of this high-pressure N-type metal oxide semiconductor tube is greatly enhanced, and area of safety operaton improves greatly.
(5) because a plurality of polysilicon field plate of floating the polysilicon field plate and linking with drain terminal of the present utility model can be based on realizing on the standard extension low pressure metal oxide semiconductor processing line, and needn't increase any processing step, so the utlity model has low cost of manufacture, but advantages such as industrialization.Concrete prepared flow process is: at first select P type substrate, prepare epitaxial loayer then, prepare P type trap then, carry out the preparation of gate oxide then, being growth, the etching of polysilicon gate and polysilicon field plate then, next is exactly source, drain region, fairlead, the preparation of aluminum lead and Passivation Treatment, whole technical process fully can be based on realizing on the standard extension low pressure metal oxide semiconductor processing line.
(6) N type epitaxial material is compared with the body silicon materials better breakdown characteristics can be provided.
(7) P type trap can improve the impurity concentration of channel region, thereby has prevented the punch through of this high-pressure N-type metal oxide semiconductor tube effectively, has improved the puncture voltage of whole high pressure N pipe and has dwindled chip area.
Description of drawings
Fig. 1 is the structural representation of present embodiment.
Embodiment
A kind of many current potentials field plate high-pressure N-type metal oxide semiconductor tube that relates to high tension apparatus of embodiment, by N type substrate 1, P type epitaxial loayer 2, source 3, leak 4, polysilicon gate 5, field oxide 6 and oxide layer 8 are formed, P type epitaxial loayer 2 is located at the top of N type substrate 1, field oxide 6 is in the source 3 and leak between 4, source 3, leak 4, polysilicon gate 5 and field oxide 6 are positioned at the top of P type epitaxial loayer 2, between polysilicon gate 5 and P type epitaxial loayer 2, be provided with gate oxide 7, oxide layer 8 is positioned at source 3, leak 4, the top of polysilicon gate 5 and field oxide 6, above P type epitaxial loayer 2, the below of oxide layer 8 and between source 3 and field oxide 6, be provided with P type contact hole 9, at polysilicon gate 5, be respectively equipped with metallic aluminium lead-in wire 13 in source 3 and the leakage 4,14 and 15, it is characterized in that being provided with polysilicon field plate 10 above the field oxide 6 and between leakage 4 and polysilicon gate 5, this polysilicon field plate 10 is connected with leakage 4, in the present embodiment, be provided with the polysilicon field plate 11 of floating above the field oxide 6 and between polysilicon field plate 10 and polysilicon gate 5, the quantity that is provided with of polysilicon field plate 11 of floating is 1,2,3,4 or more a plurality of, P type epitaxial loayer 2 cut be positioned at source 3 and P type contact hole 9 below be provided with P type trap 12.
Claims (3)
1, a kind of many current potentials field plate high-pressure N-type metal oxide semiconductor tube that relates to high tension apparatus, by N type substrate (1), P type epitaxial loayer (2), source (3), leak (4), polysilicon gate (5), field oxide (6) and oxide layer (8) are formed, P type epitaxial loayer (2) is located at the top of N type substrate (1), field oxide (6) is positioned at source (3) and leaks between (4), source (3), leak (4), polysilicon gate (5) and field oxide (6) are positioned at the top of P type epitaxial loayer (2), between polysilicon gate (5) and P type epitaxial loayer (2), be provided with gate oxide (7), oxide layer (8) is positioned at source (3), leak (4), the top of polysilicon gate (5) and field oxide (6), in P type epitaxial loayer (2) top, the below of oxide layer (8) and be positioned at source (3) and field oxide (6) between be provided with P type contact hole (9), in polysilicon gate (5), be respectively equipped with metallic aluminium lead-in wire (13 in source (3) and the leakage (4), 14 and 15), it is characterized in that the top of field oxide (6) and be positioned at leakage (4) and polysilicon gate (5) between be provided with polysilicon field plate (10), this polysilicon field plate (10) with leak (4) and be connected.
2, many current potentials field plate high-pressure N-type metal oxide semiconductor tube according to claim 1, it is characterized in that the top of field oxide (6) and be positioned at polysilicon field plate (10) and polysilicon gate (5) between be provided with the polysilicon field plate (11) of floating.
3, many current potentials field plate high-pressure N-type metal oxide semiconductor tube according to claim 1 and 2 is characterized in that cutting the below that is positioned at source (3) and P type contact hole (9) at P type epitaxial loayer (2) is provided with P type trap (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200420062099XU CN2743978Y (en) | 2004-06-24 | 2004-06-24 | Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200420062099XU CN2743978Y (en) | 2004-06-24 | 2004-06-24 | Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2743978Y true CN2743978Y (en) | 2005-11-30 |
Family
ID=35633995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200420062099XU Expired - Fee Related CN2743978Y (en) | 2004-06-24 | 2004-06-24 | Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2743978Y (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324717C (en) * | 2004-06-24 | 2007-07-04 | 东南大学 | Multi electric potential field plate lateral high voltage N type MOS transistor |
| CN103187443A (en) * | 2011-12-30 | 2013-07-03 | 无锡华润上华半导体有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor |
| CN103579313A (en) * | 2012-08-10 | 2014-02-12 | 上海华虹Nec电子有限公司 | Structure for improving breakdown voltages of high-voltage LDMOS device |
| CN105789051A (en) * | 2014-12-24 | 2016-07-20 | 北大方正集团有限公司 | LDMOS (laterally diffused metal oxide semiconductor) transistor and manufacturing method therefor |
| CN116960183A (en) * | 2023-07-27 | 2023-10-27 | 荣芯半导体(淮安)有限公司 | Semiconductor device including LDMOS transistor |
-
2004
- 2004-06-24 CN CNU200420062099XU patent/CN2743978Y/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324717C (en) * | 2004-06-24 | 2007-07-04 | 东南大学 | Multi electric potential field plate lateral high voltage N type MOS transistor |
| CN103187443A (en) * | 2011-12-30 | 2013-07-03 | 无锡华润上华半导体有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor |
| CN103187443B (en) * | 2011-12-30 | 2016-06-01 | 无锡华润上华半导体有限公司 | Cross bimoment |
| CN103579313A (en) * | 2012-08-10 | 2014-02-12 | 上海华虹Nec电子有限公司 | Structure for improving breakdown voltages of high-voltage LDMOS device |
| CN105789051A (en) * | 2014-12-24 | 2016-07-20 | 北大方正集团有限公司 | LDMOS (laterally diffused metal oxide semiconductor) transistor and manufacturing method therefor |
| CN116960183A (en) * | 2023-07-27 | 2023-10-27 | 荣芯半导体(淮安)有限公司 | Semiconductor device including LDMOS transistor |
| CN116960183B (en) * | 2023-07-27 | 2024-05-17 | 荣芯半导体(淮安)有限公司 | Semiconductor device including LDMOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101964344B (en) | Panel display driving chip based on silicon on insulator (SOI) and preparation method thereof | |
| CN108091685A (en) | It is a kind of to improve half pressure-resistant super node MOSFET structure and preparation method thereof | |
| CN1212674C (en) | Transverse buffer P-type MOS transistors | |
| CN107123684A (en) | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor | |
| CN101777581B (en) | P-type super-junction laterally double diffused metal oxide semiconductor | |
| CN207183281U (en) | A kind of groove grid super node semiconductor devices of adjustable switch speed | |
| CN109888002A (en) | Normally-off gallium nitride field effect transistor with super junction gate structure and manufacturing method thereof | |
| CN2743978Y (en) | Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate | |
| CN113066865B (en) | Semiconductor device for reducing switching loss and manufacturing method thereof | |
| CN106158927A (en) | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method | |
| CN101587901B (en) | Flat panel display driver chip of silicon materials on insulator and method for preparing the same | |
| CN208422922U (en) | A kind of groove grid super node semiconductor devices optimizing switching speed | |
| CN1324717C (en) | Multi electric potential field plate lateral high voltage N type MOS transistor | |
| CN110544722A (en) | gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor | |
| CN1996616A (en) | Thick-bar high-voltage P type MOS tube and its preparing method | |
| CN116013960A (en) | Groove type MOSFET cell structure and preparation method thereof | |
| CN2836241Y (en) | Integrated high-voltage P-type LDMOS transistor structure | |
| CN113410299B (en) | High-voltage-resistance n-channel LDMOS device and preparation method thereof | |
| CN1208839C (en) | Built-in protetive N-type high-voltage MOS transistors | |
| CN208923149U (en) | A kind of N-type LDMOS device | |
| CN208045508U (en) | The high-power groove MOS field-effect tube of high-frequency | |
| CN210723041U (en) | High-voltage-resistant high-EMI super-junction MOSFET chip | |
| CN210467853U (en) | High-voltage-resistant shielding grid power MOSFET chip | |
| CN109817711A (en) | Gallium nitride lateral transistor and preparation method thereof with AlGaN/GaN hetero-junctions | |
| CN215771155U (en) | Vertical double-diffusion MOS with high avalanche tolerance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |