CN108091685A - It is a kind of to improve half pressure-resistant super node MOSFET structure and preparation method thereof - Google Patents
It is a kind of to improve half pressure-resistant super node MOSFET structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000001413 cellular effect Effects 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 110
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 93
- 229920005591 polysilicon Polymers 0.000 claims description 75
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000012010 growth Effects 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 230000033228 biological regulation Effects 0.000 claims description 3
- 230000009647 facial growth Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
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- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The present invention provides half pressure-resistant super node MOSFET structure of a kind of raising and preparation method thereof, half super node MOSFET structure includes at least one transistor unit, and the transistor unit includes the first conductivity type substrate and the first conduction type drift layer above first conductivity type substrate；Cellular groove is set in the first conduction type drift layer, shielded gate structures are set in cellular groove, in the slot bottom of cellular groove, one or more second conduction type island areas are set, the second conduction type island area of vertical array and the top is contacted with the slot bottom of cellular groove successively on the second conduction type island area, the depth of groove can be effectively increased using the second conduction type island area and the first conduction type auxiliary layer, optimize the slot bottom doping of cellular groove, the voltage endurance capability of MOSFET element can be further improved, the conduction voltage drop of device can be reduced using the shielded gate structures of upper part, this design is compatible with existing process, securely and reliably.
Description
Technical field
It is especially a kind of to improve half pressure-resistant super node MOSFET structure and its preparation the present invention relates to a kind of MOSFET element
Method belongs to the technical field of semiconductor devices.
Background technology
VDMOSFET（High-voltage power MOSFET）Conducting resistance can be reduced by the way that the thickness of drain terminal drift region is thinned, so
And the breakdown voltage that the thickness that drain terminal drift region is thinned may result in device reduces, therefore in VDMOSFET, improve device
Breakdown voltage and the conducting resistance for reducing device are two conflicting aspects, and half super node MOSFET structure uses draws in the trench
Two vertical polycrystalline field versions are entered, this not only causes device to introduce two new peak electric fields in drift region, increases
The breakdown voltage of device, and device is caused vertically to leak the accumulation layer for foring one layer of concentration bigger around field plate, so as to reduce
Conducting resistance.Since existing vertical field plate to influence devices switch speed between this new device longitudinal direction grid, leakage field plate
The gate drain capacitance value of degree is partially converted into the gate-source capacitance and drain source capacitance of device, so that N-type region is under high-dopant concentration
It realizes high breakdown voltage, so as to obtain low on-resistance and high-breakdown-voltage simultaneously, breaks conventional power MOSFET electric conductions
The theoretical limit of resistance.
Half super node MOSFET structure is low with conduction loss, and gate charge is low, and switching speed is fast, and device heating is small, efficiency
The advantages of high, product can be widely used for PC, laptop, net book or mobile phone, illumination（High-voltage gas discharging light）
Product and television set（Liquid crystal or plasma TV）With the power supply or adapter of the high-end consumption electronic product such as game machine.
It is pressure-resistant mainly to be undertaken by the thick oxygen column of the gate structure below deep groove structure for half super node MOSFET knot,
But the limitation of technological ability, often limit the development continued toward high pressure/super-pressure direction.
Therefore it provides a kind of half super node MOSFET structure and preparation method thereof, further to promote high-voltage MOSFET device
Voltage endurance capability is necessary.
The content of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, provide a kind of half pressure-resistant super node MOSFET of raising
Structure and preparation method thereof, it is compact-sized, the voltage endurance capability of MOSFET element can be further improved, it is compatible with existing process,
Securely and reliably.
The present invention provide the technical solution adopted is that：It is a kind of to improve half pressure-resistant super node MOSFET structure, including at least one
A transistor unit, the transistor unit include the first conductivity type substrate and above first conductivity type substrates
The first conduction type drift layer；Cellular groove in the first conduction type drift layer is set, shielding is set in cellular groove
Grid structure；Top is equipped with the second conduction type base region and in second conduction type base region outside cellular trenched side-wall
First conduction type source region；The underface of the cellular groove slot bottom sets at least one second conduction type island area, and described the
Two conduction type islands area are located in the first conduction type drift layer, successively the second conduction type island area of vertical array and the top
It is contacted with the slot bottom of cellular groove.
Further, when the slot bottom of cellular groove has multiple second conduction type island areas, the second conduction type island
Area is arranged in order in cellular beneath trenches along the direction of the first conduction type drift layer the first conductivity type substrate of direction, and second
Conduction type island section adjoins each other；The width on the second conduction type island area is not less than the width of cellular groove.
Further, the depth of the cellular groove is 3 μm ~ 6 μm, and each second conduction type island area is in the first conductive-type
Depth in type drift layer is 1 μm ~ 20 μm.
Further, first conductivity type substrate is equipped with the first conductive-type with first conduction type drift interlayer
Type auxiliary layer, the first conduction type auxiliary layer abut the first conductivity type substrate and the first conduction type drift layer respectively,
The thickness of first conduction type auxiliary layer is 10 μm ~ 20 μm.
Further, the shielded gate structures include lower floor's polysilicon body and grooved surface upper strata polysilicon body in groove, institute
State the outer ring of lower floor's polysilicon body in groove by side wall and the bottom wall insulation of lower insulating oxide in groove and cellular groove every
From the outer ring of grooved surface upper strata polysilicon body passes through lower floor in the side wall and groove of insulating oxide on grooved surface and cellular groove
Polysilicon body is dielectrically separated from, and the width of grooved surface upper strata polysilicon body is more than the width of lower floor's polysilicon body in groove.
Further, the gate metal above the first conduction type drift layer and described grooved surface upper strata polysilicon body ohm
It contacts, the source metal above the first conduction type drift layer and second conduction type base region, the first conduction type source region
With lower floor's polysilicon body Ohmic contact in groove.
Further, a kind of preparation method for improving half pressure-resistant super node MOSFET structure includes the following steps：
Step 1：The semiconductor substrate with the first conduction type is provided, the semiconductor substrate includes the first conductivity type substrate
With first the first epitaxial layer of conduction type above first conductivity type substrate, in first conduction type first
The injection of the second conductive type impurity ion is carried out in epitaxial layer, to obtain the second required conduction type island area；
Step 2：The first conductive type epitaxial layer growth is carried out above first conductivity type substrate, to obtain being located at first
The first conduction type drift layer above conductivity type substrate, performs etching the first conduction type drift layer, to obtain
Cellular groove in the first conduction type drift layer；
Step 3：Required shielded gate structures are prepared in the cellular groove；
Step 4：The injection of the second conductive type impurity ion is carried out on the first conduction type drift layer, after diffusion formed with it is right
The second conduction type base region that cellular groove lateral wall is answered to contact；
Step 5：The injection of the first conductive type impurity ion is carried out on the first conduction type drift layer, is formed after diffusion
The the first conduction type source region contacted with the side wall of cellular groove；
Step 6：Required source metal and gate metal, the source electrode gold are set on the first conduction type drift layer
Belong to, gate metal is dielectrically separated from the first conduction type drift layer.
Further, it is conductive first when multiple second conduction type island areas are set in the first conduction type drift layer
After the second conduction type island area is obtained in the first epitaxial layer of type, first is carried out on first epitaxial layer of the first conduction type
Conductive type epitaxial layer is grown, to obtain first the second epitaxial layer of conduction type；In first the second epitaxial layer of conduction type into
The injection of row the second conductive type impurity ion, to obtain two the second adjacent conduction type island areas, the second of two adjoinings lead
It arranges in the direction that electric type island area is directed toward first the second epitaxial layer of conduction type along the first conductivity type substrate；Repeat above-mentioned step
Suddenly, until obtaining the second required conduction type island area in the first conduction type drift layer.
Further, the process of step 3 preparation shielded gate structures is as follows：
Step 3-1：First groove insulating oxide, the first groove insulating oxide covering are filled in the cellular groove
The side wall and bottom wall of cellular groove, and the first polysilicon filling hole is formed in cellular groove；
Step 3-2：Conductive polycrystalline silicon is filled in first polysilicon filling hole, is filled out with obtaining filling up the first conductive polycrystalline silicon
Fill the polysilicon obturator in hole；
Step 3-3：The polysilicon obturator is performed etching, to obtain lower floor's polysilicon in the groove being located in cellular groove
Body and the etching location hole directly over polysilicon body in the groove；
Step 3-4：Full etching is carried out to the first groove insulating oxide of the etching location hole outer ring, with obtain in groove
Insulating oxide is descended in the corresponding groove of lower floor's polysilicon body and positioned at the upper tank body in groove directly over lower floor's polysilicon body；
Step 3-5：Second groove insulating oxide, the second groove insulating oxide covering are filled in the upper tank body
The side wall and bottom wall at upper slot bottom, after second groove insulating oxide is filled, by mechanical milling tech by the of silicon face
Two insulating oxides go all to carve；
Step 3-6：The second conductive polycrystalline silicon filling hole is formed directly over lower floor's polysilicon body in the trench；It is conductive described second
Polysilicon filling fills conductive polycrystalline silicon in hole, to obtain filling up the grooved surface upper strata polysilicon in the second conductive polycrystalline silicon filling hole
Body, second groove insulating oxide corresponding with grooved surface upper strata polysilicon body form insulating oxide on grooved surface；
Step 3-7：In three channel insulation oxide layer of silicon face growth regulation；And in the 3rd channel insulation oxidation layer surface growth
Polysilicon, self-defined etching window etch away the polysilicon and the 3rd channel insulation oxide layer on both sides, retain intermediate one piece of polycrystalline
Silicon and the 3rd channel insulation oxide layer.
Further, the material of semiconductor substrate includes silicon.
The invention has the advantages that：Shielded gate structures in cellular groove are set, are set in the slot bottom of cellular groove
One or more second conduction type island areas, the second conduction type island area second conduction type of vertical array and the top successively
Island area is contacted with the slot bottom of cellular groove, can be effectively increased using the second conduction type island area and the first conduction type auxiliary layer
The depth of groove, the slot bottom doping of optimization cellular groove, can further improve the voltage endurance capability of MOSFET element, utilize upper part
Shielded gate structures can reduce the conduction voltage drop of device, it is compatible with existing process, securely and reliably.In addition, second layer polysilicon
For the structure of plane, cellular raceway groove is horizontal structure, to technological ability requirement than relatively low.
Description of the drawings
In " first conduction type " and " the second conduction type " the two, led for N-type power MOSFET device, first
Electric type refers to N-type, and the second conduction type is p-type；For p-type power MOSFET device, the first conduction type and the second conductive-type
The type and N-type semiconductor device of type meaning are exactly the opposite.
Fig. 1 is the structural diagram of the present invention.
Fig. 2 ~ Figure 15 is specific implementation process step sectional view of the present invention；Wherein：
Fig. 2 obtains the sectional view in the first GePXing Dao areas for the present invention；
Fig. 3 obtains the sectional view in the second GePXing Dao areas for the present invention；
Fig. 4 obtains the sectional view after cellular groove for the present invention；
Fig. 5 is that the present invention obtains the sectional view behind the first polysilicon filling hole；
Fig. 6 obtains the sectional view after polysilicon obturator for the present invention；
Fig. 7 is that the present invention obtains the sectional view after etching location hole；
Fig. 8 obtains the sectional view after upper tank body for the present invention；
Fig. 9 is that the second insulating oxide is removed the sectional view after all carving by the present invention；
Figure 10 obtains the sectional view after the 3rd insulating oxide for the present invention；
Figure 11 is that the present invention obtains the sectional view behind the second polysilicon filling hole；
Figure 12 obtains the sectional view after the polysilicon body of grooved surface upper strata for the present invention；
Figure 13 obtains the sectional view behind p-type base for the present invention；
Figure 14 obtains the sectional view after N+ source regions for the present invention；
Figure 15 obtains the sectional view after source metal and gate metal for the present invention.
Reference sign：201-N+ substrates, 202-N types auxiliary layer, 203-N types drift layer, 204-P Xing Dao areas, 205-
Lower floor's polysilicon body in groove interior insulation oxide layer, 206- grooves, 207-P types base, 208-N+ source regions, on 209- grooved surfaces absolutely
Edge oxide layer, 210- grooved surfaces upper strata polysilicon body, 211- gate metals, 212- source metals, 213- cellular grooves.
Specific embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in the figure, a kind of improve half pressure-resistant super node MOSFET structure, including at least one transistor unit, the crystalline substance
Body pipe unit includes the first conductivity type substrate and the first conduction type drift above first conductivity type substrate
Layer；Cellular groove in the first conduction type drift layer is set, shielded gate structures are set in cellular groove；In cellular channel side
The outer top of wall is equipped with the second conduction type base region and the first conduction type source region in second conduction type base region；Institute
The underface for stating cellular groove slot bottom sets at least one second conduction type island area, and the second conduction type island area is located at the
In one conduction type drift layer, the second conduction type island area and the slot bottom of cellular groove of vertical array and the top connect successively
It touches.
When the slot bottom of cellular groove has multiple second conduction type island areas, the second conduction type island area is in cellular ditch
The direction for being directed toward the first conductivity type substrate below slot along the first conduction type drift layer is arranged in order, and the second conduction type island
Section adjoins each other；The width on the second conduction type island area is not less than the width of cellular groove.
The depth of the cellular groove is 3 μm ~ 6 μm, and each second conduction type island area is in the first conduction type drift layer
Interior depth is 1 μm ~ 20 μm.
First conductivity type substrate is equipped with the first conduction type auxiliary layer with first conduction type drift interlayer,
The first conduction type auxiliary layer abuts the first conductivity type substrate and the first conduction type drift layer, the first conductive-type respectively
The thickness of type auxiliary layer is 10 μm ~ 20 μm.
The shielded gate structures include lower floor's polysilicon body and grooved surface upper strata polysilicon body in groove, under the groove is interior
The outer ring of layer polysilicon body is dielectrically separated from by the side wall and bottom wall of lower insulating oxide and cellular groove in groove, on grooved surface
The outer ring of layer polysilicon body is exhausted by insulating oxide on grooved surface and lower floor's polysilicon body in the side wall and groove of cellular groove
Edge is isolated, and the width of grooved surface upper strata polysilicon body is more than the width of lower floor's polysilicon body in groove.
Gate metal and the grooved surface upper strata polysilicon body Ohmic contact above first conduction type drift layer, first
Under in source metal and second conduction type base region, the first conduction type source region and groove above conduction type drift layer
Layer polysilicon body Ohmic contact.
A kind of preparation method for improving half pressure-resistant super node MOSFET structure includes the following steps：
Step 1：The semiconductor substrate with the first conduction type is provided, the semiconductor substrate includes the first conductivity type substrate
With first the first epitaxial layer of conduction type above first conductivity type substrate, in first conduction type first
The injection of the second conductive type impurity ion is carried out in epitaxial layer, to obtain the second required conduction type island area；
Step 2：The first conductive type epitaxial layer growth is carried out above first conductivity type substrate, to obtain being located at first
The first conduction type drift layer above conductivity type substrate, performs etching the first conduction type drift layer, to obtain
Cellular groove in the first conduction type drift layer；
Step 3：Required shielded gate structures are prepared in the cellular groove；
Step 4：The injection of the second conductive type impurity ion is carried out on the first conduction type drift layer, after diffusion formed with it is right
The second conduction type base region that cellular groove lateral wall is answered to contact；
Step 5：The injection of the first conductive type impurity ion is carried out on the first conduction type drift layer, is formed after diffusion
The the first conduction type source region contacted with the side wall of cellular groove；
Step 6：Required source metal and gate metal, the source electrode gold are set on the first conduction type drift layer
Belong to, gate metal is dielectrically separated from the first conduction type drift layer.
When multiple second conduction type island areas are set in the first conduction type drift layer, outside the first conduction type first
Prolong after the second conduction type island area is obtained in floor, carried out on first epitaxial layer of the first conduction type outside the first conduction type
Prolong layer growth, to obtain first the second epitaxial layer of conduction type；It is conductive that second is carried out in first the second epitaxial layer of conduction type
The injection of type dopant ion, to obtain two the second adjacent conduction type island areas, the second conduction type island area of two adjoinings
It arranges in the direction that first the second epitaxial layer of conduction type is directed toward along the first conductivity type substrate；It repeats the above steps, until the
The second required conduction type island area is obtained in one conduction type drift layer.
The process that step 3 prepares shielded gate structures is as follows：
Step 3-1：First groove insulating oxide, the first groove insulating oxide covering are filled in the cellular groove
The side wall and bottom wall of cellular groove, and the first polysilicon filling hole is formed in cellular groove；
Step 3-2：Conductive polycrystalline silicon is filled in first polysilicon filling hole, is filled out with obtaining filling up the first conductive polycrystalline silicon
Fill the polysilicon obturator in hole；
Step 3-3：The polysilicon obturator is performed etching, to obtain lower floor's polysilicon in the groove being located in cellular groove
Body and the etching location hole directly over polysilicon body in the groove；
Step 3-4：Full etching is carried out to the first groove insulating oxide of the etching location hole outer ring, with obtain in groove
Insulating oxide is descended in the corresponding groove of lower floor's polysilicon body and positioned at the upper tank body in groove directly over lower floor's polysilicon body；
Step 3-5：Second groove insulating oxide, the second groove insulating oxide covering are filled in the upper tank body
The side wall and bottom wall at upper slot bottom, after second groove insulating oxide is filled, by mechanical milling tech by the of silicon face
Two insulating oxides go all to carve；
Step 3-6：The second conductive polycrystalline silicon filling hole is formed directly over lower floor's polysilicon body in the trench；It is conductive described second
Polysilicon filling fills conductive polycrystalline silicon in hole, to obtain filling up the grooved surface upper strata polysilicon in the second conductive polycrystalline silicon filling hole
Body, second groove insulating oxide corresponding with grooved surface upper strata polysilicon body form insulating oxide on grooved surface；
Step 3-7：In three channel insulation oxide layer of silicon face growth regulation；And in the 3rd channel insulation oxidation layer surface growth
Polysilicon, self-defined etching window etch away the polysilicon and the 3rd channel insulation oxide layer on both sides, retain intermediate one piece of polycrystalline
Silicon and the 3rd channel insulation oxide layer.
The material of semiconductor substrate includes silicon.
When setting multiple transistor units in N-type drift layer, in concrete technology, in same step, increase more
A cellular groove and corresponding PXing Dao areas design, i.e., form multiple PXing Dao areas and multiple corresponding cellulars in same step
Groove, multiple transistor units are connected with each other integrally by source metal, are specifically interconnected to multiple transistor units
The mode and technique of one are known to those skilled in the art, and details are not described herein again.
The present invention can also have other embodiments, without deviating from the spirit and substance of the present invention, be familiar with this field
Technical staff make various corresponding changes and deformation in accordance with the present invention, but these corresponding change and deformation should all belong to
In the protection domain of appended claims of the invention.For example, with reference to the present embodiment, by the materials conductive type in each area or position
It is N<—>The MOSFET element that the exchange of P is formed, it is understood that the equivalent technical solutions of appended claims of the present invention.
Claims (10)
1. a kind of improve half pressure-resistant super node MOSFET structure, including at least one transistor unit, the transistor unit bag
Include the first conductivity type substrate and the first conduction type drift layer above first conductivity type substrate；Described first
Cellular groove in conduction type drift layer is set, shielded gate structures are set in cellular groove；Top is set outside cellular trenched side-wall
There are the second conduction type base region and the first conduction type source region in second conduction type base region；It is characterized in that：
The underface of the cellular groove slot bottom sets at least one second conduction type island area, and the second conduction type island area is located at
In first conduction type drift layer, the second conduction type island area and the slot bottom of cellular groove of vertical array and the top connect successively
It touches.
2. the half super node MOSFET structure that a kind of raising according to claim 1 is pressure-resistant, it is characterised in that：Cellular groove
When slot bottom has multiple second conduction type island areas, the second conduction type island area is in cellular beneath trenches along the first conductive-type
The direction that type drift layer is directed toward the first conductivity type substrate is arranged in order, and the second conduction type island section adjoins each other；Second
The width in conduction type island area is not less than the width of cellular groove.
3. the half super node MOSFET structure that a kind of raising according to claim 1 is pressure-resistant, it is characterised in that：The cellular ditch
The depth of slot is 3 μm ~ 6 μm, and depth of each second conduction type island area in the first conduction type drift layer is 1 μm ~ 20 μm.
4. the half super node MOSFET structure that a kind of raising according to claim 1 is pressure-resistant, it is characterised in that：Described first leads
Electric type substrates are equipped with the first conduction type auxiliary layer with first conduction type drift interlayer, and first conduction type is auxiliary
Layer is helped to abut the first conductivity type substrate and the first conduction type drift layer respectively, the thickness of the first conduction type auxiliary layer is 10
μm~20μm。
5. the half super node MOSFET structure that a kind of raising according to claim 1 is pressure-resistant, it is characterised in that：The shield grid
Structure includes lower floor's polysilicon body and grooved surface upper strata polysilicon body in groove, and the outer ring of lower floor's polysilicon body leads in the groove
The side wall and bottom wall for crossing lower insulating oxide and cellular groove in groove are dielectrically separated from, and the outer ring of grooved surface upper strata polysilicon body leads to
It crosses insulating oxide on grooved surface to be dielectrically separated from lower floor's polysilicon body in the side wall and groove of cellular groove, grooved surface upper strata is more
The width of crystal silicon body is more than the width of lower floor's polysilicon body in groove.
6. a kind of according to claim 1 or 5 improve half pressure-resistant super node MOSFET structure, it is characterised in that：First leads
Gate metal and the grooved surface upper strata polysilicon body Ohmic contact above electric type drift layer, the first conduction type drift layer
The source metal of top and lower floor's polysilicon body ohm in second conduction type base region, the first conduction type source region and groove
Contact.
7. a kind of preparation method for improving half pressure-resistant super node MOSFET structure, it is characterised in that：Include the following steps：
Step 1：The semiconductor substrate with the first conduction type is provided, the semiconductor substrate includes the first conductivity type substrate
With first the first epitaxial layer of conduction type above first conductivity type substrate, in first conduction type first
The injection of the second conductive type impurity ion is carried out in epitaxial layer, to obtain the second required conduction type island area；
Step 2：The first conductive type epitaxial layer growth is carried out above first conductivity type substrate, to obtain being located at first
The first conduction type drift layer above conductivity type substrate, performs etching the first conduction type drift layer, to obtain
Cellular groove in the first conduction type drift layer；
Step 3：Required shielded gate structures are prepared in the cellular groove；
Step 4：The injection of the second conductive type impurity ion is carried out on the first conduction type drift layer, after diffusion formed with it is right
The second conduction type base region that cellular groove lateral wall is answered to contact；
Step 5：The injection of the first conductive type impurity ion is carried out on the first conduction type drift layer, is formed after diffusion
The the first conduction type source region contacted with the side wall of cellular groove；
Step 6：Required source metal and gate metal, the source electrode gold are set on the first conduction type drift layer
Belong to, gate metal is dielectrically separated from the first conduction type drift layer.
8. a kind of preparation method for improving half pressure-resistant super node MOSFET structure according to claim 7, it is characterised in that：
When multiple second conduction type island areas are set in the first conduction type drift layer, in first the first epitaxial layer of conduction type
To after the second conduction type island area, the first conductive type epitaxial layer life is carried out on first epitaxial layer of the first conduction type
It is long, to obtain first the second epitaxial layer of conduction type；It is miscellaneous that the second conduction type is carried out in first the second epitaxial layer of conduction type
The injection of matter ion, to obtain two the second adjacent conduction type island areas, the second conduction type island areas of two adjoinings are along first
Conductivity type substrate is directed toward the direction arrangement of first the second epitaxial layer of conduction type；It repeats the above steps, until conductive first
The second required conduction type island area is obtained in type drift layer.
9. a kind of preparation method for improving half pressure-resistant super node MOSFET structure according to claim 7, it is characterised in that：
The process that step 3 prepares shielded gate structures is as follows：
Step 3-1：First groove insulating oxide, the first groove insulating oxide covering are filled in the cellular groove
The side wall and bottom wall of cellular groove, and the first polysilicon filling hole is formed in cellular groove；
Step 3-2：Conductive polycrystalline silicon is filled in first polysilicon filling hole, is filled out with obtaining filling up the first conductive polycrystalline silicon
Fill the polysilicon obturator in hole；
Step 3-3：The polysilicon obturator is performed etching, to obtain lower floor's polysilicon in the groove being located in cellular groove
Body and the etching location hole directly over polysilicon body in the groove；
Step 3-4：Full etching is carried out to the first groove insulating oxide of the etching location hole outer ring, with obtain in groove
Insulating oxide is descended in the corresponding groove of lower floor's polysilicon body and positioned at the upper tank body in groove directly over lower floor's polysilicon body；
Step 3-5：Second groove insulating oxide, the second groove insulating oxide covering are filled in the upper tank body
The side wall and bottom wall at upper slot bottom, after second groove insulating oxide is filled, by mechanical milling tech by the of silicon face
Two insulating oxides go all to carve；
Step 3-6：The second conductive polycrystalline silicon filling hole is formed directly over lower floor's polysilicon body in the trench；It is conductive described second
Polysilicon filling fills conductive polycrystalline silicon in hole, to obtain filling up the grooved surface upper strata polysilicon in the second conductive polycrystalline silicon filling hole
Body, second groove insulating oxide corresponding with grooved surface upper strata polysilicon body form insulating oxide on grooved surface；
Step 3-7：In three channel insulation oxide layer of silicon face growth regulation；And in the 3rd channel insulation oxidation layer surface growth
Polysilicon, self-defined etching window etch away the polysilicon and the 3rd channel insulation oxide layer on both sides, retain intermediate one piece of polycrystalline
Silicon and the 3rd channel insulation oxide layer.
10. a kind of preparation method for improving half pressure-resistant super node MOSFET structure according to claim 7, feature exist
In：The material of semiconductor substrate includes silicon.
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| CN110459612A (en) * | 2019-08-19 | 2019-11-15 | 无锡橙芯微电子科技有限公司 | High-tension shielding gate MOSFET and production method with chinampa structure |
| CN111509049A (en) * | 2020-03-19 | 2020-08-07 | 娜美半导体有限公司 | Shielding gate groove type metal oxide semiconductor field effect transistor |
| CN112185957A (en) * | 2020-05-08 | 2021-01-05 | 娜美半导体有限公司 | SGT MOSFET of integrated SBR |
| CN117253905A (en) * | 2023-11-13 | 2023-12-19 | 深圳天狼芯半导体有限公司 | SiC device with floating island structure and preparation method thereof |
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