CN107731926B - MOSFET device with improved voltage withstanding range and preparation method thereof - Google Patents
MOSFET device with improved voltage withstanding range and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention relates to a MOSFET device and a preparation method thereof, in particular to a MOSFET device for improving the withstand voltage range and a preparation method thereof, belonging to the technical field of semiconductor devices. The active cells of the cell area adopt a trench structure, a plurality of terminal trenches are arranged in the terminal protection area, the depth of each terminal trench is greater than that of each cell trench, and the conductive polycrystalline silicon of each terminal trench is insulated and isolated from the side walls and the bottom walls of the terminal trenches through terminal trench insulation oxidation layers; the terminal groove adjacent to the cell area is contacted with the second conductive type base region above the outer side wall of the cell groove adjacent to the terminal protection area, so that the voltage-resistant range can be effectively improved, and the method is compatible with the prior art, safe and reliable.
Description
Technical Field
The invention relates to a MOSFET device and a preparation method thereof, in particular to a MOSFET device for improving the withstand voltage range and a preparation method thereof, belonging to the technical field of semiconductor devices.
Background
The VDMOSFET (high-voltage power MOSFET) can reduce the on-resistance by reducing the thickness of the drain end drift region, however, the reduction of the thickness of the drain end drift region can reduce the breakdown voltage of a device, so in the VDMOSFET, the improvement of the breakdown voltage of the device and the reduction of the on-resistance of the device are a pair of contradictions, two vertical polycrystalline field plates are introduced into a groove in the shielding grid MOSFET structure, two new electric field peak values are introduced into the drift region of the device, the Breakdown Voltage (BV) of the device is increased, an accumulation layer with higher concentration is formed around the vertical drain field plate of the device, and the on-resistance is reduced. The vertical field plate between the longitudinal grid and the drain field plate of the novel device enables the grid-drain capacitance value which influences the switching speed of the device to be partially converted into the grid-source capacitance and the drain-source capacitance of the device, so that the N-type region can realize high breakdown voltage under high doping concentration, low on-resistance and high breakdown voltage can be obtained at the same time, and the theoretical limit of the on-resistance of the traditional power MOSFET can be broken.
The shielding grid MOSFET structure has the advantages of low conduction loss, low grid charge, high switching speed, small device heating and high energy efficiency, and can be widely applied to power supplies or adapters of high-end consumer electronics products such as personal computers, notebook computers, netbooks or mobile phones, lighting (high-pressure gas discharge lamp) products, televisions (liquid crystal or plasma televisions) and game machines.
For the shielded gate MOSFET junction, the withstand voltage is mainly born by the thick oxygen column of the gate structure below the deep trench structure, but the process capability limitation often limits the continuous development towards the high voltage/ultrahigh voltage direction.
Therefore, it is necessary to provide a shielded gate MOSFET structure and a method for fabricating the same to further improve the voltage endurance of the high voltage MOSFET device.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide the MOSFET device with the improved voltage withstanding range, which has a compact structure, can effectively improve the voltage withstanding range, is compatible with the prior art, and is safe and reliable.
According to the technical scheme provided by the invention, the MOSFET device with the improved withstand voltage range comprises a cellular area and a terminal protection area, wherein the cellular area is positioned on a semiconductor substrate, the cellular area is positioned in the central area of the semiconductor substrate, the terminal protection area is positioned on the outer ring of the cellular area, and the terminal protection area surrounds and surrounds the cellular area; the semiconductor substrate comprises a first conductive type substrate and a first conductive type drift layer positioned above the first conductive type substrate; active cells in the cell area adopt a groove structure, and a groove gate structure is arranged in the cell groove; a second conductive type base region is arranged above the outside of the side wall of the cellular trench, is positioned in the first conductive type drift layer and is contacted with the corresponding side wall of the cellular trench; arranging first conductive type source regions in the second conductive type base regions above and outside the side walls between the adjacent cell grooves, wherein the first conductive type source regions are contacted with the side walls of the corresponding cell grooves;
arranging a plurality of terminal grooves in the terminal protection region, wherein the terminal grooves are positioned in the first conduction type drift layer, and the depth of the terminal grooves in the first conduction type drift layer is greater than that of the cell grooves in the first conduction type drift layer; terminal conductive polycrystalline silicon is arranged in the terminal groove and is insulated and isolated from the side wall and the bottom wall of the terminal groove through a terminal groove insulating oxide layer; and the terminal groove adjacent to the cell area is contacted with the second conductive type base region above the outer side wall of the cell groove adjacent to the terminal protection area.
The trench gate structure in the cell trench comprises a shielding gate structure, the shielding gate structure comprises a lower polysilicon body in the trench and an upper polysilicon body in the trench, the outer ring of the lower polysilicon body in the trench is insulated and isolated from the side wall and the bottom wall of the cell trench through a lower insulating oxide layer in the trench, the outer ring of the upper polysilicon body in the trench is insulated and isolated from the side wall of the cell trench and the lower polysilicon body in the trench through an upper insulating oxide layer in the trench, and the width of the upper polysilicon body in the trench is greater than that of the lower polysilicon body in the trench;
an upper polycrystalline silicon body in the groove is in ohmic contact with the grid metal above the first conduction type drift layer, and a lower polycrystalline silicon body in the groove is in ohmic contact with the source metal above the first conduction type drift layer; the source electrode metal is in ohmic contact with a second conductive type base region which is arranged above the outside of the side wall between the adjacent cellular grooves and a first conductive type source region which is positioned in the second conductive type base region.
The depth of the cellular trench is 3-6 μm, and the thickness of the insulating oxide layer of the terminal trench is consistent with that of the lower insulating oxide layer in the trench.
And a first conduction type auxiliary layer is arranged between the first conduction type substrate and the first conduction type drift layer, the first conduction type auxiliary layer is respectively adjacent to the first conduction type substrate and the first conduction type drift layer, and the thickness of the first conduction type auxiliary layer is 10-20 mu m.
A preparation method of a MOSFET device for improving the withstand voltage range comprises the following steps:
step 1, providing a semiconductor substrate with a first conductivity type, wherein the semiconductor substrate comprises a first conductivity type substrate and a first conductivity type drift layer positioned above the first conductivity type substrate; selectively masking and etching the first conductive type drift layer to obtain a required cell trench and a terminal auxiliary trench in the first conductive type drift layer;
step 2, etching the terminal auxiliary groove again to obtain a required terminal groove, wherein the depth of the terminal groove is greater than that of the cellular groove, and the depth of the terminal groove is smaller than the thickness of the first conductive type drift layer;
step 3, performing a required trench gate preparation process on the cell trench to obtain a required trench gate structure in the cell trench, and obtaining terminal conductive polysilicon in the terminal trench when the trench gate structure is obtained by preparation, wherein the terminal trench conductive polysilicon is insulated and isolated from the side wall and the bottom wall of the terminal trench through a terminal trench insulating oxide layer;
step 4, injecting second conductive type impurity ions above the first conductive type drift layer, forming required second conductive type base regions on two sides of the cellular trench after diffusion, wherein the second conductive type base regions are in contact with the cellular trench, and the terminal trench adjacent to the cellular region is in contact with the second conductive type base region above the outer side wall of the cellular trench adjacent to the terminal protection region;
step 5, injecting first conductive type impurity ions above the first conductive type drift layer to obtain a first conductive type source region in a second conductive type base region which is positioned above and outside the side wall between adjacent cell grooves, wherein the first conductive type source region is contacted with the side wall of the corresponding cell groove;
and 6, depositing a metal layer above the first conductive type drift layer to obtain source metal and grid metal which are positioned above the first conductive type drift layer, wherein the source metal is in ohmic contact with the first conductive type source region and the second conductive type base region where the first conductive type source region is positioned, and the grid metal is electrically connected with the trench grid structure in the cell trench.
In step 3, when the prepared trench gate structure is a shielded gate structure, the specific process comprises the following steps:
step 3-1, simultaneously arranging a first groove insulating oxide layer in the cell groove and the terminal groove, wherein the first groove insulating oxide layer in the cell groove covers the side wall and the bottom wall of the cell groove, the first groove insulating oxide layer in the terminal groove covers the side wall and the bottom wall of the terminal groove, and after the first groove insulating oxide layer is arranged, a first polycrystalline silicon filling hole is formed in the cell groove and a terminal groove polycrystalline silicon filling hole is formed in the terminal groove;
step 3-2, conducting polycrystalline silicon deposition is carried out above the first conduction type drift layer, so that a cell polycrystalline silicon filling body filling the first polycrystalline silicon filling hole and terminal conducting polycrystalline silicon filling the terminal groove polycrystalline silicon filling hole are obtained; forming a terminal groove insulating oxide layer by the first groove insulating oxide layer corresponding to the terminal conductive polycrystalline silicon;
3-3, etching the cellular polysilicon filling body to obtain a lower-layer polysilicon body in the groove in the cellular groove and an etching positioning hole right above the lower-layer polysilicon body in the groove;
step 3-4, fully etching the first groove insulating oxide layer at the upper part in the cellular groove by using the etching positioning hole to obtain a lower groove insulating oxide layer corresponding to the lower layer polycrystalline silicon body in the groove and an upper groove body positioned right above the lower layer polycrystalline silicon body in the groove, wherein the width of the upper groove body is consistent with that of the cellular groove;
3-5, arranging a second groove insulating oxide layer in the upper groove body, wherein the second groove insulating oxide layer covers the side wall and the bottom of the upper groove body, and a second polycrystalline silicon filling hole is formed after the second groove insulating oxide layer is arranged in the upper groove body;
step 3-6, conducting polycrystalline silicon filling is carried out in the second polycrystalline silicon filling hole, so that an upper polycrystalline silicon body in the groove is obtained, the second groove insulation oxide layer corresponding to the upper polycrystalline silicon body in the groove forms an upper insulation oxide layer in the groove, and the upper polycrystalline silicon body in the groove is insulated and isolated from the side wall of the cellular groove and the lower polycrystalline silicon body in the groove through the upper insulation oxide layer in the groove; the width of the upper layer polysilicon body in the groove is larger than that of the lower layer polysilicon body in the groove;
the grid metal is in ohmic contact with the upper polysilicon body in the groove, and the source metal is in ohmic contact with the lower polysilicon body in the groove.
And a first conduction type auxiliary layer is arranged between the first conduction type substrate and the first conduction type drift layer, the first conduction type auxiliary layer is respectively adjacent to the first conduction type substrate and the first conduction type drift layer, and the thickness of the first conduction type auxiliary layer is 10-20 mu m.
The semiconductor substrate is made of silicon, and the depth of the cell groove is 3-6 microns.
In both the first conductivity type and the second conductivity type, for an N-type power MOSFET device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power MOSFET device, the first conductivity type and the second conductivity type refer to the opposite type of the N-type semiconductor device.
The invention has the advantages that: the active cells of the cell area adopt a trench structure, a plurality of terminal trenches are arranged in the terminal protection area, the depth of each terminal trench is greater than that of each cell trench, and the conductive polycrystalline silicon of each terminal trench is insulated and isolated from the side walls and the bottom walls of the terminal trenches through terminal trench insulation oxidation layers; the terminal groove adjacent to the cell area is contacted with the second conductive type base region above the outer side wall of the cell groove adjacent to the terminal protection area, so that the voltage-resistant range can be effectively improved, and the method is compatible with the prior art, safe and reliable.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
FIGS. 2-11 are cross-sectional views of process steps in accordance with an embodiment of the present invention, wherein
Fig. 2 is a cross-sectional view of the cell trench and the terminal auxiliary trench according to the present invention.
Fig. 3 is a cross-sectional view of the present invention after a termination trench has been formed.
Fig. 4 is a cross-sectional view of the first polysilicon fill hole and the termination trench polysilicon fill hole of the present invention.
Fig. 5 is a cross-sectional view of the cell polysilicon fill and the terminal conductive polysilicon of the present invention.
FIG. 6 is a cross-sectional view of the etched locating hole of the present invention.
Figure 7 is a cross-sectional view of the invention after the upper trough body has been obtained.
Fig. 8 is a cross-sectional view of the present invention after a first polysilicon fill hole is obtained.
FIG. 9 is a cross-sectional view of the resulting upper polysilicon body within a trench in accordance with the present invention.
Fig. 10 is a cross-sectional view after obtaining the N + source region according to the present invention.
Fig. 11 is a cross-sectional view of the source metal and the gate metal obtained by the present invention.
Description of reference numerals: 201-N + substrate, 202-N type auxiliary layer, 203-N type drift layer, 204-lower insulating oxide layer in trench, 205-lower polysilicon body in trench, 206-upper insulating oxide layer in trench, 207-upper polysilicon body in trench, 208-P type base region, 209-N + source region, 210-source metal, 211-gate metal, 212-cell trench, 213-terminal trench, 214-terminal trench insulating oxide, 215-terminal conductive polysilicon, 216-terminal auxiliary trench, 217-first trench insulating oxide, 218-first polysilicon fill hole, 219-terminal trench polysilicon fill hole, 220-cell polysilicon fill, 221-etch location hole, 222-upper trench body, and 223-second polysilicon fill hole.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1 and 11: in order to effectively improve the voltage withstanding range, taking an N-type MOSFET device as an example, the invention comprises a cellular area and a terminal protection area, wherein the cellular area is positioned on a semiconductor substrate, the cellular area is positioned in the central area of the semiconductor substrate, the terminal protection area is positioned on the outer ring of the cellular area, and the terminal protection area surrounds the cellular area; the semiconductor substrate comprises an N + substrate 201 and an N-type drift layer 203 positioned above the N + substrate 201; active cells in the cell area adopt a trench structure, and a trench gate structure is arranged in the cell trench 212; a P-type base region 208 is arranged above and outside the side wall of the cell trench 212, and the P-type base region 208 is positioned in the N-type drift layer 203 and is in contact with the corresponding side wall of the cell trench 212; n + source regions 209 are arranged in the P-type base regions 208 above and outside the side walls between the adjacent cell grooves 212, and the N + source regions 209 are in contact with the side walls of the corresponding cell grooves 212;
a plurality of terminal grooves 213 are arranged in the terminal protection region, the terminal grooves 213 are positioned in the N-type drift layer 203, and the depth of the terminal grooves 213 in the N-type drift layer 203 is greater than that of the cell grooves 212 in the N-type drift layer 203; a terminal conductive polysilicon 215 is arranged in the terminal trench 213, and the terminal trench conductive polysilicon 215 is insulated and isolated from the side wall and the bottom wall of the terminal trench 213 by a terminal trench insulating oxide layer 214; the terminal trench 213 adjacent to the cell region contacts the P-type base region 208 on the outer upper side of the sidewall of the cell trench 212 adjacent to the terminal protection region.
Specifically, the material of the semiconductor substrate may be silicon or other commonly used semiconductor materials, the cell region is located in a central region of the semiconductor substrate, the terminal protection region surrounds the cell region, and the specific functions and distribution positions of the cell region and the terminal protection region are consistent with those of the conventional power MOSFET device, which is not described herein again. The doping concentration of the N + substrate 201 in the semiconductor substrate is greater than that of the N-type drift layer 203, the active cells in the cell area adopt a trench structure, and the cell trenches 213 are arranged in the N-type drift layer 203.
A P-type base region 208 is arranged above and outside the sidewall of each cell trench 212, the P-type base region 208 extends vertically downwards from the upper surface of the N-type drift layer 203, and the P-type base region 208 is in contact with the outer sidewall of the cell trench 213. The N + source region 209 is disposed in the P-type base region 208 above the sidewall between the adjacent cell trenches 213, and the N + source region 209 and the P-type base region 208 are simultaneously in contact with the outer walls of the corresponding cell trenches 213. Therefore, for the cell trench 213 adjacent to the terminal protection region, there is no adjacent cell trench 213 on the side of the cell trench 213 adjacent to the terminal protection region, i.e., there is no N + source region 209 in the P-type base region 208 on the side of the cell trench 213 adjacent to the terminal protection region.
A plurality of terminal trenches 213 are disposed in the terminal protection region, and the number of the terminal trenches 213 can be selectively determined according to the requirement. The termination trench 213 is located in the N-type drift layer 203, the notch of the termination trench 213 and the notch of the cell trench 212 are located on the same horizontal plane, and the depth of the termination trench 213 is greater than the depth of the cell trench 212 in the N-type drift layer 203 and is smaller than the thickness of the N-type drift layer 203. A termination trench insulating oxide layer 214 and a termination conductive polysilicon body 215 are disposed in the termination trench 213, and the termination conductive polysilicon body 215 is insulated from the sidewalls and bottom wall of the termination trench 213 by the termination trench insulating oxide layer 214. The terminal trench 213 adjacent to the cell region is in contact with the P-type base region 208 above and outside the sidewall of the cell trench 212 adjacent to the terminal protection region, and the other terminal trenches 213 are independent from each other and are not associated with the cell region. The depth of the terminal trench 213 in the terminal protection region, the arrangement of the terminal conductive polysilicon 215 and the terminal trench insulating oxide layer 214 can effectively improve the voltage withstanding range, and expand the application field of the obtained MOSFET device.
The terminal conductive polysilicon 214 and the terminal trench insulating oxide layer 214 in the terminal trench 213 form a floating field plate, and after the depth of the terminal trench 213 is greater than that of the cell trench 212, the potential density distributed in the terminal trench insulating oxide layer 214 is reduced, thereby avoiding electric field concentration and improving voltage resistance. In general, the higher the withstand voltage, the faster the electric field laterally depletes, so more termination trenches 213 are required.
Further, the trench gate structure in the cell trench 212 includes a shield gate structure, the shield gate structure includes a trench inner lower polysilicon body 205 and a trench inner upper polysilicon body 207, an outer ring of the trench inner lower polysilicon body 205 is insulated and isolated from the sidewall and the bottom wall of the cell trench 212 by a trench inner lower insulating oxide layer 204, an outer ring of the trench inner upper polysilicon body 207 is insulated and isolated from the sidewall of the cell trench 212 and the trench inner lower polysilicon body 205 by a trench inner upper insulating oxide layer 206, and a width of the trench inner upper polysilicon body 207 is greater than a width of the trench inner lower polysilicon body 205;
the upper polysilicon body 207 in the trench is in ohmic contact with the gate metal 211 above the N-type drift layer 203, and the lower polysilicon body 205 in the trench is in ohmic contact with the source metal 210 above the N-type drift layer 203; the source metal 210 is also in ohmic contact with the P-type base region 208 on the outer upper side of the sidewall between the adjacent cell trenches 212 and the N + source region 209 located in the P-type base region 208.
In the embodiment of the present invention, the trench gate structure in the cell trench 212 may adopt a shielded gate structure or other common gate structure, and when a shielded gate is adopted, the shielded gate includes a lower polysilicon body 205 in the trench and an upper polysilicon body 207 in the trench, and the width of the upper polysilicon body 207 in the trench is greater than the width of the lower polysilicon body 205 in the trench. The source metal 210 is in ohmic contact with the N + source region 209, the P-type base region 208 where the N + source region 209 is located and the lower polysilicon body 205 in the trench, a source electrode of the MOSFET device can be formed by using the source metal 210, the gate metal 211 is in ohmic contact with the upper polysilicon body 207 in the trench, and a gate electrode of the MOSFET device can be formed by using the gate metal 211. The active cells of the cell region are integrally connected to each other through the source metal 210.
Certainly, in the specific implementation, an insulating dielectric layer is further required to be disposed between the source metal 210, the gate metal 211 and the N-type drift layer 203 to achieve the required insulating isolation, and the specific configuration of the insulating dielectric layer is well known to those skilled in the art and will not be described herein again.
In specific implementation, the depth of the cell trench 212 is 3 μm to 6 μm, and the thickness of the terminal trench insulating oxide layer 204 is consistent with the thickness of the lower insulating oxide layer 204 in the trench. An N-type auxiliary layer 202 is arranged between the N + substrate 201 and the N-type drift layer 203, the N-type auxiliary layer 202 is respectively adjacent to the N + substrate 201 and the N-type drift layer 203, the thickness of the N-type auxiliary layer 202 is 10-20 microns, and the cut-off electric field of the MOSFET device can be effectively improved through the N-type auxiliary layer 202.
As shown in fig. 2 to 11, the MOSFET device with the improved withstand voltage range can be prepared by the following steps, specifically, the method for preparing the MOSFET device includes the following steps:
step 1, providing a semiconductor substrate with an N conductive type, wherein the semiconductor substrate comprises an N + substrate 201 and an N type drift layer 203 positioned above the N + substrate 201; selectively masking and etching the N-type drift layer 203 to obtain a desired cell trench 212 and a terminal auxiliary trench 216 in the N-type drift layer 203;
specifically, the semiconductor substrate may be made of silicon or other materials, and by using the technical means commonly used in the art, the cell trench 212 and the terminal auxiliary trench 216 can be simultaneously obtained in the N-type drift layer 203, the cell trench 212 and the terminal auxiliary trench 216 vertically extend downward from the upper surface of the N-type drift layer 203, and the depths of the cell trench 212 and the terminal auxiliary trench 216 are the same, as shown in fig. 2. The process of preparing the cell trench 212 and the terminal auxiliary trench 216 is well known in the art and will not be described herein.
An N-type auxiliary layer 202 is provided between the N + substrate 201 and the N-type drift layer 203, the N-type auxiliary layer 203 is adjacent to the N + substrate 201 and the N-type drift layer 203, and the thickness of the N-type auxiliary layer 202 is 10 μm to 20 μm.
Step 2, etching the terminal auxiliary trench 216 again to obtain a required terminal trench 213, wherein the depth of the terminal trench 213 is greater than that of the cell trench 212, and the depth of the terminal trench 213 is less than the thickness of the N-type drift layer 203;
specifically, only the terminal auxiliary trench 215 is etched by a conventional technique in the art to obtain a terminal trench 213 having a depth greater than that of the cell trench 212, where the depth of the cell trench is 3 μm to 6 μm, as shown in fig. 3.
Step 3, performing a required trench gate preparation process on the cell trench 212 to obtain a required trench gate structure in the cell trench 212, and obtaining terminal conductive polysilicon 215 in the terminal trench 213 when the trench gate structure is obtained by preparation, wherein the terminal trench conductive polysilicon 215 is insulated and isolated from the side wall and the bottom wall of the terminal trench 213 by a terminal trench insulating oxide layer 214;
specifically, when the prepared trench gate structure is a shielding gate structure, the specific process comprises the following steps:
step 3-1, simultaneously arranging a first trench insulating oxide layer 217 in the cell trench 212 and the terminal trench 213, wherein the first trench insulating oxide layer 217 in the cell trench 212 covers the side wall and the bottom wall of the cell trench 212, the first trench insulating oxide layer 217 in the terminal trench 213 covers the side wall and the bottom wall of the terminal trench, and after the first trench insulating oxide layer 217 is arranged, a first polysilicon filling hole 218 is formed in the cell trench 212, and a terminal trench polysilicon filling hole 219 is formed in the terminal trench 213;
as shown in fig. 4, the first trench insulating oxide layer 217 may be a silicon dioxide layer, the first trench insulating oxide layer 217 covers the cell trench 212 and the terminal trench 213 at the same time, and the first trench insulating oxide layer 217 may be disposed in a thermal oxidation or filling manner, which may be specifically selected and determined according to the need, and is not described herein again.
Step 3-2, conducting polysilicon deposition is performed on the N-type drift layer 203 to obtain a cell polysilicon filling body 220 filling the first polysilicon filling hole 218 and a terminal conducting polysilicon 215 filling the terminal trench polysilicon filling hole 219; the first trench insulating oxide layer 217 corresponding to the terminal conductive polysilicon 215 forms a terminal trench insulating oxide layer 214;
as shown in fig. 5, the conductive polysilicon filled in the terminal trench polysilicon filling hole 219 forms a terminal conductive polysilicon 215, and after the terminal conductive polysilicon 215 is obtained, the first trench insulating oxide layer 217 in the terminal trench 213 forms a terminal trench insulating oxide layer 214, and the length of the terminal conductive polysilicon 215 is greater than that of the cell polysilicon filling body 220.
Step 3-3, etching the cell polysilicon filling body 220 to obtain a trench inner lower polysilicon body 205 positioned in the cell trench 212 and an etching positioning hole 221 positioned right above the trench inner lower polysilicon body 205;
as shown in fig. 6, only the cell polysilicon filling body 220 is etched by a conventional technique in the art to remove the upper portion of the cell polysilicon filling body 220, that is, the lower portion of the cell polysilicon filling body 220 forms the in-trench lower polysilicon body 205 in the cell trench 212, after the upper portion of the cell polysilicon filling body 220 is removed, an etching positioning hole 221 is formed right above the in-trench lower polysilicon body 205, and the aperture of the etching positioning hole 221 is consistent with the outer diameter of the in-trench lower polysilicon body 205.
Step 3-4, fully etching the first trench insulating oxide layer 217 on the upper portion in the cell trench 212 by using the etching positioning hole 221 to obtain an in-trench lower insulating oxide layer 204 corresponding to the in-trench lower polysilicon body 205 and an upper slot body 222 located right above the in-trench lower polysilicon body 205, wherein the width of the upper slot body 222 is consistent with the width of the cell trench 212;
as shown in fig. 7, when the first trench insulating oxide layer 217 is etched by using the etching positioning hole 221, an upper slot body 222 is obtained, the height of the upper slot body 222 is the same as that of the etching positioning hole 221, and the width of the upper slot body 222 is the same as that of the cell trench 212. After etching the first trench insulating oxide layer 217 on the upper portion of the cell trench 212, the remaining first trench insulating oxide layer 217 is the trench inner lower insulating oxide layer 204.
3-5, arranging a second groove insulating oxide layer 224 in the upper groove body 222, wherein the second groove insulating oxide layer 224 covers the side wall and the bottom of the upper groove body 222, and a second polysilicon filling hole 223 is formed after the second groove insulating oxide layer 224 is arranged in the upper groove body 222;
as shown in fig. 8, the second trench insulating oxide layer 224 is used to form the trench upper insulating oxide layer 206, and the thickness of the trench upper insulating oxide layer 206 is smaller than that of the trench lower insulating oxide layer 204. After the second trench insulating oxide layer 224 is disposed, a second polysilicon filling hole 223 is obtained.
Step 3-6, conducting polysilicon filling is performed in the second polysilicon filling hole 223, so as to obtain an in-trench upper polysilicon body 207 filling the second polysilicon filling hole 223, an in-trench upper insulating oxide layer 206 is formed on a second trench insulating oxide layer 224 corresponding to the in-trench upper polysilicon body 207, and the in-trench upper polysilicon body 207 is insulated and isolated from the sidewall of the cell trench 212 and the in-trench lower polysilicon body 205 by the in-trench upper insulating oxide layer 206; the width of the upper polysilicon body 207 in the trench is greater than the width of the lower polysilicon body 205 in the trench;
as shown in fig. 9, the thickness of the upper insulating oxide layer 206 in the trench is the same as that of the second trench insulating oxide layer 224, and the width of the upper polysilicon body 207 in the trench is greater than that of the lower polysilicon body 205 in the trench, so that the thickness of the upper insulating oxide layer 206 in the trench is less than that of the lower insulating oxide layer 204 in the trench.
Step 4, injecting P-type impurity ions above the N-type drift layer 203, forming required P-type base regions 208 on two sides of the cell trench 212 after diffusion, wherein the P-type base regions 208 are in contact with the cell trench 212, and the terminal trench 213 adjacent to the cell region is in contact with the P-type base region 208 above the outer wall of the cell trench side 212 adjacent to the terminal protection region;
specifically, a technical means commonly used in the technical field is adopted to perform P-type impurity ion implantation, and the P-type base regions 208 are distributed on two sides of each cell trench 212; the P-type base region 208 extends downward from the notch of the cell trench 212, and when the trench gate in the cell trench 212 adopts a shielded gate structure, the P-type base region 208 is located above the bottom of the upper polysilicon body 207 in the trench.
Step 5, injecting N-type impurity ions above the N-type drift layer 203 to obtain an N + source region 209 in the P-type base region 208 located above and outside the sidewall between the adjacent cell trenches 212, wherein the N + source region 209 is in contact with the sidewall of the corresponding cell trench 212;
as shown in fig. 10, by using the conventional technical means in the art to implant N-type impurity ions, the N + source regions 209 are only distributed in the P-type base region 208 above the sidewall between the adjacent cell trenches 212, and therefore, the N + source regions 209 are not present in the P-type base region 208 between the terminal trench 213 and the cell trenches 212.
And 6, depositing a metal layer above the N-type drift layer 203 to obtain a source metal 210 and a gate metal 211 which are positioned above the N-type drift layer 203, wherein the source metal 210 is in ohmic contact with the N + source region 209 and the P-type base region 208 where the N + source region 209 is positioned, and the gate metal 211 is electrically connected with the trench gate structure in the cell trench 211.
As shown in fig. 11, a source metal 210 and a gate metal 211 are prepared by depositing a metal layer by a conventional technique in the art, and when a shielded gate structure is adopted, the gate metal 211 is in ohmic contact with the upper polysilicon body 207 in the trench, and the source metal 210 is in ohmic contact with the lower polysilicon body 205 in the trench. The process of specifically setting the source metal 210 and the gate metal, and the process of implementing the extraction and the like can be implemented by using a common process method, and details are not described again. In specific implementation, the source metal 210 and the gate metal are isolated from each other, the source metal 210, the gate metal and the N-type drift layer 203 can be isolated from each other by an insulating dielectric layer, and the active cells in the cell region of the MOSFET device are connected into a whole by the source metal 210.
In addition, a drain structure is required to be disposed on the lower surface of the N + substrate 201, a drain electrode of the MOSFET device can be formed through the drain structure, and the existing material can be selected or referred to in the specific process for forming the drain electrode and the specific form of the drain structure, which is not described herein again.
Claims (2)
1. A MOSFET device for improving the withstand voltage range comprises a cellular area and a terminal protection area, wherein the cellular area is positioned on a semiconductor substrate, the cellular area is positioned in the central area of the semiconductor substrate, the terminal protection area is positioned on the outer ring of the cellular area, and the terminal protection area surrounds and surrounds the cellular area; the semiconductor substrate comprises a first conductive type substrate and a first conductive type drift layer positioned above the first conductive type substrate; active cells in the cell area adopt a groove structure, and a groove gate structure is arranged in the cell groove; a second conductive type base region is arranged above the outside of the side wall of the cellular trench, is positioned in the first conductive type drift layer and is contacted with the corresponding side wall of the cellular trench; arranging first conductive type source regions in the second conductive type base regions above and outside the side walls between the adjacent cell grooves, wherein the first conductive type source regions are contacted with the side walls of the corresponding cell grooves; the method is characterized in that:
arranging a plurality of terminal grooves in the terminal protection region, wherein the terminal grooves are positioned in the first conduction type drift layer, and the depth of the terminal grooves in the first conduction type drift layer is greater than that of the cell grooves in the first conduction type drift layer; terminal conductive polycrystalline silicon is arranged in the terminal groove and is insulated and isolated from the side wall and the bottom wall of the terminal groove through a terminal groove insulating oxide layer; the terminal groove adjacent to the cell area is contacted with the second conductive type base region above the outer side wall of the cell groove adjacent to the terminal protection area;
the trench gate structure in the cell trench comprises a shielding gate structure, the shielding gate structure comprises a lower polysilicon body in the trench and an upper polysilicon body in the trench, the outer ring of the lower polysilicon body in the trench is insulated and isolated from the side wall and the bottom wall of the cell trench through a lower insulating oxide layer in the trench, the outer ring of the upper polysilicon body in the trench is insulated and isolated from the side wall of the cell trench and the lower polysilicon body in the trench through an upper insulating oxide layer in the trench, and the width of the upper polysilicon body in the trench is greater than that of the lower polysilicon body in the trench;
an upper polycrystalline silicon body in the groove is in ohmic contact with the grid metal above the first conduction type drift layer, and a lower polycrystalline silicon body in the groove is in ohmic contact with the source metal above the first conduction type drift layer; the source electrode metal is in ohmic contact with a second conductive type base region which is arranged above and outside the side wall between the adjacent cellular trenches and a first conductive type source region which is positioned in the second conductive type base region;
the depth of the cellular trench is 3-6 μm, and the thickness of the insulating oxide layer of the terminal trench is consistent with that of the lower insulating oxide layer in the trench;
and a first conduction type auxiliary layer is arranged between the first conduction type substrate and the first conduction type drift layer, the first conduction type auxiliary layer is respectively adjacent to the first conduction type substrate and the first conduction type drift layer, and the thickness of the first conduction type auxiliary layer is 10-20 mu m.
2. A preparation method of an MOSFET device for improving the withstand voltage range is characterized by comprising the following steps:
step 1, providing a semiconductor substrate with a first conductivity type, wherein the semiconductor substrate comprises a first conductivity type substrate and a first conductivity type drift layer positioned above the first conductivity type substrate; selectively masking and etching the first conductive type drift layer to obtain a required cell trench and a terminal auxiliary trench in the first conductive type drift layer;
step 2, etching the terminal auxiliary groove again to obtain a required terminal groove, wherein the depth of the terminal groove is greater than that of the cellular groove, and the depth of the terminal groove is smaller than the thickness of the first conductive type drift layer;
step 3, performing a required trench gate preparation process on the cell trench to obtain a required trench gate structure in the cell trench, and obtaining terminal conductive polysilicon in the terminal trench when the trench gate structure is obtained by preparation, wherein the terminal trench conductive polysilicon is insulated and isolated from the side wall and the bottom wall of the terminal trench through a terminal trench insulating oxide layer;
step 4, injecting second conductive type impurity ions above the first conductive type drift layer, forming required second conductive type base regions on two sides of the cellular trench after diffusion, wherein the second conductive type base regions are in contact with the cellular trench, and the terminal trench adjacent to the cellular region is in contact with the second conductive type base region above the outer side wall of the cellular trench adjacent to the terminal protection region;
step 5, injecting first conductive type impurity ions above the first conductive type drift layer to obtain a first conductive type source region in a second conductive type base region which is positioned above and outside the side wall between adjacent cell grooves, wherein the first conductive type source region is contacted with the side wall of the corresponding cell groove;
step 6, depositing a metal layer above the first conductive type drift layer to obtain a source metal and a gate metal which are positioned above the first conductive type drift layer, wherein the source metal is in ohmic contact with a first conductive type source region and a second conductive type base region where the first conductive type source region is positioned, and the gate metal is electrically connected with a trench gate structure in a cell trench;
in step 3, when the prepared trench gate structure is a shielded gate structure, the specific process comprises the following steps:
step 3-1, simultaneously arranging a first groove insulating oxide layer in the cell groove and the terminal groove, wherein the first groove insulating oxide layer in the cell groove covers the side wall and the bottom wall of the cell groove, the first groove insulating oxide layer in the terminal groove covers the side wall and the bottom wall of the terminal groove, and after the first groove insulating oxide layer is arranged, a first polycrystalline silicon filling hole is formed in the cell groove and a terminal groove polycrystalline silicon filling hole is formed in the terminal groove;
step 3-2, conducting polycrystalline silicon deposition is carried out above the first conduction type drift layer, so that a cell polycrystalline silicon filling body filling the first polycrystalline silicon filling hole and terminal conducting polycrystalline silicon filling the terminal groove polycrystalline silicon filling hole are obtained; forming a terminal groove insulating oxide layer by the first groove insulating oxide layer corresponding to the terminal conductive polycrystalline silicon;
3-3, etching the cellular polysilicon filling body to obtain a lower-layer polysilicon body in the groove in the cellular groove and an etching positioning hole right above the lower-layer polysilicon body in the groove;
step 3-4, fully etching the first groove insulating oxide layer at the upper part in the cellular groove by using the etching positioning hole to obtain a lower groove insulating oxide layer corresponding to the lower layer polycrystalline silicon body in the groove and an upper groove body positioned right above the lower layer polycrystalline silicon body in the groove, wherein the width of the upper groove body is consistent with that of the cellular groove;
3-5, arranging a second groove insulating oxide layer in the upper groove body, wherein the second groove insulating oxide layer covers the side wall and the bottom of the upper groove body, and a second polycrystalline silicon filling hole is formed after the second groove insulating oxide layer is arranged in the upper groove body;
step 3-6, conducting polycrystalline silicon filling is carried out in the second polycrystalline silicon filling hole, so that an upper polycrystalline silicon body in the groove is obtained, the second groove insulation oxide layer corresponding to the upper polycrystalline silicon body in the groove forms an upper insulation oxide layer in the groove, and the upper polycrystalline silicon body in the groove is insulated and isolated from the side wall of the cellular groove and the lower polycrystalline silicon body in the groove through the upper insulation oxide layer in the groove; the width of the upper layer polysilicon body in the groove is larger than that of the lower layer polysilicon body in the groove;
the grid metal is in ohmic contact with the upper polysilicon body in the groove, and the source metal is in ohmic contact with the lower polysilicon body in the groove;
a first conductive type auxiliary layer is arranged between the first conductive type substrate and the first conductive type drift layer, the first conductive type auxiliary layer is respectively adjacent to the first conductive type substrate and the first conductive type drift layer, and the thickness of the first conductive type auxiliary layer is 10-20 mu m;
the semiconductor substrate is made of silicon, and the depth of the cell groove is 3-6 microns.
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