CN109166924B - Transverse MOS type power semiconductor device and preparation method thereof - Google Patents
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Abstract
The invention provides a transverse MOS device and a preparation method thereof, belonging to the technical field of semiconductor power devices. The invention introduces deep medium groove, semi-insulating polysilicon column and buffer layer into drift region of traditional lateral MOS type device. The introduction of the deep dielectric groove enables the device to form a U-shaped conductive channel, and the length of the drift region is effectively increased under the condition of the same device length; the semi-insulating polysilicon columns and the drift region are alternately connected along the transverse extension direction of the deep dielectric trench to form a three-dimensional resistive field plate structure, so that when the device is blocked, the multi-dimensional depletion effect is introduced into the drift region to improve the doping concentration of the drift region, the width of the drift region at two sides of the deep trench is not limited by the doping dose, the electric field distribution of the drift region is improved, the breakdown voltage of the device is improved, and the specific on-resistance/on-voltage drop of the device is also reduced. The introduction of the buffer layer can improve the charge balance characteristic of the three-dimensional medium super junction structure, so that the performance and the reliability of the device are further improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a transverse MOS type power semiconductor device and a preparation method thereof.
Background
Lateral double-diffused metal oxide semiconductor field effect transistor (L DMOS) and lateral insulated gate bipolar transistor (L IGBT) devices are widely used in large-scale integrated circuits and become an essential part of power integrated circuit development due to the advantages of good thermal stability, high gain, low noise and high compatibility with CMOS processes, for conventional L DMOS (as shown in fig. 1) and L IGBT devices, if the voltage endurance capability of the devices is increased, the length of a drift region must be increased to improve the voltage endurance capability of the devices, however, the on-resistance/on-voltage drop of the devices is increased, the power consumption is increased, the chip area is increased, and the cost is increased.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a transverse MOS device and a preparation method thereof, wherein a deep dielectric trench is introduced into a drift region of the traditional transverse MOS device (L DMOS device/L IGBT device) to form a conductive channel, a semi-insulating polysilicon (SIPOS) column is introduced at the same time, the SIPOS column and the drift region are alternately connected along the transverse extension direction of the deep dielectric trench to form a three-dimensional resistive field plate structure, a semiconductor region with the doping type opposite to that of the drift region is further introduced into the other side of the drift region opposite to that of the SIPOS column to provide a three-dimensional charge compensation effect, so that the doping concentration of the drift region is improved by introducing a depletion effect into the drift region when the device is blocked, the widths of the drift regions at two sides of a deep trench are not limited by the doping dose, the electric field distribution of the drift region is improved, the ratio on-resistance/on-voltage drop is reduced while the breakdown voltage is improved, and the charge balance characteristic of a three-dimensional dielectric super junction structure is further improved by introducing a.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a MOS type power semiconductor device, in particular to a lateral diffusion metal oxide semiconductor device (L DMOS device):
an L DMOS device, the cellular structure includes a substrate, a substrate electrode 16 arranged on the back of the substrate and a first conductive type semiconductor drift region 10 on the front of the substrate, one side of the top layer of the first conductive type semiconductor drift region 10 is provided with a first conductive type semiconductor drain region 9, the other side of the top layer of the first conductive type semiconductor drift region 10 is provided with an MOS structure, the MOS structure includes a second conductive type semiconductor body region 7, a first conductive type semiconductor source region 6, a second conductive type semiconductor contact region 8, a source electrode 3 and a trench gate structure, the trench gate structure includes a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side and the bottom of the trench gate electrode 1, the second conductive type semiconductor body region 7 is arranged between the trench gate structure and the first conductive type semiconductor drain region 9 and is arranged next to the trench gate structure, the second conductive type semiconductor body region 7 and the first conductive type semiconductor drift region 10 thereunder are contacted with the trench gate electrode 1 through a trench dielectric layer 2, the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8 are arranged side by side on the top layer of the trench gate electrode 7, wherein the first conductive type semiconductor source region 6 is characterized in that:
a first conductive type semiconductor buffer layer 13 is arranged between the substrate and the first conductive type semiconductor drift region 10; the lower surface of the first conductivity type semiconductor buffer layer 13 coincides with the upper surface of the substrate, and the upper surface of the first conductivity type semiconductor buffer layer 13 coincides with the lower surface of the first conductivity type semiconductor drift region 10; a deep dielectric trench 4 is arranged in a first conductive type semiconductor drift region 10 between the trench gate structure and the first conductive type semiconductor drain region 9; the side face of the deep dielectric trench 4 is in contact with the second conductivity type semiconductor contact region 8 and the second conductivity type semiconductor body region 7; a semi-insulating polysilicon groove is further arranged in the first conductive type semiconductor drift region 10 and comprises semi-insulating polysilicon 11 and insulating medium layers 12 arranged on the side faces and the bottom face of the semi-insulating polysilicon 11, the semi-insulating polysilicon groove is alternately connected with the first conductive type semiconductor drift region 10 along the transverse extension direction of the deep medium groove 4, the upper surface of the semi-insulating polysilicon groove is flush with the upper surface of the first conductive type semiconductor drain region 9, and the lower surface of the semi-insulating polysilicon groove is flush with the lower surface of the first conductive type semiconductor drift region 10; the semi-insulating polycrystalline silicon 11 is contacted with the trench gate electrode 1 through the trench gate dielectric layer 2, and the active electrodes 3 are arranged on the upper surfaces of the semi-insulating polycrystalline silicon 11, the insulating dielectric layer 12, the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8; the source electrode 3 is isolated from the trench gate electrode 1 through a dielectric layer; the upper surfaces of the semi-insulating polysilicon 11 and the first conductivity type semiconductor drain region 9 are provided with a drain electrode 5.
Further, the present invention may use an SOI layer as the substrate, where the SOI layer is specifically formed by stacking a second conductivity type semiconductor layer 15, a buried oxide layer 14, and a first conductivity type semiconductor buffer layer 13 from bottom to top, or may directly use the second conductivity type semiconductor layer 15 as the substrate.
Further, the material of the semiconductor used in the device of the present invention may be selected from silicon, germanium, silicon carbide, gallium nitride, gallium sesquioxide or diamond.
Further, the deep dielectric trench is formed by filling a deep trench with a dielectric material.
Further, the semi-insulating polysilicon trench is formed by first forming an insulating dielectric layer 12 in the trench and then filling a semi-insulating polysilicon material.
Further, the longitudinal depth of the deep dielectric trench 4 may be equal to or greater than the junction depth of the first conductivity type semiconductor drift region 10, i.e., the deep dielectric trench 4 may extend into the first conductivity type semiconductor drift region 10, coincide with the lower surface of the first conductivity type semiconductor drift region 10, and may also extend into the first conductivity type semiconductor buffer layer 13.
Further, the depth of the deep dielectric trench 4 in the longitudinal direction is greater than the width thereof, i.e. the aspect ratio of the deep dielectric trench 4 is less than 1.
Further, the longitudinal depth of the semi-insulating polysilicon trench may be greater than the longitudinal depth of the deep dielectric trench 4, may also be less than the longitudinal depth of the deep dielectric trench 4, and may also be equal to the longitudinal depth of the deep dielectric trench 4.
Further, the semi-insulating polysilicon 11 is contacted with the trench gate electrode 1 through the lateral trench gate dielectric layer 2.
Further, the junction depth of the second conductivity type semiconductor body region 7 is smaller than the depth of the trench gate electrode 1.
Further, a semi-insulating polysilicon trench penetrates the deep dielectric trench 4.
Further, the longitudinal depth of the trench gate electrode 1 is smaller than the longitudinal depth of the deep dielectric trench 4.
Further, a second conductive type semiconductor column region 17 is further disposed in the first conductive type semiconductor drift region 10, the second conductive type semiconductor column region 17 is laterally connected to the first conductive type semiconductor drift region 10 along the deep dielectric trench 4 and is sandwiched between the first conductive type semiconductor drift regions 10 on two sides to avoid contact with the semi-insulating polysilicon, and the second conductive type semiconductor column region 17 is flush with the upper and lower surfaces of the first conductive type semiconductor drift region 10.
Further, a lateral first conductivity type semiconductor buffer layer 18 is disposed in the first conductivity type semiconductor drift region 10 under the first conductivity type semiconductor drain region 9 and clings to the sidewall of the deep dielectric trench 4. The doping concentration of the lateral first conductivity type semiconductor buffer layer 18 may be uniformly doped or may be decreased from top to bottom.
Further, a bottom surface first conductivity type semiconductor buffer layer 19 closely attached to the bottom wall of the deep dielectric trench 4 is further disposed in the first conductivity type semiconductor drift region 10 below the deep dielectric trench 4. The doping concentration of the bottom first conductivity type semiconductor buffer layer 19 may be uniform doping, or may decrease in a direction from the metalized drain 5 to the metalized source 3.
Further, when the side surface first conductivity type semiconductor buffer layer 18 and the bottom surface first conductivity type semiconductor buffer layer 19 coexist, the doping concentration of the side surface first conductivity type semiconductor buffer layer 18 is not less than that of the bottom surface first conductivity type semiconductor buffer layer 19.
Further, a lateral second conductivity type semiconductor buffer layer is arranged in the first conductivity type semiconductor drift region 10 below the second conductivity type semiconductor body region 7 and clings to the sidewall of the deep dielectric trench 4. The doping concentration of the lateral second conductive type semiconductor buffer layer can be uniformly doped or can be gradually reduced from top to bottom.
Further, the doping concentration of the first conductivity type semiconductor buffer layer 13, the side first conductivity type semiconductor buffer layer 18, and the bottom first conductivity type semiconductor buffer layer 18 is greater than the doping concentration of the first conductivity type semiconductor drift region 10.
Further, a first field plate 401 and a second field plate 402 which are symmetrically arranged and have the same extension direction as the deep dielectric trench 4 are also arranged in the deep dielectric trench. Wherein the longitudinal extension depth of the first field plate 401 and the second field plate 402 is smaller than the longitudinal depth of the deep dielectric trench 4; the thicknesses of the dielectric layers of the first field plate 401 and the second field plate 402, which are far away from the edge of the deep dielectric trench 4, can be adjusted, that is, the thickness of the dielectric layers can be uniform, or the thicknesses of the dielectric layers can be set to be step-type field plates, or the thicknesses of the first field plate 401 and the second field plate 402 and the thickness of the dielectric layer at the edge of the deep dielectric trench 4 adjacent to the first field plate and the second field plate can be increased progressively along the longitudinal direction by reasonably setting the positions of.
The invention provides a power semiconductor device belonging to MOS type, in particular to a lateral insulated gate bipolar transistor (namely L IGBT device):
a L IGBT device comprises a substrate, a substrate electrode 16 arranged on the back of the substrate and a first conduction type semiconductor drift region 10 on the front of the substrate, wherein one side of the top layer of the first conduction type semiconductor drift region 10 is provided with an MOS structure, the other side of the top layer of the first conduction type semiconductor drift region 10 is provided with a first conduction type semiconductor Buffer region and a second conduction type semiconductor collector region arranged on the upper surface of the first conduction type semiconductor Buffer region, the second conduction type semiconductor collector region on the upper surface of the first conduction type semiconductor Buffer region is in contact with a deep dielectric trench 4, the MOS structure comprises a second conduction type semiconductor body region 7, a first conduction type semiconductor source region 6, a second conduction type semiconductor contact region 8, a source electrode 3 and a trench gate structure, the trench gate structure comprises a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side surface and the bottom surface of the trench gate electrode 1, the second conduction type semiconductor body region 7 is arranged between the trench gate electrode structure and the first conduction type semiconductor Buffer region and is arranged adjacent to the trench gate electrode 1, the second conduction type semiconductor body region 7 is in contact with the second conduction type semiconductor trench gate electrode 2 through the first conduction type semiconductor drift region 7 and the second conduction type semiconductor trench gate electrode 2, and the second conduction type semiconductor trench gate electrode 7 are arranged side by side through the first conduction type semiconductor trench gate electrode 1 and the first conduction type semiconductor drift region, and the second conduction type semiconductor trench gate electrode 2, and the second conduction type semiconductor trench gate electrode:
a first conductive type semiconductor buffer layer 13 is arranged between the substrate and the first conductive type semiconductor drift region 10; the lower surface of the first conductivity type semiconductor buffer layer 13 coincides with the upper surface of the substrate, and the upper surface of the first conductivity type semiconductor buffer layer 13 coincides with the lower surface of the first conductivity type semiconductor drift region 10; a deep dielectric trench 4 is arranged in the first conductive type semiconductor drift region 10 between the trench gate structure and the first conductive type semiconductor Buffer region; the side face of the deep dielectric trench 4 is in contact with the second conductivity type semiconductor contact region 8 and the second conductivity type semiconductor body region 7; the first conductive type semiconductor drift region 10 is also provided with semi-insulating polysilicon grooves, the semi-insulating polysilicon grooves comprise semi-insulating polysilicon 11 and insulating dielectric layers 12 arranged on the side surfaces and the bottom surface of the semi-insulating polysilicon 11, the semi-insulating polysilicon grooves are alternately connected with the first conductive type semiconductor drift region 10 along the transverse extension direction of the deep dielectric trench 4, wherein the upper surfaces of the semi-insulating polysilicon grooves are flush with the upper surface of the second conductive type semiconductor collector region, and the lower surfaces of the semi-insulating polysilicon grooves are flush with the lower surface of the first conductive type semiconductor drift region 10; the semi-insulating polycrystalline silicon 11 is contacted with the trench gate electrode 1 through the trench gate dielectric layer 2, and the active electrodes 3 are arranged on the upper surfaces of the semi-insulating polycrystalline silicon 11, the insulating dielectric layer 12, the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8; the source electrode 3 is isolated from the trench gate electrode 1 through a dielectric layer; the upper surfaces of the semi-insulating polysilicon trench and the first conductivity type semiconductor drain region 9 are provided with a drain electrode 5.
Further, the present invention may use an SOI layer as the substrate, where the SOI layer is specifically formed by stacking a second conductivity type semiconductor layer 15, a buried oxide layer 14, and a first conductivity type semiconductor buffer layer 13 from bottom to top, or may directly use the second conductivity type semiconductor layer 15 as the substrate.
Further, the material of the semiconductor used in the device of the present invention may be selected from silicon, germanium, silicon carbide, gallium nitride, gallium sesquioxide or diamond.
Further, the deep dielectric trench is formed by filling a deep trench with a dielectric material.
Further, the semi-insulating polysilicon trench is formed by first forming an insulating dielectric layer 12 in the trench and then filling a semi-insulating polysilicon material.
Further, the longitudinal depth of the deep dielectric trench 4 may be equal to or greater than the junction depth of the first conductivity type semiconductor drift region 10, i.e., the deep dielectric trench 4 may extend into the first conductivity type semiconductor drift region 10, coincide with the lower surface of the first conductivity type semiconductor drift region 10, and may also extend into the first conductivity type semiconductor buffer layer 13.
Further, the depth of the deep dielectric trench 4 in the longitudinal direction is greater than the width thereof, i.e. the aspect ratio of the deep dielectric trench 4 is less than 1.
Further, the longitudinal depth of the semi-insulating polysilicon trench may be greater than the longitudinal depth of the deep dielectric trench 4, may also be less than the longitudinal depth of the deep dielectric trench 4, and may also be equal to the longitudinal depth of the deep dielectric trench 4.
Further, the semi-insulating polysilicon 11 is contacted with the trench gate electrode 1 through the lateral trench gate dielectric layer 2.
Further, the junction depth of the second conductivity type semiconductor body region 7 is smaller than the depth of the trench gate electrode 1.
Further, a semi-insulating polysilicon trench penetrates the deep dielectric trench 4.
Further, the longitudinal depth of the trench gate electrode 1 is smaller than the longitudinal depth of the deep dielectric trench 4.
Further, a second conductive type semiconductor column region 17 is further disposed in the first conductive type semiconductor drift region 10, the second conductive type semiconductor column region 17 is laterally connected to the first conductive type semiconductor drift region 10 along the deep dielectric trench 4 and is sandwiched between the first conductive type semiconductor drift regions 10 on both sides to avoid contact with the semi-insulating polysilicon column, and the second conductive type semiconductor column region 17 is flush with the upper and lower surfaces of the first conductive type semiconductor drift region 10.
Further, a lateral first conductivity type semiconductor buffer layer 18 is disposed in the first conductivity type semiconductor drift region 10 under the second conductivity type semiconductor collector region 9 and clings to the sidewall of the deep dielectric trench 4. The doping concentration of the lateral first conductivity type semiconductor buffer layer 18 may be uniformly doped or may be decreased from top to bottom.
Further, a bottom surface first conductivity type semiconductor buffer layer 19 closely attached to the bottom wall of the deep dielectric trench 4 is further disposed in the first conductivity type semiconductor drift region 10 below the deep dielectric trench 4. The doping concentration of the bottom first conductivity type semiconductor buffer layer 19 may be uniform doping, or may decrease in a direction from the metalized drain 5 to the metalized source 3.
Further, when the side surface first conductivity type semiconductor buffer layer 18 and the bottom surface first conductivity type semiconductor buffer layer 19 coexist, the doping concentration of the side surface first conductivity type semiconductor buffer layer 18 is not less than that of the bottom surface first conductivity type semiconductor buffer layer 19.
Further, a lateral second conductivity type semiconductor buffer layer is arranged in the first conductivity type semiconductor drift region 10 below the second conductivity type semiconductor body region 7 and clings to the sidewall of the deep dielectric trench 4. The doping concentration of the lateral second conductive type semiconductor buffer layer can be uniformly doped or can be gradually reduced from top to bottom.
Further, the doping concentration of the first conductivity type semiconductor buffer layer 13, the side first conductivity type semiconductor buffer layer 18, and the bottom first conductivity type semiconductor buffer layer 18 is greater than the doping concentration of the first conductivity type semiconductor drift region 10.
Further, a first field plate 401 and a second field plate 402 which are symmetrically arranged and have the same extension direction as the deep dielectric trench 4 are also arranged in the deep dielectric trench. Wherein the longitudinal extension depth of the first field plate 401 and the second field plate 402 is smaller than the longitudinal depth of the deep dielectric trench 4; the thicknesses of the dielectric layers of the first field plate 401 and the second field plate 402, which are far away from the edge of the deep dielectric trench 4, can be adjusted, that is, the thickness of the dielectric layers can be uniform, or the thicknesses of the dielectric layers can be set to be step-type field plates, or the thicknesses of the first field plate 401 and the second field plate 402 and the thickness of the dielectric layer at the edge of the deep dielectric trench 4 adjacent to the first field plate and the second field plate can be increased progressively along the longitudinal direction by reasonably setting the positions of.
In addition, the invention also provides a preparation method of the transverse MOS type power semiconductor device, which is characterized by comprising the following steps:
(1) selecting a second conductive type semiconductor layer as a substrate;
(2) forming a first conductive type semiconductor buffer layer on the second conductive type semiconductor layer;
(3) forming a first conductive type semiconductor drift region on the first conductive type semiconductor buffer layer;
(4) etching a groove in the first conduction type semiconductor drift region, forming an insulating medium layer on the inner wall of the groove, and filling semi-insulating polysilicon material in the groove to form a semi-insulating polysilicon column which is connected with the first conduction type semiconductor drift region and has level upper and lower surfaces;
(5) etching a deep groove along a direction vertical to a connecting interface of the first conductive type semiconductor drift region and the semi-insulating polysilicon column, and filling a dielectric material in the deep groove to form a deep dielectric groove;
(6) forming a trench gate structure in the first conductive type semiconductor drift region on one side of the deep dielectric trench;
(7) forming a second conductive type semiconductor base region in the top layer of the first conductive type semiconductor drift region between the deep dielectric trench and the trench gate structure, wherein the junction depth of the second conductive type semiconductor base region is smaller than the longitudinal depth of the trench gate structure;
(8) forming a first conductive type semiconductor source region and a second conductive type semiconductor contact region on the top layer of the second conductive type semiconductor base region;
(9) forming a first conductive type semiconductor drain region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench, or forming a first conductive type semiconductor Buffer region and a second conductive type semiconductor collector region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench;
(10) depositing a dielectric layer, photoetching and etching holes; and forming a source electrode metal and a drain electrode metal, and forming a substrate electrode metal on the back surface of the turnover device.
Furthermore, in the present invention, the substrate may be directly selected from an SOI layer, the SOI layer is specifically formed by sequentially stacking a second conductivity type semiconductor layer 15, a buried oxide layer 14, and a first conductivity type semiconductor buffer layer 13 from bottom to top, and step 2 may be omitted when the first conductivity type semiconductor buffer layer 13 of the SOI layer reaches an actually required thickness.
Further, the material of the semiconductor in the present invention may be selected from silicon, germanium, silicon carbide, gallium nitride, gallium sesquioxide, or diamond.
The working principle of the invention is as follows:
on the basis of a transverse MOS type semiconductor power device, a deep dielectric groove and a semi-insulating polysilicon column region which is connected with a drift region in parallel along the transverse extension direction of the deep dielectric groove are introduced into the drift region to serve as a three-dimensional resistive field plate structure, and a buffer layer is introduced between the drift region and a substrate. When the source electrode 3, the trench gate electrode 1 and the substrate electrode 16 are connected with a low potential and the drain electrode 5 is connected with a high potential, the device is in a blocking state, at the moment, the conductive channel of the device is changed into a U-shaped conductive channel from a traditional transverse channel due to the existence of the deep medium trench in the drift region, and the length of the drift region is effectively increased under the condition of the same device length; meanwhile, due to the effect of a three-dimensional resistive field plate provided by a semi-insulating polysilicon SIPOS column region vertical to the deep dielectric trench, the device can form multi-dimensional depletion in multiple directions during blocking, so that the drift region and the buffer layer are completely depleted before the device is broken down, the doping concentration of the drift region and the buffer layer is increased, and the electric field distribution of the N-type drift region and the buffer layer is improved; meanwhile, the problem that the drift region cannot be completely exhausted due to the deep groove is solved, so that the device does not need to adopt the means of deepening the groove gate structure in order to maintain a certain depth of the deep dielectric groove in the traditional technology, the shallow groove gate structure can be realized, the gate capacitance of the device is reduced, and the switching speed of the device is increased; and because of the relatively high critical breakdown electric field of the deep dielectric groove medium, the device obtains high breakdown voltage and reduces specific on resistance/on voltage drop. Meanwhile, a semiconductor region with a doping type different from that of the drift region is introduced into the other side of the N-type drift region relative to the semi-insulating polysilicon SIPOS column region to form a super junction structure, so that a three-dimensional charge compensation effect can be further provided, an electric field in the drift region forms trapezoid-like distribution, the problem that the drift region cannot be completely depleted due to a thick drift region and a deep trench is solved, and the doping concentration of the drift region of the device is further improved; due to the three-dimensional depletion effect provided by the semi-insulating polysilicon SIPOS column region and the semiconductor region with the doping type different from that of the drift region, the width of the drift region at two sides of the deep trench can be wide under the condition of high doping concentration without being limited by the doping amount, the withstand voltage of the device is improved, and the on-resistance of the device is reduced. In addition, high-concentration N-type buffer layers are further introduced into the side wall and the bottom wall of the deep dielectric trench, the effect of reducing the surface electric field RESURF provided by the back buried oxide layer and the deep dielectric layer can be fully utilized to improve the doping concentration of a drift region, auxiliary depletion caused by different potentials at the two sides of the substrate and the deep dielectric trench is inhibited, the charge balance characteristic between semiconductor regions with different doping types in a super junction structure is improved, meanwhile, the high-concentration N-type buffer layers further reduce the on-resistance, and the performance and the reliability of the device are improved.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the deep dielectric groove and the semi-insulating polysilicon column region which is connected with the drift region in parallel along the transverse extension direction of the deep dielectric groove are introduced into the drift region and used as a three-dimensional resistive field plate structure, so that a conductive channel of a device is changed from a traditional transverse channel into a U-shaped conductive channel, the effective length of the drift region is increased under a certain device length, and the N-type drift region and the N-type buffer layer are fully depleted before the device is broken down by forming a multi-dimensional depletion function in multiple directions during blocking, so that the specific on-resistance is reduced while high device breakdown voltage is obtained; meanwhile, the introduction of the N-type buffer layer fully utilizes the effect of reducing the surface electric field RESURF provided by the back buried oxide layer and the deep trench dielectric layer to improve the doping concentration of the drift region, inhibits the auxiliary depletion caused by different potentials at the two sides of the substrate and the deep trench, further improves the withstand voltage of the device, reduces the specific on-resistance, saves the chip area and reduces the cost.
Drawings
Fig. 1 is a schematic structural diagram of a conventional deep trench L DMOS device, where 1 is a trench gate electrode, 2 is a trench gate dielectric layer, 3 is a source electrode, 4 is a deep dielectric trench, 5 is a drain electrode, 6 is an N + source region, 7 is a P-type base region, 8 is a P + contact region, 9 is an N-type drain region, 10 is an N-type drift region, 15 is a P-type semiconductor layer, and 16 is a substrate electrode.
Fig. 2 is a schematic structural diagram of an L DMOS device of embodiment 1;
fig. 3 is a schematic cross-sectional view of an L DMOS device of example 1 taken along line AB;
fig. 4 is a schematic cross-sectional view of an L DMOS device of example 1 along the CD;
fig. 5 is a schematic three-dimensional structure of an L DMOS device of embodiment 2;
fig. 6 is a schematic cross-sectional view of an L DMOS device of example 2 taken along line AB;
fig. 7 is a schematic cross-sectional view of an L DMOS device of example 2 along the CD;
fig. 8 is a schematic cross-sectional view of an L DMOS device of example 2 taken along EF;
fig. 9 is a schematic three-dimensional structure of an L DMOS device of embodiment 3;
fig. 10 is a schematic cross-sectional view of an L DMOS device of example 3 taken along line AB;
fig. 11 is a schematic cross-sectional view of an L DMOS device of example 3 along the CD;
fig. 12 is a schematic cross-sectional view of an L DMOS device of example 3 taken along EF;
fig. 13 is a schematic three-dimensional structure of an L DMOS device of example 4;
fig. 14 is a schematic cross-sectional view of an L DMOS device of example 4 taken along line AB;
fig. 15 is a schematic cross-sectional view of an L DMOS device of example 4 along the CD;
fig. 16 is a schematic cross-sectional view of an L DMOS device of example 4 taken along EF;
fig. 17 is a schematic three-dimensional structure of an L DMOS device of example 5;
fig. 18 is a schematic cross-sectional view of an L DMOS device of example 5 taken along line AB;
fig. 19 is a schematic cross-sectional view of an L DMOS device of example 5 along the CD;
in fig. 2 to 19: the structure comprises a groove gate electrode 1, a groove gate dielectric layer 2, a source electrode 3, a deep dielectric groove 4, a first field plate 104, a second field plate 402, a drain electrode 5, an N + source region 6, a P-type base region 7, a P + contact region 8, an N-type drain region 9, an N-type drift region 10 and semi-insulating polysilicon 11. 12 is an insulating medium layer, 13 is an N-type buffer layer, 14 is a buried oxide layer, 15 is a P-type semiconductor layer, 16 is a substrate electrode, 17 is a P-type column region, 18 is a side N-type buffer layer, and 19 is a bottom N-type buffer layer.
Detailed Description
So that those skilled in the art can readily understand the principles and concepts of the invention, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof that are illustrated in the appended drawings. The teachings of the present invention are not limited to any particular embodiment nor represent the best embodiment, and general alternatives known to those skilled in the art are also encompassed within the scope of the present invention.
Example 1:
the embodiment provides an L DMOS device, the cellular structure of which is shown in FIG. 2, the schematic cross-sectional structures along the AB line and the CD line of the cellular structure shown in FIG. 2 are shown in FIGS. 3 and 4, respectively, and when viewed from FIGS. 2 to 4, the cellular structure comprises a substrate electrode 16, a P-type semiconductor layer 15, a buried oxide layer 14, an N-type buffer layer 13 and an N-type drift region 10 which are vertically stacked from bottom to top, an N-type drain region 9 is arranged on one side of the surface of the N-type drift region 10, an MOS structure is arranged on the other side of the surface of the N-type drift region 10, the MOS structure comprises a P-type body region 7, an N + source region 6, a P + contact region 8, a trench gate structure and a source electrode 3, wherein the trench gate structure comprises a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side and the bottom of the trench gate electrode 1, a P-type body region 7 is arranged near one side of the N-type drain region 9 and is in contact with the trench gate structure, the N + source region 6 and the:
a deep dielectric trench 4 formed by a deep trench filled with a dielectric material is arranged in the N-type drift region 10 between the trench gate structure and the N-type drain region 9; the side surface of the deep dielectric groove 4 is contacted with a P + contact region 8 and a P type body region 7; a semi-insulating polysilicon column 11 arranged along the transverse extension direction of the deep dielectric trench 4 is also arranged in the N-type drift region 10; the semi-insulating polycrystalline silicon column 11, the P type body region 7 and the N type drift region 10 are in contact with the trench gate electrode 1 through the trench gate dielectric layer 2; an active electrode 3 is arranged on the upper surfaces of the semi-insulating polycrystalline silicon 11, the insulating medium layer 12, the N + source region 6 and the P + contact region 8; the source electrode 3 is isolated from the trench gate electrode 1 through a dielectric layer; the upper surfaces of the semi-insulating polysilicon 11 and the N-type drain region 9 are provided with a drain electrode 5.
In this embodiment, the thickness of the N-type buffer layer 13 is 0.5-2 μm; doping concentration of 1015～1017Per cm3(ii) a The width of the N-type drift region 10 along the z direction is 0.5-2 μm, the depth along the y direction is 5-25 μm, and the width along the x direction is 4-20 μm; doping concentration of 1015～1017Per cm3(ii) a The depth of the deep dielectric groove 4 along the y-axis direction is 5-20 μm, and the width along the x-axis direction is 2-10 μm.
Example 2:
this embodiment provides an L DMOS device, the cell structure of which is shown in fig. 5, the cross-sectional structure of the cell structure shown in fig. 5 along the line AB, the line CD and the line EF are shown in fig. 6, 7 and 8, respectively, and in combination with fig. 5 to 8, this embodiment is based on embodiment 1, and the N-drift region 10 is relatively far away from one of the semi-insulating polysilicon pillars 11A P-type column region 17 is arranged in the side, and the lower surface of the P-type column region 17 is in contact with the N-buffer layer 13; the P-type column regions 17 are connected with the N-drift region 10 in parallel along the lateral extension direction of the deep dielectric trench 4 and are alternately arranged to form a super junction structure. In this embodiment, the P-type column region 17 has a width of 0.5-1.5 μm along the z-axis direction, a longitudinal depth of 5-25 μm along the y-axis direction, a width of 4-20 μm along the x-axis direction, and a doping concentration of 1015～1017Per cm3. The introduction of the P-type column region 17 further provides a three-dimensional charge compensation effect, so that the electric field in the N-type drift region 10 forms a trapezoid-like distribution, and the doping concentration and the breakdown voltage of the drift region of the device are further improved.
Example 3:
this embodiment provides an L DMOS device, a cell structure of which is shown in fig. 9, and cross-sectional structural diagrams of the cell structure shown in fig. 9 along an AB line, a CD line, and an EF line are shown in fig. 10, 11, and 12, respectively, in this embodiment, on the basis of embodiment 2, a lateral N-type buffer layer 18 is disposed in an N-type drift region 10 and a P-type column region 17 below an N-type drain region 9 and closely attached to a sidewall of a deep dielectric trench 4, a doping concentration of the lateral N-type buffer layer 18 is not less than a doping concentration of the N-type drift region 10, the doping concentration of the lateral N-type buffer layer 18 may be uniformly doped or may be decreased from top to bottom, the introduction of the lateral N-type buffer layer 18 may suppress an influence of auxiliary depletion on charge balance between the N-type drift region 10 and the P-type column region 17 due to a difference in potentials at two sides of the deep trench, and further reduce.
Example 4:
this embodiment provides an L DMOS device, a cell structure of which is shown in fig. 13, and cross-sectional structure schematic diagrams of the cell structure shown in fig. 13 along an AB line, a CD line, and an EF line are shown in fig. 14, 15, and 16, respectively, in this embodiment, on the basis of embodiment 3, a bottom N-type buffer layer 19 is further disposed in the N-type drift region 10 and the P-type column region 17 below the deep dielectric trench 4 and clings to the bottom wall of the deep dielectric trench 4, a doping concentration of the bottom N-type buffer layer 19 is greater than a doping concentration of the N-type drift region 10, a doping concentration of the bottom N-type buffer layer 19 may be uniformly doped or decreases from right to left, introduction of the bottom N-type buffer layer 19 may suppress an influence of auxiliary depletion caused by a difference between a bottom of the deep trench and a source potential on charge balance between the N-type drift region 10 and the P-type column 17, and further reduce an on-resistance.
Example 5:
the present embodiment provides an L DMOS device, the cellular structure of which is shown in fig. 17, the schematic cross-sectional structures of the cellular structure shown in fig. 17 along the AB line and the CD line are respectively shown in fig. 18 and 19, the present embodiment is based on embodiment 1, a first field plate 401 and a second field plate 402 are introduced into the deep dielectric trench 4, the first field plate 401 and the second field plate 402 are arranged along the direction in which the N-type column region 10 and the semi-insulating polysilicon column 11 are connected in parallel, the longitudinal depth of the first field plate 401 and the longitudinal depth of the second field plate 402 are smaller than the longitudinal depth of the deep dielectric trench 4, the thicknesses of the first field plate 401 and the second field plate 402 and the edge of the deep dielectric trench 4 are adjustable, that is, a field plate with uniform dielectric layer thickness can be used, a step-type field plate can be used, and the thicknesses of the first field plate 401 and the second field plate 402 and the dielectric layer at the edge of the deep dielectric trench 4 adjacent side can be increased along the longitudinal direction, that is the y-axis direction shown in the figure.
Example 6:
the embodiment provides an L DMOS device, and on the basis of embodiment 4, a side P-type buffer layer is disposed in an N-type drift region 10 below a P-type body region 7 and clings to a sidewall of a deep dielectric trench 4, the doping concentration of the side P-type buffer layer may be uniformly doped or gradually decreased from top to bottom, and the introduction of the side P-type buffer layer can further suppress the influence of auxiliary depletion caused by different potentials at two sides of a deep trench on the charge balance of a super junction structure, so that the voltage resistance of the device is improved, and the on-resistance of the device is further reduced.
Example 7:
this embodiment provides an L DMOS device, and based on embodiment 1, the insulating dielectric layer 12 between the semi-insulating polysilicon pillar 11 and the deep dielectric trench 4, between the N-type buffer layer 13 and between the semi-insulating polysilicon pillar 11 and the N-type drift region 10 is omitted, that is, the semi-insulating polysilicon pillar 11 directly contacts with the deep dielectric trench 4, the N-type buffer layer 13 and the N-type drift region 10.
Example 8:
an L IGBT device comprises a substrate electrode 16, a P-type semiconductor layer 15, an oxygen buried layer 14, an N-type Buffer layer 13 and an N-type drift region 10 which are longitudinally stacked from bottom to top, wherein an N-type Buffer region and a P-type collector region are arranged on one side of the surface of the N-type drift region 10 and are independent from each other, the P-type collector region is arranged on the upper surface of the N-type Buffer region and is in contact with a deep dielectric trench 4, the P-type collector region is in contact with a metalized drain 5 above the P-type collector region, an MOS structure is arranged on the other side of the surface of the N-type drift region 10 and comprises a P-type body region 7, an N + source region 6, a P + contact region 8, a trench gate structure and a source electrode 3, the trench gate structure comprises a trench gate electrode 1 and a trench gate electrode 2 arranged on the side surface and the bottom surface of the trench gate electrode 1, the P-type body region 7 is arranged close to the N-type collector region and the P-type collector region and is in contact with the trench structure, the N + source region 6 and the P + contact region 8 are arranged on the top layer of the P-type collector region:
a deep dielectric trench 4 formed by a deep trench filled with a dielectric material is arranged in the N-type drift region 10 between the trench gate structure and the N-type Buffer region and the P-type collector region; the side surface of the deep dielectric groove 4 is contacted with a P + contact region 8 and a P type body region 7; a semi-insulating polysilicon column (comprising semi-insulating polysilicon 11 and an insulating dielectric layer 12) arranged along the transverse extension direction of the deep dielectric trench 4 is also arranged in the N-type drift region 10; the semi-insulating polycrystalline silicon 11, the P type body region 7 and the N type drift region 10 are in contact with the trench gate electrode 1 through the trench gate dielectric layer 2; an active electrode 3 is arranged on the upper surfaces of the semi-insulating polycrystalline silicon 11, the insulating medium layer 12, the N + source region 6 and the P + contact region 8; the source electrode 3 is isolated from the trench gate electrode 1 through the dielectric layer 2; and a drain electrode 5 is arranged on the upper surface of the P-type collector region of the semi-insulating polysilicon column.
As can be appreciated by those skilled in the art, all variations of the above embodiments are still applicable to the super junction IGBT device and will not be described herein.
Example 9:
the invention provides a preparation method of a transverse MOS device, which comprises the following steps:
the first step is as follows: selecting an SOI layer with a certain thickness as a substrate according to requirements, wherein the SOI material consists of an N-type buffer layer, an oxygen buried layer and a P-type substrate, and the doping concentration of the N-type buffer layer is 1015～1017Per cm3(ii) a The doping concentration of the P-type substrate is 1014～1015Per cm3；
The second step is that: extending an N-type drift region with a certain thickness on the substrate, wherein the doping concentration is 1015～1017Per cm3；
The third step: photoetching and etching the surface of the drift region to form a groove in the N-type drift region, forming a dielectric layer through high-temperature oxidation, and then depositing a semi-insulating polysilicon SIPOS film to fill the groove to form a semi-insulating polysilicon column region; removing redundant SIPOS material on the surface by a CMP process;
the fourth step: growing an oxide layer on the surface of the drift region, etching by adopting a photoetching process along a direction vertical to the interface of the N-drift region and the semi-insulating polysilicon column region to form a medium deep groove, then filling a silicon dioxide medium in the medium deep groove, and then removing redundant medium materials on the surface by a CMP process;
the fifth step: etching an N-type drift region on one side of the deep dielectric trench by adopting a photoetching process to form a gate trench, growing silicon dioxide on the surface of the gate trench through high-temperature oxidation to form a gate oxide layer, and then filling polycrystalline silicon to form a gate electrode; the depth of the gate trench is smaller than that of the deep dielectric trench;
and a sixth step: forming a P-type base region between the gate trench and the deep dielectric trench through ion implantation and high-temperature annealing; the depth of the P-type base region is smaller than that of the gate trench;
the seventh step: sequentially forming an N-type drain region, an N-type source region and a P-type contact region by ion implantation and annealing;
eighth step: depositing a dielectric layer, photoetching and etching holes; depositing metal on the surface of the device and etching to form a source electrode and a drain electrode; and the back side of the flip silicon chip is metallized to form a substrate electrode.
Further, the first step SOI material can also be directly selected from a P-type substrate material with a certain thickness, and the doping concentration of the P-type substrate is 1014～1015Per cm3。
It should be noted that the material of the substrate of the present invention may be selected from SOI substrate materials as an example, or may be a direct P-type semiconductor layer material, the semiconductor material used in the device of the present invention may be any suitable semiconductor material such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, diamond, etc., the dielectric insulating layer filled in the deep dielectric trench 4 of the present invention may be a single dielectric material, or may be a composite material formed by using different dielectric materials, such as any one or more of silicon dioxide, silicon nitride, sapphire or other suitable insulating dielectric materials.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A lateral MOS type power semiconductor device, a cell structure of which comprises: the semiconductor drift region comprises a substrate, a substrate electrode (16) arranged on the back surface of the substrate and a first conduction type semiconductor drift region (10) arranged on the front surface of the substrate; a first conductive type semiconductor drain region (9) is arranged on one side of the top layer of the first conductive type semiconductor drift region (10); an MOS structure is arranged on the other side of the top layer of the first conductive type semiconductor drift region (10), and comprises a second conductive type semiconductor body region (7), a first conductive type semiconductor source region (6), a second conductive type semiconductor contact region (8), a source electrode (3) and a trench gate structure; the trench gate structure comprises a trench gate electrode (1) and trench gate dielectric layers (2) arranged on the side surface and the bottom surface of the trench gate electrode (1); the second conductive type semiconductor body region (7) is arranged between the trench gate structure and the first conductive type semiconductor drain region (9) and is close to the trench gate structure; the second conductive type semiconductor body region (7) and the first conductive type semiconductor drift region (10) below the second conductive type semiconductor body region are in contact with the trench gate electrode (1) through the trench gate dielectric layer (2); a first conductive type semiconductor source region (6) and a second conductive type semiconductor contact region (8) are arranged side by side on the top layer of the second conductive type semiconductor body region (7), wherein the first conductive type semiconductor source region (6) is contacted with the trench gate electrode (1) through the lateral trench gate dielectric layer (2); the method is characterized in that:
a first conductive type semiconductor buffer layer (13) is arranged between the substrate and the first conductive type semiconductor drift region (10); the lower surface of the first conduction type semiconductor buffer layer (13) coincides with the upper surface of the substrate, and the upper surface of the first conduction type semiconductor buffer layer (13) coincides with the lower surface of the first conduction type semiconductor drift region (10); a deep dielectric trench (4) is arranged in a first conductive type semiconductor drift region (10) between the trench gate structure and the first conductive type semiconductor drain region (9); the side face of the deep medium groove (4) is contacted with the second conductive type semiconductor contact region (8) and the second conductive type semiconductor body region (7); the first conductive type semiconductor drift region (10) is also provided with a semi-insulating polysilicon groove, the semi-insulating polysilicon groove comprises semi-insulating polysilicon (11) and insulating dielectric layers (12) arranged on the side surfaces and the bottom surface of the semi-insulating polysilicon (11), the semi-insulating polysilicon groove is connected with the first conductive type semiconductor drift region (10) along the transverse extension direction of the deep dielectric groove (4), the semi-insulating polysilicon groove is divided into a first part, a second part, a third part and a fourth part which are sequentially connected with each other by a groove gate structure and the deep dielectric groove (4), the groove gate structure is positioned on the first part, the deep dielectric groove (4) is positioned on the third part, wherein the upper surface of the semi-insulating polysilicon groove is flush with the upper surface of the first conductive type semiconductor drain region (9), and the lower surface of the semi-insulating polysilicon groove is flush with the lower surface of the first conductive type semiconductor drift region (10), the rear surface of the semi-insulating polycrystalline silicon groove is flush with the rear surface of the trench gate structure, and the rear surface of the semi-insulating polycrystalline silicon groove is the surface opposite to the surface connected with the semi-insulating polycrystalline silicon groove and the first conduction type semiconductor drift region (10); the semi-insulating polycrystalline silicon (11) is contacted with the trench gate electrode (1) through the trench gate dielectric layer (2), and the active electrode (3) is arranged on the second part of the semi-insulating polycrystalline silicon trench, the first conductive type semiconductor source region (6) and the upper surface of the second conductive type semiconductor contact region (8); and a drain electrode (5) is arranged on the fourth part of the semi-insulating polycrystalline silicon groove and the upper surface of the first conduction type semiconductor drain region (9).
2. A lateral MOS-type power semiconductor device according to claim 1, characterized in that: replacing the first conductive type semiconductor drain region (9) with a first conductive type semiconductor Buffer region and a second conductive type semiconductor collector region which are mutually independent, wherein the second conductive type semiconductor collector region is arranged on the upper surface of the first conductive type semiconductor Buffer region; a second conductive type semiconductor collector region on the upper surface of the first conductive type semiconductor Buffer region is contacted with the deep medium groove (4); and the second conductive type semiconductor collector region is contacted with the upper drain electrode (5) to form the IGBT device.
3. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the first conduction type semiconductor drift region (10) is also internally provided with a second conduction type semiconductor column region (17), the second conduction type semiconductor column region (17) is transversely connected with the first conduction type semiconductor drift region (10) along the deep dielectric trench (4) and is clamped between the first conduction type semiconductor drift regions (10) on two sides, and the second conduction type semiconductor column region (17) is flush with the upper surface and the lower surface of the first conduction type semiconductor drift region (10).
4. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the longitudinal depth of the deep dielectric trench (4) is equal to or greater than the junction depth of the first conductivity type semiconductor drift region (10).
5. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: and a buffer layer tightly attached to the wall surface of the deep dielectric trench (4) is arranged in the first conductive type semiconductor drift region (10) below the first conductive type semiconductor drain region (9) and/or in the first conductive type semiconductor drift region (10) below the deep dielectric trench (4) and/or in the first conductive type semiconductor drift region (10) below the second conductive type semiconductor body region (7).
6. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the longitudinal depth of the trench gate electrode (1) is less than the longitudinal depth of the deep dielectric trench (4).
7. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the deep dielectric trench (4) is internally provided with a first field plate (401) and a second field plate (402) which are same with the deep dielectric trench in extension direction and are symmetrically arranged, and the longitudinal extension depth of the first field plate (401) and the second field plate (402) is smaller than that of the deep dielectric trench (4).
8. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the semi-insulating polysilicon groove penetrates through the deep medium groove (4).
9. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the first conductive type semiconductor is an N-type semiconductor, the second conductive type semiconductor is a P-type semiconductor, or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
10. A method for preparing a lateral MOS type power semiconductor device is characterized by comprising the following steps:
1) selecting a second conductive type semiconductor layer as a substrate;
2) forming a first conductive type semiconductor buffer layer on the second conductive type semiconductor layer;
3) forming a first conductive type semiconductor drift region on the first conductive type semiconductor buffer layer;
4) etching a groove in the first conduction type semiconductor drift region, forming an insulating medium layer on the inner wall of the groove, and filling semi-insulating polysilicon material in the groove to form a semi-insulating polysilicon groove which is connected with the first conduction type semiconductor drift region and has level upper and lower surfaces;
5) etching a deep groove along a direction vertical to a connecting interface of the first conductive type semiconductor drift region and the semi-insulating polycrystalline silicon groove, and filling a dielectric material in the deep groove to form a deep dielectric groove;
6) forming a trench gate structure in the first conductive type semiconductor drift region on one side of the deep dielectric trench;
7) forming a second conductive type semiconductor base region in the top layer of the first conductive type semiconductor drift region between the deep dielectric trench and the trench gate structure, wherein the junction depth of the second conductive type semiconductor base region is smaller than the longitudinal depth of the trench gate structure;
8) forming a first conductive type semiconductor source region and a second conductive type semiconductor contact region on the top layer of the second conductive type semiconductor base region;
9) forming a first conductive type semiconductor drain region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench, or forming a first conductive type semiconductor Buffer region and a second conductive type semiconductor collector region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench;
10) depositing a dielectric layer, photoetching and etching holes; and forming a source electrode metal and a drain electrode metal, and forming a substrate electrode metal on the back surface of the turnover device.
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| CN111933687B (en) * | 2020-07-07 | 2023-04-18 | 电子科技大学 | Lateral power device with high safety working area |
| CN112164750B (en) * | 2020-09-29 | 2024-10-22 | 上海晶丰明源半导体股份有限公司 | High density integrated active capacitor |
| CN114843332B (en) * | 2022-04-27 | 2023-04-25 | 电子科技大学 | Low-power-consumption high-reliability semi-package trench gate MOSFET device and preparation method thereof |
| CN115332323A (en) * | 2022-10-18 | 2022-11-11 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
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| CN117253924A (en) * | 2023-11-20 | 2023-12-19 | 深圳天狼芯半导体有限公司 | Silicon carbide LDMOS and preparation method |
| CN117878158A (en) * | 2024-03-08 | 2024-04-12 | 粤芯半导体技术股份有限公司 | Groove gate type LDMOS device and manufacturing method thereof |
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