CN109166924B - A lateral MOS type power semiconductor device and its preparation method - Google Patents

Abstract

The invention provides a transverse MOS device and a preparation method thereof, belonging to the technical field of semiconductor power devices. The invention introduces deep medium groove, semi-insulating polysilicon column and buffer layer into drift region of traditional lateral MOS type device. The introduction of the deep dielectric groove enables the device to form a U-shaped conductive channel, and the length of the drift region is effectively increased under the condition of the same device length; the semi-insulating polysilicon columns and the drift region are alternately connected along the transverse extension direction of the deep dielectric trench to form a three-dimensional resistive field plate structure, so that when the device is blocked, the multi-dimensional depletion effect is introduced into the drift region to improve the doping concentration of the drift region, the width of the drift region at two sides of the deep trench is not limited by the doping dose, the electric field distribution of the drift region is improved, the breakdown voltage of the device is improved, and the specific on-resistance/on-voltage drop of the device is also reduced. The introduction of the buffer layer can improve the charge balance characteristic of the three-dimensional medium super junction structure, so that the performance and the reliability of the device are further improved.

Description

A lateral MOS type power semiconductor device and its preparation method

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a lateral MOS type power semiconductor device and a preparation method thereof.

Background technique

With the rapid development of electronic technology, there is an urgent need for high-voltage integratable power MOS devices. Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) and Lateral Insulated Gate Bipolar Transistor (LIGBT) devices are widely used for their good thermal stability, high gain, low noise, and high compatibility with CMOS technology. In large-scale integrated circuits, it has become an indispensable part of the development of power integrated circuits. For traditional LDMOS (as shown in Figure 1) and LIGBT devices, if the voltage withstand capability of the device is to be increased, the length of the drift region must be increased to improve the device voltage withstand capability. However, this will increase the on-resistance/conduction of the device. The voltage drop increases, the power consumption increases, the chip area increases, and the cost increases. Although the industry has introduced the effect of double reduced surface electric field (RESURF) in the drift region, the improvement of device performance is very limited.

SUMMARY OF THE INVENTION

In view of the defects existing in the prior art, the present invention provides a lateral MOS type device and a preparation method thereof. By introducing a deep dielectric trench into the drift region of a traditional lateral MOS type device (LDMOS device/LIGBT device), the device forms a conductive type At the same time, a semi-insulating polysilicon (SIPOS) column is introduced, and the SIPOS column and the drift region are alternately connected along the lateral extension direction of the deep dielectric trench as a three-dimensional resistive field plate structure, which is further introduced in the drift region on the other side of the SIPOS column. The semiconductor region with the opposite doping type to the drift region provides a three-dimensional charge compensation effect, so that the multi-dimensional depletion effect is introduced into the drift region when the device is blocked to increase the doping concentration of the drift region, and make the drift region on both sides of the deep trench. The width is not limited by the dopant dose, improves the electric field distribution in the drift region, and reduces the specific on-resistance/on-voltage drop while increasing the breakdown voltage; further, by introducing a buffer layer to improve the charge balance characteristics of the three-dimensional dielectric superjunction structure , thereby further improving the performance and reliability of the device.

In order to achieve the above object, the technical scheme of the present invention is:

The present invention provides a MOS type power semiconductor device, specifically a laterally diffused metal oxide semiconductor device (LDMOS device):

An LDMOS device, its cell structure includes a substrate, a substrate electrode 16 disposed on the back of the substrate, and a first conductive type semiconductor drift region 10 on the front of the substrate; the top side of the first conductive type semiconductor drift region 10 is provided with The first conductive type semiconductor drain region 9; the other side of the top layer of the first conductive type semiconductor drift region 10 is provided with a MOS structure, the MOS structure includes a second conductive type semiconductor body region 7, a first conductive type semiconductor source region 6, The second conductive type semiconductor contact region 8, the source electrode 3 and the trench gate structure; the trench gate structure includes the trench gate electrode 1 and the trench gate dielectric layer 2 arranged on the side and bottom surfaces of the trench gate electrode 1; the second conductive type The type semiconductor body region 7 is arranged between the trench gate structure and the first conductivity type semiconductor drain region 9 and is arranged next to the trench gate structure; the second conductivity type semiconductor body region 7 and the first conductivity type semiconductor drift region 10 below it The trench gate electrode 1 is in contact with the trench dielectric layer 2; the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8 are arranged side by side on the top layer of the second conductive type semiconductor body region 7, wherein the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8 are arranged side by side on the top layer of the second conductive type semiconductor body region 7, wherein the first The conductive type semiconductor source region 6 is in contact with the trench gate electrode 1 through the trench dielectric layer 2 on the side surface; it is characterized in that:

A first conductive type semiconductor buffer layer 13 is disposed between the substrate and the first conductive type semiconductor drift region 10; the lower surface of the first conductive type semiconductor buffer layer 13 coincides with the upper surface of the substrate, and the first conductive type semiconductor buffer layer The upper surface of 13 coincides with the lower surface of the first conductive type semiconductor drift region 10; a deep dielectric trench is provided in the first conductive type semiconductor drift region 10 between the trench gate structure and the first conductive type semiconductor drain region 9 The side surface of the deep dielectric trench 4 is in contact with the second conductive type semiconductor contact region 8 and the second conductive type semiconductor body region 7; the first conductive type semiconductor drift region 10 is also provided with a semi-insulating polysilicon groove, The semi-insulating polysilicon trench includes semi-insulating polysilicon 11 and an insulating dielectric layer 12 disposed on the side and bottom surfaces of the semi-insulating polysilicon 11. The semi-insulating polysilicon trench extends laterally along the deep dielectric trench 4 to the first conductivity type semiconductor drift region. 10 are alternately connected, wherein the upper surface of the semi-insulating polysilicon trench is flush with the upper surface of the first conductivity type semiconductor drain region 9, and its lower surface is flush with the lower surface of the first conductivity type semiconductor drift region 10; the semi-insulating polysilicon 11 passes through The trench gate dielectric layer 2 is in contact with the trench gate electrode 1, and the upper surfaces of the semi-insulating polysilicon 11, the insulating dielectric layer 12, the first conductive type semiconductor source region 6, and the second conductive type semiconductor contact region 8 are provided with a source electrode 3 ; The source electrode 3 and the trench gate electrode 1 are separated by a dielectric layer; the upper surface of the semi-insulating polysilicon 11 and the drain region 9 of the first conductivity type semiconductor is provided with a drain electrode 5 .

Further, the present invention can use an SOI layer as a substrate, and the SOI layer specifically includes a second conductive type semiconductor layer 15, a buried oxide layer 14 and a first conductive type semiconductor buffer layer 13 that are sequentially stacked from bottom to top. The second conductive type semiconductor layer 15 may also be directly used as the substrate.

Further, the semiconductor material used in the device of the present invention can be selected from silicon, germanium, silicon carbide, gallium nitride, gallium trioxide or diamond.

Further, the deep dielectric trench is specifically formed by filling the deep trench with a dielectric material.

Further, the semi-insulating polysilicon trench is specifically formed by first forming an insulating dielectric layer 12 in the trench and then filling the semi-insulating polysilicon material.

Further, the longitudinal depth of the deep dielectric trench 4 may be equal to or greater than the junction depth of the first conductivity type semiconductor drift region 10 , that is, the deep dielectric trench 4 may extend to the first conductivity type semiconductor drift region 10 , and the The lower surface of the semiconductor drift region 10 overlaps and may also extend into the first conductive type semiconductor buffer layer 13 .

Further, the longitudinal depth of the deep dielectric trench 4 is greater than its width, that is, the aspect ratio of the deep dielectric trench 4 is less than 1.

Further, the longitudinal depth of the semi-insulating polysilicon trench may be greater than the longitudinal depth of the deep dielectric trench 4 , may also be smaller than the longitudinal depth of the deep dielectric trench 4 , and may also be equal to the longitudinal depth of the deep dielectric trench 4 .

Further, the semi-insulating polysilicon 11 is in contact with the trench gate electrode 1 through the trench gate dielectric layer 2 on the side.

Further, the junction depth of the second conductive type semiconductor body region 7 is smaller than the depth of the trench gate electrode 1 .

Further, the semi-insulating polysilicon trench runs through the deep dielectric trench 4 .

Further, the longitudinal depth of the trench gate electrode 1 is smaller than the longitudinal depth of the deep dielectric trench 4 .

Further, the first conductive type semiconductor drift region 10 is further provided with a second conductive type semiconductor column region 17 , and the second conductive type semiconductor column region 17 is in contact with the first conductive type semiconductor drift region 10 along the lateral direction of the deep dielectric trench 4 . And sandwiched between the first conductive type semiconductor drift regions 10 on both sides to avoid contact with semi-insulating polysilicon, and the second conductive type semiconductor pillar regions 17 are flush with the upper and lower surfaces of the first conductive type semiconductor drift region 10 .

Further, the first conductive type semiconductor buffer layer 18 is further provided in the first conductive type semiconductor drift region 10 under the first conductive type semiconductor drain region 9 , which is close to the sidewall of the deep dielectric trench 4 . The doping concentration of the first conductive type semiconductor buffer layer 18 on the side surface may be uniform doping, or may be gradually decreasing from top to bottom.

Further, the first conductive type semiconductor drift region 10 under the deep dielectric trench 4 is further provided with a bottom surface first conductive type semiconductor buffer layer 19 that is close to the bottom wall of the deep dielectric trench 4 . The doping concentration of the first conductive type semiconductor buffer layer 19 on the bottom surface may be uniform doping, or may be gradually decreased along the direction from the metallized drain electrode 5 to the metallized source electrode 3 .

Further, when the side first conductivity type semiconductor buffer layer 18 and the bottom first conductivity type semiconductor buffer layer 19 coexist, the doping concentration of the side first conductivity type semiconductor buffer layer 18 is not less than that of the bottom first conductivity type semiconductor buffer layer. 19 doping concentration.

Further, a side surface second conductive type semiconductor buffer layer close to the sidewall of the deep dielectric trench 4 is further provided in the first conductive type semiconductor drift region 10 under the second conductive type semiconductor body region 7 . The doping concentration of the side surface second conductive type semiconductor buffer layer may be uniform doping, or may be decreasing from top to bottom.

Further, the doping concentration of the first conductive type semiconductor buffer layer 13 , the side first conductive type semiconductor buffer layer 18 and the bottom first conductive type semiconductor buffer layer 18 is greater than that of the first conductive type semiconductor drift region 10 .

Further, the deep dielectric trench 4 is also provided with a first field plate 401 and a second field plate 402 which are symmetrically arranged in the same extending direction. The longitudinal extension depth of the first field plate 401 and the second field plate 402 is smaller than the longitudinal depth of the deep dielectric trench 4; the thickness of the dielectric layer between the first field plate 401 and the second field plate 402 from the edge of the deep dielectric trench 4 can be adjusted , that is, it can be set as a field plate with uniform thickness of the dielectric layer, or can be set as a stepped field plate, or the first field plate 401 and the second field plate 402 can be reasonably set so that the two are close to the adjacent side deep medium. The thickness of the dielectric layer at the edge of the trench 4 increases along the longitudinal direction.

The present invention provides a MOS type power semiconductor device, in particular a lateral insulated gate bipolar transistor (ie an LIGBT device):

An LIGBT device, its cell structure includes: a substrate, a substrate electrode 16 arranged on the backside of the substrate, and a first conductivity type semiconductor drift region 10 on the front side of the substrate; the first conductivity type semiconductor drift region 10 is provided on one side of the top layer There is a MOS structure, and the other side of the top layer of the first conductive type semiconductor drift region 10 is provided with a mutually independent first conductive type semiconductor buffer region and a second conductive type semiconductor collector region disposed on the upper surface of the first conductive type semiconductor buffer region; The second conductive type semiconductor collector region on the upper surface of the first conductive type semiconductor buffer region is in contact with the deep dielectric trench 4; the MOS structure includes a second conductive type semiconductor body region 7 and a first conductive type semiconductor source region 6 , a second conductivity type semiconductor contact region 8, a source electrode 3 and a trench gate structure; the trench gate structure includes a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side and bottom surfaces of the trench gate electrode 1; the second The conductive type semiconductor body region 7 is disposed between the trench gate structure and the first conductive type semiconductor buffer region and is disposed next to the trench gate structure; the second conductive type semiconductor body region 7 and the first conductive type semiconductor drift region 10 below it The trench gate electrode 1 is in contact with the trench dielectric layer 2; the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8 are arranged side by side on the top layer of the second conductive type semiconductor body region 7, wherein the first conductive type semiconductor source region 6 and the second conductive type semiconductor contact region 8 are arranged side by side on the top layer of the second conductive type semiconductor body region 7, wherein the first The conductive type semiconductor source region 6 is in contact with the trench gate electrode 1 through the trench dielectric layer 2 on the side surface; it is characterized in that:

A first conductive type semiconductor buffer layer 13 is disposed between the substrate and the first conductive type semiconductor drift region 10; the lower surface of the first conductive type semiconductor buffer layer 13 coincides with the upper surface of the substrate, and the first conductive type semiconductor buffer layer The upper surface of 13 coincides with the lower surface of the first conductive type semiconductor drift region 10; a deep dielectric trench is provided in the first conductive type semiconductor drift region 10 between the trench gate structure and the first conductive type semiconductor buffer region 4; the side surface of the deep dielectric trench 4 is in contact with the second conductive type semiconductor contact region 8 and the second conductive type semiconductor body region 7; the first conductive type semiconductor drift region 10 is also provided with a semi-insulating polysilicon groove, so The semi-insulating polysilicon trench includes semi-insulating polysilicon 11 and insulating dielectric layers 12 disposed on the side and bottom surfaces of the semi-insulating polysilicon 11, and the semi-insulating polysilicon trench is connected to the first conductivity type semiconductor drift region along the lateral extension direction of the deep dielectric trench 4. 10 are alternately connected, wherein the upper surface of the semi-insulating polysilicon trench is flush with the upper surface of the second conductivity type semiconductor collector region, and its lower surface is flush with the lower surface of the first conductivity type semiconductor drift region 10; the semi-insulating polysilicon 11 The trench gate dielectric layer 2 is in contact with the trench gate electrode 1, and source electrodes are provided on the upper surfaces of the semi-insulating polysilicon 11, the insulating dielectric layer 12, the first conductive type semiconductor source region 6, and the second conductive type semiconductor contact region 8 3; the source electrode 3 and the trench gate electrode 1 are separated by a dielectric layer; the semi-insulating polysilicon trench and the upper surface of the first conductive type semiconductor drain region 9 are provided with a drain electrode 5 .

Further, the present invention can use an SOI layer as a substrate, and the SOI layer specifically includes a second conductive type semiconductor layer 15, a buried oxide layer 14 and a first conductive type semiconductor buffer layer 13 that are sequentially stacked from bottom to top. The second conductive type semiconductor layer 15 may also be directly used as the substrate.

Further, the semiconductor material used in the device of the present invention can be selected from silicon, germanium, silicon carbide, gallium nitride, gallium trioxide or diamond.

Further, the deep dielectric trench is specifically formed by filling the deep trench with a dielectric material.

Further, the semi-insulating polysilicon trench is specifically formed by first forming an insulating dielectric layer 12 in the trench and then filling the semi-insulating polysilicon material.

Further, the longitudinal depth of the deep dielectric trench 4 may be equal to or greater than the junction depth of the first conductivity type semiconductor drift region 10 , that is, the deep dielectric trench 4 may extend to the first conductivity type semiconductor drift region 10 , and the The lower surface of the semiconductor drift region 10 overlaps and may also extend into the first conductive type semiconductor buffer layer 13 .

Further, the longitudinal depth of the deep dielectric trench 4 is greater than its width, that is, the aspect ratio of the deep dielectric trench 4 is less than 1.

Further, the longitudinal depth of the semi-insulating polysilicon trench may be greater than the longitudinal depth of the deep dielectric trench 4 , may also be smaller than the longitudinal depth of the deep dielectric trench 4 , and may also be equal to the longitudinal depth of the deep dielectric trench 4 .

Further, the semi-insulating polysilicon 11 is in contact with the trench gate electrode 1 through the trench gate dielectric layer 2 on the side.

Further, the junction depth of the second conductive type semiconductor body region 7 is smaller than the depth of the trench gate electrode 1 .

Further, the semi-insulating polysilicon trench runs through the deep dielectric trench 4 .

Further, the longitudinal depth of the trench gate electrode 1 is smaller than the longitudinal depth of the deep dielectric trench 4 .

Further, the first conductive type semiconductor drift region 10 is further provided with a second conductive type semiconductor column region 17 , and the second conductive type semiconductor column region 17 is in contact with the first conductive type semiconductor drift region 10 along the lateral direction of the deep dielectric trench 4 . and sandwiched between the first conductivity type semiconductor drift regions 10 on both sides to avoid contact with the semi-insulating polysilicon pillars, and the second conductivity type semiconductor pillar regions 17 are flush with the upper and lower surfaces of the first conductivity type semiconductor drift regions 10 .

Further, the first conductive type semiconductor buffer layer 18 is further provided in the first conductive type semiconductor drift region 10 below the second conductive type semiconductor collector region 9 , which is close to the sidewall of the deep dielectric trench 4 . The doping concentration of the first conductive type semiconductor buffer layer 18 on the side surface may be uniform doping, or may be gradually decreasing from top to bottom.

Further, the first conductive type semiconductor drift region 10 under the deep dielectric trench 4 is further provided with a bottom surface first conductive type semiconductor buffer layer 19 that is close to the bottom wall of the deep dielectric trench 4 . The doping concentration of the first conductive type semiconductor buffer layer 19 on the bottom surface may be uniform doping, or may be gradually decreased along the direction from the metallized drain electrode 5 to the metallized source electrode 3 .

Further, when the side first conductivity type semiconductor buffer layer 18 and the bottom first conductivity type semiconductor buffer layer 19 coexist, the doping concentration of the side first conductivity type semiconductor buffer layer 18 is not less than that of the bottom first conductivity type semiconductor buffer layer. 19 doping concentration.

Further, a side surface second conductive type semiconductor buffer layer close to the sidewall of the deep dielectric trench 4 is further provided in the first conductive type semiconductor drift region 10 under the second conductive type semiconductor body region 7 . The doping concentration of the side surface second conductive type semiconductor buffer layer may be uniform doping, or may be decreasing from top to bottom.

Further, the doping concentration of the first conductive type semiconductor buffer layer 13 , the side first conductive type semiconductor buffer layer 18 and the bottom first conductive type semiconductor buffer layer 18 is greater than that of the first conductive type semiconductor drift region 10 .

Further, the deep dielectric trench 4 is also provided with a first field plate 401 and a second field plate 402 which are symmetrically arranged in the same extending direction. The longitudinal extension depth of the first field plate 401 and the second field plate 402 is smaller than the longitudinal depth of the deep dielectric trench 4; the thickness of the dielectric layer between the first field plate 401 and the second field plate 402 from the edge of the deep dielectric trench 4 can be adjusted , that is, it can be set as a field plate with uniform thickness of the dielectric layer, or can be set as a stepped field plate, or the first field plate 401 and the second field plate 402 can be reasonably set so that the two are close to the adjacent side deep medium. The thickness of the dielectric layer at the edge of the trench 4 increases along the longitudinal direction.

In addition, the present invention also provides a preparation method of a lateral MOS type power semiconductor device, which is characterized by comprising the following steps:

(1) select the second conductive type semiconductor layer as the substrate;

(2) forming a first conductive type semiconductor buffer layer on the second conductive type semiconductor layer;

(3) forming a first conductivity type semiconductor drift region on the first conductivity type semiconductor buffer layer;

(4) by etching a trench in the first conductivity type semiconductor drift region, forming an insulating dielectric layer on the inner wall of the trench and filling the trench with semi-insulating polysilicon material, forming a contact with the first conductivity type semiconductor drift region and Semi-insulating polysilicon pillars with flush upper and lower surfaces;

(5) etching a deep groove along the direction perpendicular to the interface between the first conductivity type semiconductor drift region and the semi-insulating polysilicon column, and filling the deep groove with a dielectric material to form a deep dielectric groove;

(6) forming a trench gate structure in the first conductivity type semiconductor drift region on one side of the deep dielectric trench;

(7) A second conductivity type semiconductor base region is formed in the top layer of the first conductivity type semiconductor drift region between the deep dielectric trench and the trench gate structure, and the junction depth of the second conductivity type semiconductor base region is smaller than that of the trench gate structure. longitudinal depth;

(8) forming a first conductive type semiconductor source region and a second conductive type semiconductor contact region on the top layer of the second conductive type semiconductor base region;

(9) forming a first conductivity type semiconductor drain region on the top layer of the first conductivity type semiconductor drift region on the other side of the deep dielectric trench, or forming a first conductivity type semiconductor drain region on the top layer of the first conductivity type semiconductor drift region on the other side of the deep dielectric trench a conductive type semiconductor buffer region and a second conductive type semiconductor collector region;

(10) Depositing a dielectric layer, photolithography, and hole etching; forming source electrode metal and drain electrode metal, and flipping the device to form a substrate electrode metal on the backside.

Further, in the present invention, the substrate can directly select the SOI layer, and the SOI layer specifically includes the second conductive type semiconductor layer 15, the buried oxide layer 14 and the first conductive type semiconductor buffer layer 13 which are sequentially stacked from bottom to top. , Step 2 can be omitted when the first conductive type semiconductor buffer layer 13 of the SOI layer reaches the actual required thickness.

Further, the material of the semiconductor in the present invention can be selected from silicon, germanium, silicon carbide, gallium nitride, gallium trioxide or diamond.

The working principle of the present invention is as follows:

Based on the lateral MOS type semiconductor power device, the invention introduces a deep dielectric trench in the drift region and a semi-insulating polysilicon pillar region parallel to the drift region along the lateral extension direction of the deep dielectric trench as a three-dimensional resistive field plate structure and introduce a buffer layer between the drift region and the substrate. When the source electrode 3, the trench gate electrode 1, and the substrate electrode 16 are connected to a low potential, and the drain electrode 5 is connected to a high potential, the device is in a blocking state. At this time, due to the existence of the deep dielectric trench in the drift region, the conductive channel of the device is From the traditional lateral channel to the U-shaped conductive channel, the length of the drift region is effectively increased under the same device length; at the same time, due to the three-dimensional resistive field plate effect provided by the semi-insulating polysilicon SIPOS pillar region perpendicular to the deep dielectric trench , the device will form multi-dimensional depletion in multiple directions when blocking, so that the drift region and buffer layer are completely depleted before the device breaks down, so as to increase the doping concentration of the drift region and buffer layer and improve the N-type The electric field distribution of the drift region and the buffer layer; at the same time, it is precisely because the present invention overcomes the problem that the drift region cannot be completely depleted due to the deep trench, so the device of the present invention does not need to adopt the traditional technology in order to maintain a certain depth of the deep dielectric trench. The method of deepening the trench gate structure can realize a shallow trench gate structure, thereby reducing the gate capacitance of the device and improving the switching speed of the device; and, due to the relatively high critical breakdown electric field of the deep dielectric trench dielectric, the device can achieve high performance. The breakdown voltage at the same time reduces the specific on-resistance/on-voltage drop. At the same time, a semiconductor region with a different doping type from the drift region is introduced on the other side of the N-type drift region relative to the semi-insulating polysilicon SIPOS column region to form a superjunction structure, which can further provide three-dimensional charge compensation and make the electric field in the drift region form a similar The trapezoidal distribution overcomes the problem that the drift region cannot be completely depleted due to thick drift regions and deep trenches, and further improves the doping concentration of the device drift region; due to the semi-insulating polysilicon SIPOS column region and the drift region doping type The three-dimensional depletion effect provided by different semiconductor regions makes the width of the drift region on both sides of the deep trench not limited by the amount of dopant, and a wide width can be used under high doping concentration, which can improve the withstand voltage of the device and reduce the On-resistance of the device. In addition, a high concentration N-type buffer layer is further introduced into the sidewall and bottom wall of the deep dielectric trench, which can make full use of the reduced surface electric field RESURF provided by the back buried oxide layer and the deep trench dielectric layer to increase the doping concentration of the drift region. It also suppresses the auxiliary depletion caused by different potentials on both sides of the substrate and the deep dielectric trench, improves the charge balance between semiconductor regions with different doping types in the superjunction structure, and further reduces the high concentration of the N-type buffer layer. The on-resistance is improved, and the performance and reliability of the device are improved.

Compared with the prior art, the beneficial effects of the present invention are as follows:

In the present invention, a deep dielectric trench and a semi-insulating polysilicon pillar region parallel to the drift region along the lateral extension direction of the deep dielectric trench are introduced into the drift region as a three-dimensional resistive field plate structure, so that the conductive channel of the device is changed from the traditional lateral The channel becomes a U-type conduction channel, which increases the effective length of the drift region under a certain device length, and causes the N-type drift region and the N-type buffer layer to hit the device by forming multi-dimensional depletion in multiple directions during blocking. It is fully depleted before breaking through, which reduces the specific on-resistance while obtaining a high device breakdown voltage; at the same time, the introduction of the N-type buffer layer makes full use of the lower surface electric field RESURF provided by the back buried oxide layer and the deep trench dielectric layer. While increasing the doping concentration of the drift region, the auxiliary depletion caused by different potentials on both sides of the substrate and the deep trench is suppressed, which further improves the withstand voltage of the device, reduces the specific on-resistance, and saves the chip area. Reduced costs.

Description of drawings

1 is a schematic structural diagram of a traditional deep trench LDMOS device; wherein: 1 is a trench gate electrode, 2 is a trench gate dielectric layer, 3 is a source electrode, 4 is a deep dielectric trench, 5 is a drain electrode, and 6 is an N+ source Polar region, 7 is a P-type base region, 8 is a P+ contact region, 9 is an N-type drain region, 10 is an N-type drift region, 15 is a P-type semiconductor layer, and 16 is a substrate electrode.

2 is a schematic structural diagram of an LDMOS device in Embodiment 1;

Fig. 3 is the cross-sectional schematic diagram of a kind of LDMOS device of embodiment 1 along AB;

4 is a schematic cross-sectional view of an LDMOS device along CD in Embodiment 1;

Fig. 5 is the three-dimensional structure schematic diagram of a kind of LDMOS device of embodiment 2;

Fig. 6 is the cross-sectional schematic diagram of a kind of LDMOS device of embodiment 2 along AB;

7 is a schematic cross-sectional view of an LDMOS device along CD in Embodiment 2;

8 is a schematic cross-sectional view of an LDMOS device in Embodiment 2 along EF;

Fig. 9 is the three-dimensional structure schematic diagram of a kind of LDMOS device of embodiment 3;

10 is a schematic cross-sectional view of an LDMOS device along AB in Embodiment 3;

11 is a schematic cross-sectional view of an LDMOS device along CD in Embodiment 3;

12 is a schematic cross-sectional view of an LDMOS device along EF in Embodiment 3;

13 is a schematic diagram of a three-dimensional structure of an LDMOS device in Embodiment 4;

14 is a schematic cross-sectional view of an LDMOS device along AB in Embodiment 4;

15 is a schematic cross-sectional view of an LDMOS device along CD in Embodiment 4;

16 is a schematic cross-sectional view of an LDMOS device along EF in Embodiment 4;

17 is a schematic diagram of a three-dimensional structure of an LDMOS device in Embodiment 5;

18 is a schematic cross-sectional view of an LDMOS device along AB in Embodiment 5;

19 is a schematic cross-sectional view of an LDMOS device along CD in Embodiment 5;

2 to 19: 1 is the trench gate electrode, 2 is the trench gate dielectric layer, 3 is the source electrode, 4 is the deep dielectric trench, 104 is the first field plate, 402 is the second field plate, 5 is the leakage current 6 is the N+ source region, 7 is the P-type base region, 8 is the P+ contact region, 9 is the N-type drain region, 10 is the N-type drift region, and 11 is the semi-insulating polysilicon. 12 is an insulating dielectric layer, 13 is an N-type buffer layer, 14 is a buried oxide layer, 15 is a P-type semiconductor layer, 16 is a substrate electrode, 17 is a P-type pillar region, 18 is a side N-type buffer layer, and 19 is the bottom surface N-type buffer layer.

Detailed ways

In order to make the solution and principle of the present invention clear to those skilled in the art, the following detailed description is given in conjunction with the accompanying drawings and specific embodiments. The content of the present invention is not limited to any specific embodiment, nor does it represent the best embodiment, and general substitutions known to those skilled in the art are also included within the protection scope of the present invention.

Example 1:

This embodiment provides an LDMOS device, the cell structure of which is shown in FIG. 2 , and the schematic cross-sectional structure diagrams of the cell structure shown in FIG. 2 along the AB line and the CD line are respectively shown in FIGS. 3 and 4 . From the point of view, the cell structure includes: the substrate electrode 16, the P-type semiconductor layer 15, the buried oxide layer 14, the N-type buffer layer 13 and the N-type drift region 10, which are stacked vertically from bottom to top; the N-type drift region 10 One side of the surface is provided with an N-type drain region 9; the other side of the surface of the N-type drift region 10 is provided with a MOS structure, the MOS structure includes a P-type body region 7, an N+ source region 6, a P+ contact region 8, and a trench gate. Structure and source electrode 3, wherein the trench gate structure includes a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side and bottom surfaces of the trench gate electrode 1, and the P-type body region 7 is arranged on the side close to the N-type drain region 9 And in contact with the trench gate structure, the N+ source region 6 and the P+ contact region 8 are arranged on the top layer of the P-type body region 7, and the N+ source region 6 is arranged close to the side of the trench gate structure; it is characterized in that:

The N-type drift region 10 between the trench gate structure and the N-type drain region 9 is provided with a deep dielectric trench 4 formed by a deep trench filled with a dielectric material; the side surface of the deep dielectric trench 4 is in contact with P+ The N-type drift region 10 is also provided with semi-insulating polysilicon pillars 11 arranged along the lateral extension direction of the deep dielectric trench 4; the semi-insulating polysilicon pillars 11 and the P-type body region 7 The N-type drift region 10 is in contact with the trench gate electrode 1 through the trench gate dielectric layer 2; the upper surfaces of the semi-insulating polysilicon 11, the insulating dielectric layer 12, the N+ source region 6, and the P+ contact region 8 are provided with a source electrode 3; The source electrode 3 and the trench gate electrode 1 are separated from each other by a dielectric layer; the semi-insulating polysilicon 11 and the upper surface of the N-type drain region 9 are provided with a drain electrode 5 .

In this embodiment, the thickness of the N-type buffer layer 13 is 0.5 to 2 μm; the doping concentration is 10 ¹⁵ to 10 ¹⁷ pieces/cm ³ ; the width of the N-type drift region 10 along the z direction is 0.5 to 2 μm, and the depth along the y direction is 0.5 to 2 μm. 5-25μm, the width along the x-direction is 4-20μm; the doping concentration is 10 ^{15-10 17} pieces/cm ³ ; the depth of the deep dielectric trench 4 along the y-axis direction is 5-20μm, along the x-axis direction The width is 2 to 10 μm.

Example 2:

This embodiment provides an LDMOS device, the cell structure of which is shown in FIG. 5 , and the schematic cross-sectional structures of the cell structure shown in FIG. 5 along the AB line, the CD line and the EF line are respectively shown in FIGS. Referring to FIGS. 5 to 8 , this embodiment is based on Embodiment 1, and a P-type pillar region 17 is provided on the side of the N-drift region 10 relatively far from the semi-insulating polysilicon pillar 11 , and the P-type pillar region 17 The lower surface of the P-type pillar region 17 is in contact with the N-drift region 10 along the lateral extension direction of the deep dielectric trench 4 and is alternately arranged to form a super junction structure. In this embodiment, the width of the P-type pillar region 17 along the z-axis direction is 0.5-1.5 μm, the longitudinal depth along the y-axis direction is 5-25 μm, the width along the x-axis direction is 4-20 μm, and the doping concentration is 10 ¹⁵ ~10 ¹⁷ /cm ³ . The introduction of the P-type pillar region 17 further provides three-dimensional charge compensation, so that the electric field in the N-type drift region 10 forms a trapezoidal-like distribution, and further improves the doping concentration and breakdown voltage of the device drift region.

Example 3:

This embodiment provides an LDMOS device, the cell structure of which is shown in FIG. 9 , and the schematic cross-sectional structures of the cell structure shown in FIG. 9 along the AB line, the CD line, and the EF line are shown in FIGS. 10 , 11 and 12 respectively. In this embodiment, on the basis of Embodiment 2, a side N-type buffer layer 18 that is close to the sidewall of the deep dielectric trench 4 is provided in the N-type drift region 10 and the P-type pillar region 17 under the N-type drain region 9, The doping concentration of the side N-type buffer layer 18 is not less than the doping concentration of the N-type drift region 10 . The doping concentration of the side N-type buffer layer 18 may be uniform doping, or may be decreasing from top to bottom. The introduction of the side N-type buffer layer 18 can suppress the influence of the auxiliary depletion on the charge balance of the N-type drift region 10 and the P-type pillar region 17 due to the different potentials on both sides of the deep trench. On-resistance of small devices.

Example 4:

This embodiment provides an LDMOS device, the cell structure of which is shown in FIG. 13 , and the schematic cross-sectional structures of the cell structure shown in FIG. 13 along the AB line, the CD line, and the EF line are shown in FIGS. In this embodiment, on the basis of Embodiment 3, a bottom N-type buffer layer close to the bottom wall of the deep dielectric trench 4 is further provided in the N-type drift region 10 and the P-type pillar region 17 under the deep dielectric trench 4 19. The doping concentration of the bottom N-type buffer layer 19 is greater than the doping concentration of the N-type drift region 10 . The doping concentration of the bottom N-type buffer layer 19 may be uniform doping, or may decrease from right to left. The introduction of the N-type buffer layer 19 on the bottom surface can suppress the influence of the auxiliary depletion on the charge balance of the N-type drift region 10 and the P-pillar 17 caused by the difference in the potential of the bottom of the deep trench and the source electrode, and further reduce the voltage of the device while improving the withstand voltage of the device. On-resistance of small devices.

Example 5:

This embodiment provides an LDMOS device, the cell structure of which is shown in FIG. 17 , and the schematic cross-sectional structures of the cell structure shown in FIG. 17 along the AB line and the CD line are respectively shown in FIGS. 18 and 19 . In this embodiment, on the basis of Embodiment 1, the first field plate 401 and the second field plate 402 arranged in the parallel connection direction of the N-type column region 10 and the semi-insulating polysilicon column 11 are introduced into the deep dielectric trench 4, so the The longitudinal depth of the first field plate 401 and the second field plate 402 is smaller than the longitudinal depth of the deep dielectric trench 4 . The thickness of the dielectric layer at the edge of the first field plate 401 and the second field plate 402 and the deep dielectric trench 4 can be adjusted, that is, a field plate with a uniform thickness of the dielectric layer can be used, a stepped field plate can be used, or the The positions of the field plate 401 and the second field plate 402 are such that the thickness of the dielectric layers adjacent to the edge of the side deep dielectric trench 4 increases along the longitudinal direction, that is, the y-axis direction shown in the figure. The introduction of the first field plate 401 and the second field plate 402 can further adjust the electric field in the N-type drift region 10 and the semi-insulating polysilicon pillar 11 on both sides of the deep dielectric trench 4, and further improve the withstand voltage of the device.

Example 6:

This embodiment provides an LDMOS device. On the basis of Embodiment 4, a side P-type buffer layer close to the sidewall of the deep dielectric trench 4 is provided in the N-type drift region 10 under the P-type body region 7 . The doping concentration of the side P-type buffer layer can be uniform doping, or it can be decreasing from top to bottom. The introduction of the side P-type buffer layer can further suppress the influence of the auxiliary depletion on the charge balance of the superjunction structure due to the different potentials on both sides of the deep trench, and further reduce the on-resistance of the device while improving the withstand voltage of the device.

Example 7:

This embodiment provides an LDMOS device. On the basis of Embodiment 1, the insulating dielectric layer 12 between the semi-insulating polysilicon pillar 11 and the deep dielectric trench 4 , the N-type buffer layer 13 and the N-type drift region 10 is omitted. That is, the semi-insulating polysilicon pillar 11 is in direct contact with the deep dielectric trench 4 , the N-type buffer layer 13 and the N-type drift region 10 . In this way, the process can be further simplified and the cost can be reduced on the basis of maintaining the device characteristics.

Example 8:

An LIGBT device, the cell structure includes: a substrate electrode 16, a P-type semiconductor layer 15, a buried oxide layer 14, an N-type buffer layer 13 and an N-type drift region 10 stacked vertically from bottom to top; an N-type drift region One side of the surface of the region 10 is provided with an independent and mutually independent N-type Buffer region and a P-type collector region arranged on the upper surface of the N-Buffer region; the P-type collector region on the upper surface of the N-Buffer region is in contact with the deep dielectric trench 4 The P-type collector region is in contact with the upper metallized drain 5; the other side of the surface of the N-type drift region 10 is provided with a MOS structure, which includes a P-type body region 7, an N+ source region 6, and a P+ contact region 8. A trench gate structure and a source electrode 3, wherein the trench gate structure includes a trench gate electrode 1 and a trench gate dielectric layer 2 arranged on the side and bottom surfaces of the trench gate electrode 1, and the P-type body region 7 is close to the N-type Buffer The N+ source region 6 and the P+ contact region 8 are arranged on the top layer of the P-type body region 7, and the N+ source region 6 is close to the trench The gate structure is arranged on one side; it is characterized in that:

The N-type drift region 10 between the trench gate structure and the N-type buffer region and the P-type collector region is provided with a deep dielectric trench 4 formed by a deep trench filled with a dielectric material; the deep dielectric trench 4 The side surface of the N-type is in contact with the P+ contact region 8 and the P-type body region 7; the N-type drift region 10 is also provided with semi-insulating polysilicon pillars (including semi-insulating polysilicon 11 and insulating dielectric layer 12); semi-insulating polysilicon 11, P-type body region 7 and N-type drift region 10 are in contact with trench gate electrode 1 through trench gate dielectric layer 2; semi-insulating polysilicon 11, insulating dielectric layer 12, N+ source region 6. The upper surface of the P+ contact region 8 is provided with a source electrode 3; the source electrode 3 and the trench gate electrode 1 are separated by the dielectric layer 2; the upper surface of the semi-insulating polysilicon column P-type collector region is provided with a drain electrode 5.

Those skilled in the art know that all the modifications of the above embodiments are still applicable to superjunction IGBT devices, and details are not described herein again.

Example 9:

A preparation method of a lateral MOS type device provided by the present invention comprises the following steps:

Step 1: Select a SOI layer with a certain thickness as the substrate as needed. The SOI material consists of an N-type buffer layer, a buried oxide layer, and a P-type substrate. The doping concentration of the N-type buffer layer is 10 ¹⁵ ～ 10 ¹⁷ pieces/cm ³ ; the doping concentration of the P-type substrate is 10 ¹⁴ to 10 ¹⁵ pieces/cm ³ ;

The second step: epitaxy an N-type drift region with a certain thickness on the substrate, and the doping concentration is 10 ¹⁵ to 10 ¹⁷ /cm ³ ;

The third step: photolithography and etching the N-type drift region on the surface of the drift region to form a trench, and a dielectric layer is formed by high temperature oxidation, and then a semi-insulating polysilicon SIPOS film is deposited to fill the trench to form a semi-insulating polysilicon pillar region; and Remove excess SIPOS material on the surface by CMP process;

The fourth step: grow an oxide layer on the surface of the drift region, and use a photolithography process to etch the dielectric deep groove in the direction perpendicular to the interface between the N-drift region and the semi-insulating polysilicon pillar region, and then fill the dielectric deep groove with two Silicon oxide dielectric, and then remove excess dielectric material on the surface by CMP process;

Step 5: A gate trench is formed by etching the N-type drift region on one side of the deep dielectric trench by photolithography, and silicon dioxide is grown on the surface of the gate trench through high temperature oxidation to form a gate oxide layer, and then polysilicon is filled to form a gate. electrode; the depth of the gate trench is less than the depth of the deep dielectric trench;

The sixth step: forming a P-type base region between the gate trench and the deep dielectric trench by ion implantation and high temperature annealing; the depth of the P-type base region is less than that of the gate trench;

Step 7: N-type drain region, N-type source region and P-type contact region are sequentially formed by ion implantation and annealing;

The eighth step: depositing a dielectric layer, photolithography, and hole etching; depositing metal on the surface of the device and etching to form source and drain electrodes; flipping the backside of the silicon wafer to metallize to form a substrate electrode.

In the further first step SOI material, a P-type substrate material with a certain thickness can also be directly selected, and the doping concentration of the P-type substrate is 10 ¹⁴ -10 ¹⁵ /cm ³ .

It should be particularly noted that, the material of the substrate of the present invention can be generally selected from the SOI substrate material as in the embodiment, or the material of the P-type semiconductor layer can be directly selected. The semiconductor material used in the device of the present invention can be any suitable semiconductor material such as silicon, germanium, silicon carbide, gallium nitride, gallium trioxide, and diamond. The dielectric layer insulating layer filled in the deep dielectric trench 4 of the present invention can be made of a single dielectric material, or a composite material formed of different dielectric materials, such as silicon dioxide, silicon nitride, sapphire or other suitable insulating media. any one or more of the materials. In addition, in order to simplify the description, the device structure and preparation method are described by taking an N-channel LDMOS device as an example, but the present invention is also applicable to a P-channel LDMOS device. The enumerated embodiments of the present invention and their relationship with the foregoing embodiments are not exhaustive or limiting, and all technical solutions obtained by those skilled in the art by combining multiple technical features on the basis of the disclosure of the present specification are within the protection scope of the present invention. In addition, the process steps and process conditions in the device preparation method of the present invention can be added, deleted and adjusted according to actual needs.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative rather than restrictive. Under the inspiration of the present invention, many modifications can be made without departing from the spirit of the present invention and the protection scope of the claims, which all belong to the protection of the present invention.

Claims (10)

1. A lateral MOS type power semiconductor device, a cell structure of which comprises: the semiconductor drift region comprises a substrate, a substrate electrode (16) arranged on the back surface of the substrate and a first conduction type semiconductor drift region (10) arranged on the front surface of the substrate; a first conductive type semiconductor drain region (9) is arranged on one side of the top layer of the first conductive type semiconductor drift region (10); an MOS structure is arranged on the other side of the top layer of the first conductive type semiconductor drift region (10), and comprises a second conductive type semiconductor body region (7), a first conductive type semiconductor source region (6), a second conductive type semiconductor contact region (8), a source electrode (3) and a trench gate structure; the trench gate structure comprises a trench gate electrode (1) and trench gate dielectric layers (2) arranged on the side surface and the bottom surface of the trench gate electrode (1); the second conductive type semiconductor body region (7) is arranged between the trench gate structure and the first conductive type semiconductor drain region (9) and is close to the trench gate structure; the second conductive type semiconductor body region (7) and the first conductive type semiconductor drift region (10) below the second conductive type semiconductor body region are in contact with the trench gate electrode (1) through the trench gate dielectric layer (2); a first conductive type semiconductor source region (6) and a second conductive type semiconductor contact region (8) are arranged side by side on the top layer of the second conductive type semiconductor body region (7), wherein the first conductive type semiconductor source region (6) is contacted with the trench gate electrode (1) through the lateral trench gate dielectric layer (2); the method is characterized in that:

a first conductive type semiconductor buffer layer (13) is arranged between the substrate and the first conductive type semiconductor drift region (10); the lower surface of the first conduction type semiconductor buffer layer (13) coincides with the upper surface of the substrate, and the upper surface of the first conduction type semiconductor buffer layer (13) coincides with the lower surface of the first conduction type semiconductor drift region (10); a deep dielectric trench (4) is arranged in a first conductive type semiconductor drift region (10) between the trench gate structure and the first conductive type semiconductor drain region (9); the side face of the deep medium groove (4) is contacted with the second conductive type semiconductor contact region (8) and the second conductive type semiconductor body region (7); the first conductive type semiconductor drift region (10) is also provided with a semi-insulating polysilicon groove, the semi-insulating polysilicon groove comprises semi-insulating polysilicon (11) and insulating dielectric layers (12) arranged on the side surfaces and the bottom surface of the semi-insulating polysilicon (11), the semi-insulating polysilicon groove is connected with the first conductive type semiconductor drift region (10) along the transverse extension direction of the deep dielectric groove (4), the semi-insulating polysilicon groove is divided into a first part, a second part, a third part and a fourth part which are sequentially connected with each other by a groove gate structure and the deep dielectric groove (4), the groove gate structure is positioned on the first part, the deep dielectric groove (4) is positioned on the third part, wherein the upper surface of the semi-insulating polysilicon groove is flush with the upper surface of the first conductive type semiconductor drain region (9), and the lower surface of the semi-insulating polysilicon groove is flush with the lower surface of the first conductive type semiconductor drift region (10), the rear surface of the semi-insulating polycrystalline silicon groove is flush with the rear surface of the trench gate structure, and the rear surface of the semi-insulating polycrystalline silicon groove is the surface opposite to the surface connected with the semi-insulating polycrystalline silicon groove and the first conduction type semiconductor drift region (10); the semi-insulating polycrystalline silicon (11) is contacted with the trench gate electrode (1) through the trench gate dielectric layer (2), and the active electrode (3) is arranged on the second part of the semi-insulating polycrystalline silicon trench, the first conductive type semiconductor source region (6) and the upper surface of the second conductive type semiconductor contact region (8); and a drain electrode (5) is arranged on the fourth part of the semi-insulating polycrystalline silicon groove and the upper surface of the first conduction type semiconductor drain region (9).

2. A lateral MOS-type power semiconductor device according to claim 1, characterized in that: replacing the first conductive type semiconductor drain region (9) with a first conductive type semiconductor Buffer region and a second conductive type semiconductor collector region which are mutually independent, wherein the second conductive type semiconductor collector region is arranged on the upper surface of the first conductive type semiconductor Buffer region; a second conductive type semiconductor collector region on the upper surface of the first conductive type semiconductor Buffer region is contacted with the deep medium groove (4); and the second conductive type semiconductor collector region is contacted with the upper drain electrode (5) to form the IGBT device.

3. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the first conduction type semiconductor drift region (10) is also internally provided with a second conduction type semiconductor column region (17), the second conduction type semiconductor column region (17) is transversely connected with the first conduction type semiconductor drift region (10) along the deep dielectric trench (4) and is clamped between the first conduction type semiconductor drift regions (10) on two sides, and the second conduction type semiconductor column region (17) is flush with the upper surface and the lower surface of the first conduction type semiconductor drift region (10).

4. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the longitudinal depth of the deep dielectric trench (4) is equal to or greater than the junction depth of the first conductivity type semiconductor drift region (10).

5. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: and a buffer layer tightly attached to the wall surface of the deep dielectric trench (4) is arranged in the first conductive type semiconductor drift region (10) below the first conductive type semiconductor drain region (9) and/or in the first conductive type semiconductor drift region (10) below the deep dielectric trench (4) and/or in the first conductive type semiconductor drift region (10) below the second conductive type semiconductor body region (7).

6. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the longitudinal depth of the trench gate electrode (1) is less than the longitudinal depth of the deep dielectric trench (4).

7. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the deep dielectric trench (4) is internally provided with a first field plate (401) and a second field plate (402) which are same with the deep dielectric trench in extension direction and are symmetrically arranged, and the longitudinal extension depth of the first field plate (401) and the second field plate (402) is smaller than that of the deep dielectric trench (4).

8. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the semi-insulating polysilicon groove penetrates through the deep medium groove (4).

9. A lateral MOS-type power semiconductor device according to claim 1 or 2, characterized in that: the first conductive type semiconductor is an N-type semiconductor, the second conductive type semiconductor is a P-type semiconductor, or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.

10. A method for preparing a lateral MOS type power semiconductor device is characterized by comprising the following steps:

1) selecting a second conductive type semiconductor layer as a substrate;

2) forming a first conductive type semiconductor buffer layer on the second conductive type semiconductor layer;

3) forming a first conductive type semiconductor drift region on the first conductive type semiconductor buffer layer;

4) etching a groove in the first conduction type semiconductor drift region, forming an insulating medium layer on the inner wall of the groove, and filling semi-insulating polysilicon material in the groove to form a semi-insulating polysilicon groove which is connected with the first conduction type semiconductor drift region and has level upper and lower surfaces;

5) etching a deep groove along a direction vertical to a connecting interface of the first conductive type semiconductor drift region and the semi-insulating polycrystalline silicon groove, and filling a dielectric material in the deep groove to form a deep dielectric groove;

6) forming a trench gate structure in the first conductive type semiconductor drift region on one side of the deep dielectric trench;

7) forming a second conductive type semiconductor base region in the top layer of the first conductive type semiconductor drift region between the deep dielectric trench and the trench gate structure, wherein the junction depth of the second conductive type semiconductor base region is smaller than the longitudinal depth of the trench gate structure;

8) forming a first conductive type semiconductor source region and a second conductive type semiconductor contact region on the top layer of the second conductive type semiconductor base region;

9) forming a first conductive type semiconductor drain region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench, or forming a first conductive type semiconductor Buffer region and a second conductive type semiconductor collector region on the top layer of the first conductive type semiconductor drift region on the other side of the deep dielectric trench;

10) depositing a dielectric layer, photoetching and etching holes; and forming a source electrode metal and a drain electrode metal, and forming a substrate electrode metal on the back surface of the turnover device.

Images