CN113690299B - Trench gate VDMOS device and preparation method thereof - Google Patents
Trench gate VDMOS device and preparation method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The application relates to a trench gate VDMOS device and a preparation method thereof, wherein the device comprises: the semiconductor device comprises a drift region, a body region formed in the drift region and a source region formed on the body region, wherein the drift region and the source region are of a first conductivity type, and the body region is of a second conductivity type; the source region is provided with a first groove and a second groove, the bottoms of which extend to the drift region, and a gate oxide layer is formed on the inner wall of each groove; the first polysilicon body is formed in the first groove and the second groove and is electrically connected with each other, the second polysilicon body is formed in the first groove and is isolated from the first polysilicon body, and the depth of the first polysilicon body is larger than that of the second polysilicon body in the first groove; the source electrode leading-out structure is connected with the source region and the first polysilicon body; the grid electrode leading-out structure is connected with the second polysilicon body. According to the VDMOS device, the grooves are formed in the cell area so as to form the inner field plates in the drift area, so that the depletion of the drift area is enhanced, and the withstand voltage of the device is improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a trench gate VDMOS device and a preparation method thereof.
Background
In a MOS (Metal Oxide Semiconductor ) field effect transistor, a conduction channel is formed between a source and a drain, and the existence of the conduction channel makes the MOS field effect transistor have a certain on-resistance, so that the larger the on-resistance is, the larger the power consumption is, and therefore, the on-resistance needs to be reduced as much as possible. At present, a trench gate VDMOS (Vertical Double diffusion Metal Oxide Semiconductor, vertical double-diffused metal oxide semiconductor) field effect transistor is generally adopted, and a trench gate structure is formed, so that a conduction channel is changed from a transverse direction to a longitudinal direction, the cell density is greatly improved, and the conduction resistance is reduced. However, on the basis of the trench gate VDMOS device, if the on-resistance is to be further reduced, the doping concentration of the drift region needs to be increased, and the voltage-withstanding capability of the device is weakened by increasing the doping concentration, so that the on-resistance of the trench gate VDMOS device is further reduced with difficulty due to the limitation of the voltage-withstanding capability.
Disclosure of Invention
Based on this, it is necessary to provide a new VDMOS device and a method for manufacturing the same, aiming at the technical problem that the on-resistance of the current trench gate VDMOS device is difficult to be further reduced.
A trench gate VDMOS device comprising:
a drift region formed on the semiconductor substrate and having a first conductivity type;
the body region is formed on the upper surface layer of the drift region and is provided with a second conductivity type;
a source region formed on an upper surface layer of the body region and having a first conductivity type;
the first groove sequentially penetrates through the source region and the body region and extends into the drift region;
the second groove is arranged at intervals with the first groove, sequentially penetrates through the source region and the body region and extends into the drift region;
the first polysilicon body is formed in the first groove and the second groove and is electrically connected with each other, and a gate oxide layer is formed between the first polysilicon body and the inner wall of the first groove and between the first polysilicon body and the inner wall of the second groove;
the second polysilicon body is formed in the first groove and is isolated from the first polysilicon body, a gate oxide layer is formed between the second polysilicon body and the inner wall of the first groove, and the distance between the bottom of the first polysilicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first groove in the first groove;
the source electrode leading-out structure is connected with the source region and the first polysilicon body; and
and the grid electrode leading-out structure is connected with the second polysilicon body.
In the VDMOS device, a plurality of trenches are formed in the cell region, wherein the first trench is filled with the second polysilicon body, and the second polysilicon body is connected with the gate to form a trench gate structure, and a vertical conduction channel is formed through the trench gate structure. Meanwhile, first polysilicon bodies which are electrically connected with each other are filled in the bottom of the first groove and the second groove, and the first polysilicon bodies are connected with the source electrode, which is equivalent to forming a plurality of inner field plates connected with the source electrode in a cellular region, and the electric field distribution of the drift region can be regulated through the inner field plates, so that the depletion of the drift region is enhanced, and the breakdown voltage of the VDMOS device is improved. Therefore, under the condition of having the same breakdown voltage, the drift region of the trench gate VDMOS can increase the doping concentration, thereby reducing the on-resistance. That is, the trench gate VDMOS device in the present application has a lower on-resistance with an equivalent breakdown voltage.
In one embodiment, the first grooves and the second grooves are arranged in alternating rows.
In one embodiment, the first trenches and the second trenches are elongated, the gate lead-out structures are disposed at ends of the first trenches on the same side and connected to the second polysilicon body in the first trenches, the gate lead-out structures are disposed on the second trenches and connected to the first polysilicon body in the second trenches, and the gate lead-out structures and the source lead-out structures are staggered from each other.
In one embodiment, the first trench and the second trench are mutually communicated through a communication trench, the first polysilicon body is further formed in the communication trench, and a gate oxide layer is formed between the first polysilicon body and the inner wall of the communication trench.
In one embodiment, the source electrode lead-out structure is arranged on the first polysilicon in the second groove and is connected with the first polysilicon body in the second groove, and one end of the source electrode lead-out structure extends along the length direction of the second groove and passes through the communication groove.
In one embodiment, the communication trench sequentially penetrates the source region and the body region and extends into the drift region.
In one embodiment, the bottom of the second trench is flush with the bottom of the first trench.
In one embodiment, the method further comprises:
an interlayer dielectric layer formed on top surfaces of the source region, the first trench and the second trench;
the source electrode lead-out structure penetrates through the interlayer dielectric layer and the source region and is connected with the source and the first polysilicon body in the second groove;
and the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second polysilicon body in the first groove.
A preparation method of a trench gate VDMOS device comprises the following steps:
providing a semiconductor substrate and forming a first conductivity type drift region on the semiconductor substrate;
a first groove and a second groove are formed in the drift region;
forming a gate oxide layer on the inner walls of the first groove and the second groove, forming a first polysilicon body which is electrically connected with each other in the first groove and the second groove, and forming a second polysilicon body which is isolated from the first polysilicon body in the first groove, wherein the distance between the bottom of the first polysilicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first groove in the first groove;
doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the first groove side wall and the second groove side wall, wherein the depth of the body region is smaller than that of the first groove and the second groove; doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the first groove side wall and the second groove side wall; and
and forming a source electrode lead-out structure connected with the source region and the first polysilicon body, and forming a grid electrode lead-out structure connected with the second polysilicon body.
According to the method for manufacturing the trench gate VDMOS device, the plurality of trenches are formed in the cell area, wherein the second polysilicon body is formed in the first trench and connected with the gate, and the formation of the plurality of trench gates in the cell area is equivalent to the formation of the second polysilicon body and the gate. And forming a first polysilicon body at the bottom of the first groove and in the second groove, wherein the first polysilicon body is connected with the source electrode, which is equivalent to forming a plurality of inner field plates in a cell region, so that the depletion of the drift region is enhanced, and the breakdown voltage is improved. Therefore, under the condition of having the same breakdown voltage, the trench gate VDMOS device prepared by the method can improve the doping concentration of the drift region of the trench gate VDMOS device, so that the on-resistance of the device is reduced.
In one embodiment, a first groove and a second groove are formed in the drift region, and a communication groove which is communicated with the first groove and the second groove is formed in the drift region; forming a gate oxide layer on the inner walls of the communication trenches while forming a gate oxide layer on the inner walls of the first trenches and the second trenches; and forming a first polysilicon body in the communication groove at the same time of forming the first polysilicon body which is electrically connected with each other in the first groove and the second groove.
Drawings
FIG. 1 is a cross-sectional side view of a cell region of a trench gate VDMOS device in accordance with one embodiment of the present application;
fig. 2 is a side cross-sectional view of a trench-gate VDMOS device at a communication trench in an embodiment of the present application;
fig. 3 is a side cross-sectional view of a trench gate VDMOS device at a gate lead-out structure in an embodiment of the present application;
fig. 4 is a cross-sectional view of a trench-gate VDMOS device according to an embodiment of the present application taken along section line A-A' in fig. 1;
FIG. 5a is a schematic view illustrating a structure of a first trench according to an embodiment of the present application;
FIG. 5b is a schematic view of a structure in a first trench according to another embodiment of the present application;
fig. 6 is a flowchart illustrating steps of a method for manufacturing a trench-gate VDMOS device according to an embodiment of the present application;
fig. 7a to 7h are cross-sectional views of structures corresponding to relevant steps in a method for manufacturing a trench gate VDMOS device according to an embodiment of the present application.
Description of the reference numerals
A 100 drift region; 110 body regions; a 111 source region; 112 heavily doped regions; 120 a first trench; 130 a second trench; 140 gate oxide layer; 150 a first polysilicon body; 160 a second polysilicon body; 170 isolation structures; 180 communication grooves; 200 dielectric layers; 310 source extraction structures; 320 gate lead-out structure.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Fig. 4 is a cross-sectional view of the trench gate VDMOS device taken along section line AA 'in fig. 1, and fig. 1 is a side cross-sectional view of the trench gate VDMOS device taken along section line BB' in fig. 4. The trench gate VDMOS device includes a drift region 100, where the drift region 100 is formed on a semiconductor substrate, specifically may be formed on an epitaxial layer formed by epitaxial growth of the semiconductor substrate, a body region 110 is formed on an upper surface layer of the drift region 100, an active region 111 is formed on an upper surface layer of the body region 110, and a plurality of first trenches 120 and second trenches 130 penetrating the active region 111 and the body region 110 and extending into the drift region 100 are formed in the source region 111, i.e., bottom ends of the first trenches 120 and the second trenches 130 are located in the drift region 100. The first polysilicon body 150 is formed in each of the first trench 120 and the second trench 130, and the first polysilicon body 150 in the first trench 120 and the first polysilicon body 150 in the second trench 130 are electrically connected and integrally formed with each other, and a gate oxide layer 140 is formed between the first polysilicon body 150 and the inner wall of the first trench 120 and between the first polysilicon body 150 and the inner wall of the second trench 130. The first trench 120 further has a second polysilicon body 160 formed therein, the second polysilicon body 160 is isolated from the first polysilicon body 150, and a gate oxide layer 140 is also formed between the second polysilicon body 160 and the inner wall of the second trench 120, and in the first trench 120, the depth of the first polysilicon body 150 is greater than the depth of the second polysilicon body 160, i.e., the distance from the first polysilicon body 150 to the bottom of the first trench 120 is smaller than the distance from the second polysilicon body 160 to the bottom of the first trench 120. The trench gate VDMOS device further includes a source extraction structure 310 and a gate extraction structure 320, where the source extraction structure 310 and the gate extraction structure 320 may be metal pillars, specifically tungsten metal, and the source extraction structure 310 is connected to the source region 111 and the first polysilicon body 150, and the gate extraction structure 320 is connected to the second polysilicon body 160. The drift region 100 and the source region 111 have a first conductivity type and the body region 110 has a second conductivity type. Wherein the first conductivity type is N type, and the second conductivity type is P type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type. It will be appreciated that the front side of the trench gate VDMOS device should also have a source metal layer and a gate metal layer isolated from each other, the source lead-out structures 310 are all connected to the source metal layer, the gate lead-out structures 320 are all connected to the gate metal layer, and a drain metal layer is also formed on the back side of the trench gate VDMOS device.
In the trench gate VDMOS device, the top source region 111 is connected to the source metal layer through the source extraction structure 310, the bottom drift region 100 is connected to the drain metal layer as a drain region, the body region 110 in the middle is used as a channel region, the first trench 120 penetrates through the body region 110 and extends into the drift region 100, the first trench 120 has the gate oxide layer 140 and the second polysilicon body 160 therein, and the second polysilicon body 160 is connected to the gate metal layer through the gate extraction structure 320, i.e., the first trench 120 and the gate oxide layer 140 and the second polysilicon body 160 therein form a trench gate structure, thereby forming the trench gate VDMOS device. By this trench gate structure, a longitudinal conductive channel may be formed within the body region 110. Meanwhile, the trench gate VDMOS device further has a second trench 130, the second trench 130 penetrates through the source region 111 and the body region 110, that is, the second trench 130 is formed in a cell region of the trench gate VDMOS device, a first polysilicon body 150 is formed in the first trench 120 and the second trench 130, the first polysilicon body 150 is connected with a source metal layer through a source lead-out structure, which is equivalent to forming a plurality of inner field plates in the drift region 100, and the inner field plates connected with the source metal layer can regulate the electric field distribution in the drift region 100, so that the depletion of the drift region 100 is enhanced. Meanwhile, in the first trench 120, the first polysilicon body 150 connected to the source metal layer is closer to the bottom of the trench than the second polysilicon body 160 connected to the gate, so that parasitic capacitance between the gate and the drain can be reduced, and the device has better characteristics.
In one embodiment, as shown in fig. 1, the first trenches 120 and the second trenches 130 are alternately arranged in parallel, and the space between the trenches is smaller, which is more beneficial to enhance the depletion of the drift region. In an embodiment, as shown in fig. 4, the first trench 120 and the second trench 130 are elongated, the first trench 120 and the second trench are arranged in parallel along the width direction (Y direction), and at least one end of the first trench 120 extends along the length direction (X direction) and spans the source region 111 and extends beyond the region covered by the source region 111. In the trench gate VDMOS device, the area covered by the source region 111 is a cell region of the trench gate VDMOS device, and the area uncovered by the source region 111 is a peripheral region, in this embodiment, a part of the first trench 120 is located in the cell region, and the other part is located in the peripheral region, where, as shown in fig. 2 in conjunction with fig. 2, fig. 2 is a side sectional view of the trench gate VDMOS device along the CC' section line in fig. 4, and the second polysilicon body 160 located in the first trench 120 in the peripheral region is connected to the gate extraction structure 320 to extract the gate. Because the source extraction structure 310 is formed in the cellular region, and the gate extraction structure 320 is arranged in the peripheral region, the source extraction structure 310 and the gate extraction structure 320 can be staggered, which is beneficial to forming a source metal layer and a gate metal layer which are mutually isolated in the later period.
In an embodiment, the first trench 120 and the second trench 130 are mutually communicated, specifically, a communication trench 180 is further formed between the first trench 120 and the second trench 130, a first polysilicon body 150 is also formed in the communication trench 180, a gate oxide layer is also formed between the first polysilicon body in the communication trench and the inner wall of the trench, and the first polysilicon bodies 150 in the first trench 120, the second trench 130 and the communication trench 180 are mutually electrically connected and integrally formed. In this embodiment, as shown in fig. 3 and fig. 4, fig. 3 is a side sectional view of the trench gate VDMOS device along the DD' section line in fig. 4, and the communication trench 180 is specifically formed in the cellular region, that is, the communication trench sequentially penetrates the source region 111, the body region 110, and extends into the drift region 100. In this embodiment, the communication trench 180 is disposed in the cellular region, and the first polysilicon body and the gate oxide layer of the communication trench also correspond to an inner field plate, so as to further enhance the depletion of the drift region. The number of the communication grooves between the adjacent grooves is not limited, and may be 1 or more, and the positions of the communication grooves may be connected to two ends of the first groove and the second groove, or may be connected to the middle of the first groove and the second groove, so long as the communication between the adjacent grooves can be achieved.
Further, with continued reference to fig. 4, the source extraction structure 310 passes through the junction of the communication trench 180 and the second trench 130, that is, the source extraction structure 310 extends along the length direction of the second trench and passes through the connection portion of the second trench 130 and the communication trench 180, so that the voltage on the source extraction structure 310 is advantageously transferred to the first polysilicon body 150 in the first trench 120, so that the voltage on the first polysilicon body 150 in the first trench 120 and the second trench 130 is uniformly distributed, and thus the electric field modulation on the drift region is advantageously performed. Meanwhile, since the gate lead-out structure 320 needs to be connected with the gate metal layer, the source lead-out structure 310 needs to be connected with the source metal layer, and the communication groove 180 and the gate lead-out structure 320 are staggered, so that the source metal layer and the gate metal layer which are isolated from each other are formed.
In an embodiment, the bottom of the first trench 120 is flush with the bottom of the second trench 130, i.e. the depths of the first trench 120 and the second trench 130 are the same, so that on one hand, the etching process steps can be simplified, and on the other hand, the first trench and the second trench can be formed by one etching step, which is also beneficial to enhancing the modulation effect on the electric field of the drift region 100. Further, the dimensions of the first trench 120 and the second trench 130 may be identical. In an embodiment, the plurality of first trenches 120 and the plurality of second trenches 130 are alternately arranged, the spacing between adjacent first trenches 120 and second trenches 130 are equal, and the first trenches 120 and the second trenches 130 are uniformly distributed, so that the inner field plates in the drift region 100 are uniformly distributed, which is also beneficial to enhancing the modulation of the electric field of the drift region 100.
In an embodiment, an interlayer dielectric layer 200 is further formed on the source region 111, the first trench 120, and the second trench 130, the dielectric layer 200 may be specifically silicon oxide, the source extraction structure 310 is formed directly above the second trench 130, penetrates through the interlayer dielectric layer 200 and the source region 111, and is connected to the source region 111 and the first polysilicon body 150 in the second trench 130, and the gate extraction structure 320 is formed directly above the first trench 120, penetrates through the interlayer dielectric layer 200, and is connected to the second polysilicon body 160 in the first trench 120.
In an embodiment, as shown in fig. 1, a heavily doped region 112 is further formed in the body region 110, the heavily doped region 112 has a second conductivity type, the doping concentration of the heavily doped region 112 is higher than that of the body region 110, the heavily doped region 112 is specifically located below the source region 111 and is spaced from the first trench 120, the second trench 130 penetrates the source region 111, the heavily doped region 112 and the body region 110 in sequence and extends into the drift region 100, the source extraction structure 310 penetrates the source region 111 and extends into the heavily doped region 112, the source extraction structure 310 is connected with the source region 111 and the first polysilicon body 150, and the bottom of the source extraction structure is surrounded by the heavily doped region 112, thereby reducing the contact resistance between the source extraction structure 310 and the body region 110.
Wherein the distribution of the first polysilicon body 150 and the second polysilicon body 160 within the first trench 120 has a plurality of designs. In an embodiment, as shown in fig. 1, in the first trench 120, the first polysilicon body 150 is distributed at the bottom of the first trench 120, the second polysilicon body 160 is distributed at the top of the first trench 120, and the first polysilicon body 150 and the second polysilicon body 160 are isolated by an isolation structure 170, wherein a gate oxide layer is formed between the first polysilicon body 150 and the inner wall of the first trench 120 and between the second polysilicon body 160 and the inner wall of the first trench 120, and in particular, the isolation structure 170 is silicon oxide. In this embodiment, the first polysilicon body 150 at the bottom of the first trench can regulate the electric field of the drift region, enhance the depletion of the drift region, weaken the parasitic capacitance between the gate and the drain, and improve the device performance. Further, the first polysilicon body 150 is also formed in the communication trench 180, the first polysilicon bodies in the trenches are electrically connected to each other, a gate oxide layer is also formed between the first polysilicon body 150 and the inner wall of the communication trench 180, and an isolation structure is also filled above the first polysilicon body in the communication trench 180, specifically, the isolation structure in the communication trench 180 is connected to the isolation structure in the first trench 120, and the communication trench 180 is filled to isolate the first polysilicon body 150 from the second polysilicon body 160. In one embodiment, the top surface of the first polysilicon body 150 and the bottom surface of the second polysilicon body 160 are approximately planar surfaces within the first trench 120. In another embodiment, as shown in fig. 5a, in the first trench 120, the middle of the top surface of the first polysilicon body 150 is protruded outwards, and the middle of the bottom surface of the second polysilicon body 160 is recessed inwards to fit the protrusion of the first polysilicon body 150.
In one embodiment, as shown in fig. 5b, in the first trench 120, the first polysilicon body 150 extends from the top of the first trench 120 to the bottom of the first trench 120, a gate oxide layer 140 is formed between the first polysilicon body 150 and the inner wall of the first trench 120, the second polysilicon body 160 is formed in the gate oxide layer 140 at two sides of the first polysilicon body 150, the first polysilicon body 150 is isolated from the second polysilicon body 160 by the gate oxide layer 140, and the depth of the first polysilicon body 150 extending towards the bottom of the trench is greater than the depth of the second polysilicon body 160 extending towards the bottom of the trench. In the present embodiment, the second polysilicon body 160 is provided in the gate oxide layer 140, and the thickness of the gate oxide layer 140 can be increased, thereby enhancing the device withstand voltage.
The application also relates to a preparation method of the trench gate VDMOS device, as shown in FIG. 6, comprising the following steps:
step S610: a semiconductor substrate is provided and a first conductivity type drift region is formed on the semiconductor substrate.
As shown in fig. 7a, the drift region 100 is formed by doping the semiconductor substrate with a first conductivity type, which may specifically be doping the epitaxial layer on the semiconductor substrate to form the drift region 100 on the epitaxial layer.
Step S620: and a first groove and a second groove are formed in the drift region.
As shown in fig. 7b, a plurality of first trenches 120 and second trenches 130 are opened on the drift region 100 by photolithography and etching processes. In a specific process, the first trench and the second trench may be formed by a single photolithography and etching process. The dimensions, positions and spacing relationships of the first trench 120 and the second trench 130 are described above, and will not be described herein.
In an embodiment, the first trench 120 and the second trench 130 are formed on the drift region, and a communication trench 180 is formed on the drift region to communicate the first trench 120 and the second trench 130. In a specific process, the first trench, the second trench and the communication trench may be formed by a single photolithography and etching process.
Step S630: forming a gate oxide layer on the inner walls of the first groove and the second groove, forming a first polysilicon body which is electrically connected with each other in the first groove and the second groove, and forming a second polysilicon body which is isolated from the first polysilicon body in the first groove, wherein in the first groove, the distance between the bottom of the first polysilicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first groove.
In an embodiment, when the communication trench 180 is formed, a gate oxide layer may be simultaneously formed at the inner walls of the first trench 120, the second trench 130, and the communication trench 180, and then the electrically connected first polysilicon body 150 may be integrally formed in the first trench 120, the second trench 130, and the communication trench 180 at the same time.
Since the structures of the first and second polysilicon bodies 150 and 160 in the first trench 120 have various forms, the steps of forming the first and second polysilicon bodies 150 and 160 in the first trench 120 have various embodiments, accordingly. In a specific embodiment, step S630 may include the following steps:
step S631: and forming a gate oxide layer on the inner walls of the first groove and the second groove.
As shown in fig. 7c, a gate oxide layer 140 is formed on the inner walls of the first trench 120 and the second trench 130, and the gate oxide layer 140 may be formed by thermal oxidation. Specifically, the first trench 120 and the second trench 130 are communicated with each other through a communication trench, and a gate oxide layer is also formed on the inner wall of the communication trench. In a specific process, the gate oxide layer may be formed on the inner walls of all the trenches by a single thermal oxidation process.
Step S632: and filling the first grooves and the second grooves with first polysilicon bodies which are electrically connected with each other.
As shown in fig. 7d, the first polysilicon body 150 is filled into the first trench 120 and the second trench 130, and the first polysilicon body 150 in the first trench 120 and the second trench 130 are electrically connected to each other and integrally formed. Specifically, the first polysilicon body may be formed by a deposition process, and the first polysilicon body 150 fills the first trench and the second trench. It will be appreciated that the communication trench is also filled with the first polysilicon body. In a specific process, the first polysilicon body may be filled in all the trenches by a single deposition process.
Step S633: and etching the first polysilicon body and the gate oxide layer which are positioned at the top of the first groove, and reserving the first polysilicon body and the gate oxide layer at the bottom of the first groove.
As shown in fig. 7e, the first polysilicon body and the gate oxide layer on the top of the first trench 120 are etched, leaving the first polysilicon body 150 on the bottom of the first trench 120 and the gate oxide layer 140 between the first polysilicon body 150 and the first trench sidewall.
Step S634: and forming an isolation structure in the first groove, wherein the isolation structure covers the first polysilicon body at the bottom of the groove and does not fill the first groove.
As shown in fig. 7f, an isolation structure 170, which may be specifically silicon oxide, is deposited in the first trench 120 by a deposition process, and the isolation structure 170 covers the first polysilicon body 150 and does not fill the first trench 120.
Step S635: and forming a gate oxide layer on the side wall of the first groove above the isolation structure and filling a second polysilicon body into the first groove.
As shown in fig. 7g, a gate oxide layer is formed on the sidewall of the first trench 120 above the isolation structure 170 and the second polysilicon body 160 is filled in the first trench 120, the second polysilicon body 160 is isolated from the inner wall of the first trench 120 by the gate oxide layer 140, and the second polysilicon body 160 is isolated from the first polysilicon body 150 by the isolation structure 170. It will be appreciated that, in order to isolate the first polysilicon body 150 and the second polysilicon body 160, in the step S633, the first polysilicon body and the gate oxide layer at the top of the communication trench are also etched away, and in the step S634, an isolation structure is also deposited in the communication trench, the isolation structure in the communication trench fills the communication trench and is connected with the isolation structure in the first trench 120, and the second polysilicon body 160 at the top of the first trench 120 is isolated from the first polysilicon body 150 at the bottom of the first trench 120 and the first polysilicon body 150 in the second trench 130 by the bottom isolation structure and the isolation structures at both sides.
Step S640: doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the first groove side wall and the second groove side wall, wherein the depth of the body region is lower than that of the first groove and the second groove; and doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the first groove side wall and the second groove side wall.
As shown in fig. 7h, the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewalls of the first trench 120 and the second trench 130, the depth of the body region 110 being smaller than the depth of the first trench 120 and the depth of the second trench 130, i.e. the bottoms of the first trench 120 and the second trench 130 remain within the drift region 100. The upper surface layer of the body region 110 is doped to form a first conductivity type source region 111 contacting the sidewalls of the first trench 120 and the sidewalls of the second trench 130. An interlayer dielectric layer 200 is formed on the source region 111, the first trench 120, and the second trench 130.
Step S650: and forming a source electrode lead-out structure connected with the source region and the first polysilicon body, and forming a grid electrode lead-out structure connected with the second polysilicon body.
As shown in fig. 7h, a source extraction structure 310 is formed in a region of the interlayer dielectric layer 200 opposite to the second trench 130, and a gate conductive region is formed in a region opposite to the first trench 120, wherein the source extraction structure 310 penetrates through the interlayer dielectric layer 200 and the source region 111 to be connected with the source region 111 and the first polysilicon body 150 in the second trench 130, and the gate extraction structure penetrates through the interlayer dielectric layer 200 to be connected with the second polysilicon body 160 in the first trench 120. Specifically, the positional relationship between the source extraction structure and the gate extraction structure is referred to the above description, and will not be described herein. Specifically, the process of forming the lead-out structure is to firstly open a contact hole and then fill conductive materials into the contact hole to form the lead-out structure. In an embodiment, in the process of forming the source lead-out structure 310, a source contact hole penetrating the source region 111 and extending into the body region 110 is first opened, then a second conductivity type heavy doping is performed to the body region 110 through the source contact hole, a heavy doped region 112 is formed in the body region 110, the doping concentration of the heavy doped region 112 is greater than that of the body region, and finally a conductive material is filled into the source contact hole to form the source lead-out structure 310, at this time, the bottom of the source lead-out structure 310 is surrounded by the heavy doped region 112.
According to the preparation method of the trench gate VDMOS device, the plurality of trenches are formed in the cell region, wherein the gate oxide layer and the second polysilicon body are formed in the first trench, the second polysilicon body is connected with the gate to form the trench gate structure, meanwhile, the first polysilicon body is formed in the first trench and the second trench, and the first polysilicon body is connected with the source, which is equivalent to forming a plurality of inner field plates in the cell region, so that the electric field of the drift region can be regulated, and the withstand voltage of the device is enhanced. Therefore, under the condition of the same breakdown voltage, the drift region of the trench gate VDMOS device obtained by the preparation method can have higher doping concentration and lower on-resistance of the device. Meanwhile, according to the preparation method, the first groove, the second groove and the communication groove can be formed through one-time photoetching and etching processes, compared with the process that the traditional VDMOS device is only provided with the first groove and the groove gate is introduced, the photoetching times are not increased, and a mask is not required to be added when different types of grooves are formed; and the filling structures in the second groove and the communicating groove are synchronously formed in the process steps of the groove gate structure, and the second groove and the communicating groove are not required to be filled by an additional process, so that the VDMOS device prepared by the preparation method has lower on-resistance, does not need to be additionally provided with an additional process step, and is compatible with the existing groove gate preparation process.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A trench gate VDMOS device comprising:
a drift region formed on the semiconductor substrate and having a first conductivity type;
the body region is formed on the upper surface layer of the drift region and is provided with a second conductivity type;
a source region formed on an upper surface layer of the body region and having a first conductivity type;
the first groove sequentially penetrates through the source region and the body region and extends into the drift region;
the second groove is arranged at intervals with the first groove, sequentially penetrates through the source region and the body region and extends into the drift region;
the first polysilicon body is formed in the first groove and the second groove and is electrically connected with each other, and a gate oxide layer is formed between the first polysilicon body and the inner wall of the first groove and between the first polysilicon body and the inner wall of the second groove;
the second polysilicon body is formed in the first groove and is isolated from the first polysilicon body, a gate oxide layer is formed between the second polysilicon body and the inner wall of the first groove, and the distance between the bottom of the first polysilicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first groove in the first groove;
the source electrode leading-out structure is connected with the source region and the first polysilicon body; and
the grid electrode leading-out structure is connected with the second polysilicon body;
the first grooves and the second grooves are communicated with each other through the communication grooves, the first polysilicon body is further formed in the communication grooves, and a gate oxide layer is formed between the first polysilicon body and the inner wall of the communication grooves.
2. The VDMOS device of claim 1, wherein the first trenches and the second trenches are alternately juxtaposed.
3. The VDMOS device of claim 2, wherein the first trenches and the second trenches are elongated, the gate extraction structures are disposed at ends of the first trenches on the same side and connected to the second polysilicon bodies in the first trenches, the gate extraction structures are disposed on the second trenches and connected to the first polysilicon bodies in the second trenches, and the gate extraction structures and the source extraction structures are offset from each other.
4. The VDMOS device of claim 1, wherein a heavily doped region is further formed in the body region, the heavily doped region having a second conductivity type and a higher doping concentration than the body region, the heavily doped region being located specifically below the source region and spaced apart from the first trench, the second trench penetrating the source region, the heavily doped region and the body region in sequence and extending into the drift region, the source extraction structure penetrating the source region and extending into the heavily doped region, the source extraction structure being connected to the source region and the first polysilicon body and surrounded at its bottom by the heavily doped region.
5. The VDMOS device of claim 1, wherein the source extraction structure is disposed on the first polysilicon in the second trench and is connected to the first polysilicon body in the second trench, and wherein one end of the source extraction structure extends along a length direction of the second trench and passes through the communication trench.
6. The VDMOS device of claim 1, wherein the communication trench extends through the source region and the body region sequentially and into the drift region.
7. The VDMOS device of claim 1, wherein a bottom of the second trench and a bottom of the first trench are flush.
8. The VDMOS device of claim 1, further comprising:
an interlayer dielectric layer formed on top surfaces of the source region, the first trench and the second trench;
the source electrode lead-out structure penetrates through the interlayer dielectric layer and the source region and is connected with the source and the first polysilicon body in the second groove;
and the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second polysilicon body in the first groove.
9. The preparation method of the trench gate VDMOS device is characterized by comprising the following steps:
providing a semiconductor substrate and forming a first conductivity type drift region on the semiconductor substrate;
a first groove and a second groove are formed in the drift region;
forming a gate oxide layer on the inner walls of the first groove and the second groove, forming a first polysilicon body which is electrically connected with each other in the first groove and the second groove, and forming a second polysilicon body which is isolated from the first polysilicon body in the first groove, wherein the distance between the bottom of the first polysilicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first groove in the first groove;
doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the first groove side wall and the second groove side wall, wherein the depth of the body region is smaller than that of the first groove and the second groove; doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the first groove side wall and the second groove side wall; and
forming a source electrode lead-out structure connected with the source region and the first polysilicon body, and forming a grid electrode lead-out structure connected with the second polysilicon body;
a first groove and a second groove are formed in the drift region, and meanwhile, a communication groove which is communicated with the first groove and the second groove is formed in the drift region; forming a gate oxide layer on the inner walls of the communication trenches while forming a gate oxide layer on the inner walls of the first trenches and the second trenches; and forming a first polysilicon body in the communication groove at the same time of forming the first polysilicon body which is electrically connected with each other in the first groove and the second groove.
10. The method of manufacturing a VDMOS device of claim 9, wherein forming a gate oxide layer on inner walls of the first trench and the second trench, and forming a first polysilicon body in the first trench and the second trench that is electrically connected to each other, and forming a second polysilicon body in the first trench that is isolated from the first polysilicon body, comprises:
forming a gate oxide layer on the inner walls of the first groove and the second groove;
filling first polysilicon bodies which are electrically connected with each other into the first groove and the second groove;
etching the first polysilicon body and the gate oxide layer which are positioned at the top of the first groove, and reserving the first polysilicon body and the gate oxide layer at the bottom of the first groove;
forming an isolation structure in the first groove, wherein the isolation structure covers the first polysilicon body at the bottom of the groove and does not fill the first groove;
and forming a gate oxide layer on the side wall of the first groove above the isolation structure and filling a second polysilicon body into the first groove.
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| PCT/CN2020/139875 WO2021232792A1 (en) | 2020-05-18 | 2020-12-28 | Trench gate vdmos device and manufacturing method therefor |
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