CN109166924A - A kind of lateral MOS type power semiconductor and preparation method thereof - Google Patents
A kind of lateral MOS type power semiconductor and preparation method thereof Download PDFInfo
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- CN109166924A CN109166924A CN201810991168.1A CN201810991168A CN109166924A CN 109166924 A CN109166924 A CN 109166924A CN 201810991168 A CN201810991168 A CN 201810991168A CN 109166924 A CN109166924 A CN 109166924A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 261
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 70
- 229920005591 polysilicon Polymers 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
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- 238000005530 etching Methods 0.000 claims description 7
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- 230000015572 biosynthetic process Effects 0.000 description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
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- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 4
- 239000010432 diamond Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
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- 230000003647 oxidation Effects 0.000 description 4
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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Abstract
The present invention provides a kind of lateral MOS type device and preparation method thereof, belongs to semiconductor power device technology field.The present invention in the drift region of traditional lateral MOS type device by introducing deep medium groove, semi-insulating polysilicon column and buffer layer.The introducing of deep medium groove effectively increases the length of drift region so that device forms U-shaped conductive channel under same device length in situation；Semi-insulating polysilicon column replaces the doping concentration for connecting and forming three-dimensional resistive field plate structure to improve drift region in drift region introducing multidimensional depletion action when device is blocked with drift region along deep medium channel lateral extending direction, and limit the drift sector width of deep trench two sides by dopant dose, the field distribution of drift region is improved, also reduces ratio conducting resistance/conduction voltage drop of device while improving device electric breakdown strength.The introducing of buffer layer can be improved the charge balancing properties of three-dimensional medium super-junction structure, to further increase the Performance And Reliability of device.
Description
Technical field
The invention belongs to power semiconductor device technology fields, and in particular to a kind of lateral MOS type power semiconductor
And preparation method thereof.
Background technique
With the fast development of electronic technology, urgent demand is proposed for the power MOS type device that high pressure can integrate.
Cross bimoment (LDMOS) and lateral insulated gate bipolar transistor (LIGBT)
Device is good by its thermal stability, and high gain, noise is low, and the high advantage with CMOS technology compatibility is widely used in big rule
In vlsi die, becomes power integrated circuit and develop essential a part.For traditional LDMOS (as shown in Figure 1)
Drift region length must just be increased if to increase the voltage endurance capability of device with LIGBT device to improve device voltage endurance capability,
However conducting resistance/conduction voltage drop of device can in this way increased, power consumption increases, and chip area increases, increased costs.Although
Industry in drift region by introducing the effect of Double RESURF (RESURF), but the promotion of device performance extremely has
Limit.
Summary of the invention
In view of the defects existing in the prior art, the present invention provides a kind of lateral MOS type device and preparation method thereof, by
Deep medium groove is introduced in the drift region of traditional lateral MOS type device (LDMOS device/LIGBT device) makes device formation type
Conducting channel；Semi-insulating polysilicon (SIPOS) column is introduced simultaneously, SIPOS column and drift region are along deep medium channel lateral extension side
Connect to alternating as three-dimensional resistive field plate structure, further introduces and drift about with respect to the other side of SIPOS column in drift region
Doping type opposite semiconductor regions in area's are to provide three-dimensional charge compensation effect, so that introducing when device is blocked to drift region
Multidimensional depletion action improves the doping concentration of drift region, and makes the drift sector width of deep trench two sides not by the limit of dopant dose
System, improves the field distribution of drift region, reduces while improving breakdown voltage than conducting resistance/conduction voltage drop；Further lead to
Cross and introduce buffer layer and improve the charge balancing properties of three-dimensional medium super-junction structure, thus further increase device performance and can
By property.
To achieve the goals above, the technical scheme is that
The present invention provides a kind of MOS type power semiconductor, specifically a kind of lateral diffusion metal oxide semiconductor
Device (LDMOS device):
A kind of LDMOS device, structure cell include substrate, the underlayer electrode 16 and substrate face that substrate back is arranged in
The first conductive type semiconductor drift region 10；First conductive type semiconductor drift region, 10 top layer side is provided with the first conduction
Type semiconductor drain region 9；First conductive type semiconductor drift region, the 10 top layer other side is provided with MOS structure, the MOS structure
Including the second conductive type semiconductor body area 7, the first conductive type semiconductor source area 6, the contact of the second conductive type semiconductor
Area 8, source electrode 3 and trench gate structure；Trench gate structure include trench gate electrode 1 and setting in 1 side of trench gate electrode and
The groove gate dielectric layer 2 of bottom surface；The setting of second conductive type semiconductor body area 7 is partly led in trench gate structure and the first conduction type
It is arranged between body drain area 9 and close to trench gate structure；Second conductive type semiconductor body area 7 and the first conduction type below
Drift semiconductor area 10 is in contact by trench dielectric layer 2 with trench gate electrode 1；First conductive type semiconductor source area, 6 He
Second conductive type semiconductor contact zone 8 is disposed side by side on the top layer in the second conductive type semiconductor body area 7, wherein first is conductive
Type semiconductor source area 6 is in contact by the trench dielectric layer 2 of side with trench gate electrode 1；It is characterized by:
The first conductive type semiconductor buffer layer 13 is provided between substrate and the first conductive type semiconductor drift region 10；
The lower surface of first conductive type semiconductor buffer layer 13 is overlapped with the upper surface of substrate, the first conductive type semiconductor buffer layer
13 upper surface is overlapped with the lower surface of the first conductive type semiconductor drift region 10；The trench gate structure and the first conductive-type
Deep medium groove 4 is provided in the first conductive type semiconductor drift region 10 between type semiconductor drain region 9；Deep medium groove 4
Side be in contact with the second conductive type semiconductor contact zone 8 and the second conductive type semiconductor body area 7；Described first is conductive
Semi-insulating polysilicon slot is additionally provided in type semiconductor drift region 10, the semi-insulating polysilicon slot includes semi-insulating polysilicon
11 and the insulating medium layer 12 of 11 side of semi-insulating polysilicon and bottom surface is set, the semi-insulating polysilicon slot is along deep medium ditch
4 transverse extension direction of slot replaces with the first conductive type semiconductor drift region 10 to connect, wherein the upper table of semi-insulating polysilicon slot
Face is flushed with 9 upper surface of the first conductive type semiconductor drain region, lower surface and the first conductive type semiconductor drift region 10
Lower surface is concordant；Semi-insulating polysilicon 11 is contacted with trench gate electrode 1 by groove gate dielectric layer 2, semi-insulating polysilicon 11, exhausted
Edge dielectric layer 12, the first conductive type semiconductor source area 6, the second conductive type semiconductor contact zone 8 upper surface be provided with
Source electrode 3；Source electrode 3 and trench gate electrode 1 are isolated by dielectric layer；Semi-insulating polysilicon 11 and the first conduction type are partly led
The upper surface in body drain area 9 is provided with drain electrode 5.
Further, the present invention can be using soi layer as substrate, and the soi layer specifically includes from bottom to top successively layer
Second conductive type semiconductor layer 15, buried oxide layer 14 and the formation of the first conductive type semiconductor buffer layer 13 of folded setting, can also
To directly adopt second conductive type semiconductor layer 15 as substrate.
Further, the material of semiconductor used in device of the present invention can be selected from silicon, germanium, silicon carbide, gallium nitride, three oxidations
Two galliums or diamond.
Further, the deep medium groove particular by deep trench filled media material formed.
Further, the semi-insulating polysilicon slot insulating medium layer 12 and then is filled out particular by being initially formed in the trench
Semi-insulating polysilicon material is filled to form.
Further, longitudinal depth of deep medium groove 4 can be equal to or more than the first conductive type semiconductor and drift about
The junction depth in area 10, i.e., deep medium groove 4 extends to the first conductive type semiconductor drift region 10, with the first conduction type half
The lower surface of conductor drift region 10 is overlapped, and is also extended in the first conductive type semiconductor buffer layer 13.
Further, the longitudinal depth of deep medium groove 4 is greater than its width, i.e., the transverse and longitudinal ratio of deep medium groove 4 is less than 1.
Further, longitudinal depth of semi-insulating polysilicon slot can be greater than longitudinal depth of deep medium groove 4, can also be with
Less than longitudinal depth of deep medium groove 4, longitudinal depth of deep medium groove 4 can also be equal to.
Further, semi-insulating polysilicon 11 is contacted by the groove gate dielectric layer 2 of side with trench gate electrode 1.
Further, the junction depth in the second conductive type semiconductor body area 7 is less than the depth of trench gate electrode 1.
Further, semi-insulating polysilicon slot runs through deep medium groove 4.
Further, longitudinal depth of trench gate electrode 1 is less than longitudinal depth of deep medium groove 4.
Further, the second conductive type semiconductor column area is additionally provided in the first conductive type semiconductor drift region 10
17, the second conductive type semiconductor column area 17 laterally connects with the first conductive type semiconductor drift region 10 along deep medium groove 4
And it is folded between two sides the first conductive type semiconductor drift region 10 and is contacted to avoid with semi-insulating polysilicon, and second leads
Electric type semiconductor column area 17 is concordant with the upper and lower surfaces of the first conductive type semiconductor drift region 10.
Further, in the first conductive type semiconductor drift region 10 of 9 lower section of the first conductive type semiconductor drain region also
It is provided with side the first conductive type semiconductor buffer layer 18 for being close to deep 4 side wall of medium groove.First conductive-type of side
The doping concentration of type semiconductor buffer layer 18 can be Uniform Doped, be also possible to successively decrease from top to bottom.
Further, abutting is additionally provided with deeply in the first conductive type semiconductor drift region 10 of deep 4 lower section of medium groove
Bottom surface the first conductive type semiconductor buffer layer 19 of 4 bottom wall of medium groove.The first conductive type semiconductor of bottom surface buffering
The doping concentration of layer 19 can be Uniform Doped, be also possible to successively decrease along metalized drain 5 to 3 direction of metallizing source.
Further, when side the first conductive type semiconductor buffer layer 18 and the first conductive type semiconductor of bottom surface buffer
When layer 19 exists simultaneously, the doping concentration of side the first conductive type semiconductor buffer layer 18 is not less than the first conduction type of bottom surface
The doping concentration of semiconductor buffer layer 19.
Further, in the first conductive type semiconductor drift region 10 of 7 lower section of the second conductive type semiconductor body area also
It is provided with side the second conductive type semiconductor buffer layer for being close to deep 4 side wall of medium groove.Second conduction type of side
The doping concentration of semiconductor buffer layer can be Uniform Doped, be also possible to successively decrease from top to bottom.
Further, the first conductive type semiconductor buffer layer 13, side the first conductive type semiconductor buffer layer 18, bottom
The doping that the doping concentration of face the first conductive type semiconductor buffer layer 18 is greater than the first conductive type semiconductor drift region 10 is dense
Degree.
Further, it is additionally provided with that extending direction therewith is identical and symmetrically arranged first field plate 401 in deep medium groove 4
With the second field plate 402.Wherein longitudinal longitudinal direction for extending depth and being less than deep medium groove 4 of the first field plate 401 and the second field plate 402
Depth；The thickness of dielectric layers of first field plate 401 and the second field plate 402 apart from deep 4 edge of medium groove is adjustable, it can setting
At the uniform field plate of thickness of dielectric layers, stepped field plate also can be set into, or can also be by the way that the first field plate is rationally arranged
401 and second field plate 402 position, both make and the thickness of dielectric layers at 4 edge of adjacent side depth medium groove passed along the longitudinal direction
Increase.
The present invention provides one kind and belongs to MOS type power semiconductor, and specifically a kind of landscape insulation bar double-pole-type is brilliant
Body pipe (i.e. LIGBT device):
A kind of LIGBT device, structure cell include: substrate, the underlayer electrode 16 that substrate back is set and substrate just
The first conductive type semiconductor drift region 10 in face；First conductive type semiconductor drift region, 10 top layer side is provided with MOS knot
Structure, the 10 top layer other side of the first conductive type semiconductor drift region are provided with mutually independent first conductive type semiconductor
The area Buffer and the second conductive type semiconductor collecting zone that the first area conductive type semiconductor Buffer upper surface is set；The
The second conductive type semiconductor collecting zone in one area conductive type semiconductor Buffer upper surface is contacted with deep medium groove 4；；Institute
Stating MOS structure includes the second conductive type semiconductor body area 7, the first conductive type semiconductor source area 6, the second conduction type half
Conductor contact zone 8, source electrode 3 and trench gate structure；Trench gate structure includes trench gate electrode 1 and is arranged in trench gate electrode
The groove gate dielectric layer 2 of 1 side and bottom surface；The setting of second conductive type semiconductor body area 7 is conductive in trench gate structure and first
It is arranged between the area type semiconductor Buffer and close to trench gate structure；The second conductive type semiconductor body area 7 and below
First conductive type semiconductor drift region 10 is in contact by trench dielectric layer 2 with trench gate electrode 1；First conduction type is partly led
Body source area 6 and the second conductive type semiconductor contact zone 8 are disposed side by side on the top layer in the second conductive type semiconductor body area 7,
Wherein the first conductive type semiconductor source area 6 is in contact by the trench dielectric layer 2 of side with trench gate electrode 1；Its feature
It is:
The first conductive type semiconductor buffer layer 13 is provided between substrate and the first conductive type semiconductor drift region 10；
The lower surface of first conductive type semiconductor buffer layer 13 is overlapped with the upper surface of substrate, the first conductive type semiconductor buffer layer
13 upper surface is overlapped with the lower surface of the first conductive type semiconductor drift region 10；The trench gate structure and the first conductive-type
Deep medium groove 4 is provided in the first conductive type semiconductor drift region 10 between the area type semiconductor Buffer；Deep medium ditch
The side of slot 4 is in contact with the second conductive type semiconductor contact zone 8 and the second conductive type semiconductor body area 7；Described first
Semi-insulating polysilicon slot is additionally provided in conductive type semiconductor drift region 10, the semi-insulating polysilicon slot includes semi-insulating more
Crystal silicon 11 and the insulating medium layer 12 that 11 side of semi-insulating polysilicon and bottom surface are set, the semi-insulating polysilicon slot is along deep
4 transverse extension direction of medium groove replaces with the first conductive type semiconductor drift region 10 to connect, wherein semi-insulating polysilicon slot
Upper surface it is concordant with the upper surface of the second conductive type semiconductor collecting zone, lower surface and the first conductive type semiconductor float
The lower surface for moving area 10 is concordant；Semi-insulating polysilicon 11 is contacted by groove gate dielectric layer 2 with trench gate electrode 1, semi-insulating more
Crystal silicon 11, insulating medium layer 12, the first conductive type semiconductor source area 6, the second conductive type semiconductor contact zone 8 upper table
Active electrode 3 is arranged in face；Source electrode 3 and trench gate electrode 1 are isolated by dielectric layer；Semi-insulating polysilicon slot and the first conduction
The upper surface in type semiconductor drain region 9 is provided with drain electrode 5.
Further, the present invention can be using soi layer as substrate, and the soi layer specifically includes from bottom to top successively layer
Second conductive type semiconductor layer 15, buried oxide layer 14 and the formation of the first conductive type semiconductor buffer layer 13 of folded setting, can also
To directly adopt second conductive type semiconductor layer 15 as substrate.
Further, the material of semiconductor used in device of the present invention can be selected from silicon, germanium, silicon carbide, gallium nitride, three oxidations
Two galliums or diamond.
Further, the deep medium groove particular by deep trench filled media material formed.
Further, the semi-insulating polysilicon slot insulating medium layer 12 and then is filled out particular by being initially formed in the trench
Semi-insulating polysilicon material is filled to form.
Further, longitudinal depth of deep medium groove 4 can be equal to or more than the first conductive type semiconductor and drift about
The junction depth in area 10, i.e., deep medium groove 4 extends to the first conductive type semiconductor drift region 10, with the first conduction type half
The lower surface of conductor drift region 10 is overlapped, and is also extended in the first conductive type semiconductor buffer layer 13.
Further, the longitudinal depth of deep medium groove 4 is greater than its width, i.e., the transverse and longitudinal ratio of deep medium groove 4 is less than 1.
Further, longitudinal depth of semi-insulating polysilicon slot can be greater than longitudinal depth of deep medium groove 4, can also be with
Less than longitudinal depth of deep medium groove 4, longitudinal depth of deep medium groove 4 can also be equal to.
Further, semi-insulating polysilicon 11 is contacted by the groove gate dielectric layer 2 of side with trench gate electrode 1.
Further, the junction depth in the second conductive type semiconductor body area 7 is less than the depth of trench gate electrode 1.
Further, semi-insulating polysilicon slot runs through deep medium groove 4.
Further, longitudinal depth of trench gate electrode 1 is less than longitudinal depth of deep medium groove 4.
Further, the second conductive type semiconductor column area is additionally provided in the first conductive type semiconductor drift region 10
17, the second conductive type semiconductor column area 17 laterally connects with the first conductive type semiconductor drift region 10 along deep medium groove 4
And it is folded between two sides the first conductive type semiconductor drift region 10 and is contacted to avoid with semi-insulating polysilicon column, and second
Conductive type semiconductor column area 17 is concordant with the upper and lower surfaces of the first conductive type semiconductor drift region 10.
Further, in the first conductive type semiconductor drift region 10 of 9 lower section of the second conductive type semiconductor collecting zone
It is additionally provided with side the first conductive type semiconductor buffer layer 18 for being close to deep 4 side wall of medium groove.The side first is conductive
The doping concentration of type semiconductor buffer layer 18 can be Uniform Doped, be also possible to successively decrease from top to bottom.
Further, abutting is additionally provided with deeply in the first conductive type semiconductor drift region 10 of deep 4 lower section of medium groove
Bottom surface the first conductive type semiconductor buffer layer 19 of 4 bottom wall of medium groove.The first conductive type semiconductor of bottom surface buffering
The doping concentration of layer 19 can be Uniform Doped, be also possible to successively decrease along metalized drain 5 to 3 direction of metallizing source.
Further, when side the first conductive type semiconductor buffer layer 18 and the first conductive type semiconductor of bottom surface buffer
When layer 19 exists simultaneously, the doping concentration of side the first conductive type semiconductor buffer layer 18 is not less than the first conduction type of bottom surface
The doping concentration of semiconductor buffer layer 19.
Further, in the first conductive type semiconductor drift region 10 of 7 lower section of the second conductive type semiconductor body area also
It is provided with side the second conductive type semiconductor buffer layer for being close to deep 4 side wall of medium groove.Second conduction type of side
The doping concentration of semiconductor buffer layer can be Uniform Doped, be also possible to successively decrease from top to bottom.
Further, the first conductive type semiconductor buffer layer 13, side the first conductive type semiconductor buffer layer 18, bottom
The doping that the doping concentration of face the first conductive type semiconductor buffer layer 18 is greater than the first conductive type semiconductor drift region 10 is dense
Degree.
Further, it is additionally provided with that extending direction therewith is identical and symmetrically arranged first field plate 401 in deep medium groove 4
With the second field plate 402.Wherein longitudinal longitudinal direction for extending depth and being less than deep medium groove 4 of the first field plate 401 and the second field plate 402
Depth；The thickness of dielectric layers of first field plate 401 and the second field plate 402 apart from deep 4 edge of medium groove is adjustable, it can setting
At the uniform field plate of thickness of dielectric layers, stepped field plate also can be set into, or can also be by the way that the first field plate is rationally arranged
401 and second field plate 402 position, both make and the thickness of dielectric layers at 4 edge of adjacent side depth medium groove passed along the longitudinal direction
Increase.
In addition, the present invention also provides a kind of preparation methods of lateral MOS type power semiconductor, which is characterized in that
Include the following steps:
(1) second conductive type semiconductor layer is chosen as substrate；
(2) the first conductive type semiconductor buffer layer is formed on second conductive type semiconductor layer；
(3) the first conductive type semiconductor drift region is formed on the first conductive type semiconductor buffer layer；
(4) by the way that in the first conductive type semiconductor drift region etching groove, wall forms insulating medium layer simultaneously in the trench
Semi-insulating polysilicon material is filled in the groove, and formation is connected with the first conductive type semiconductor drift region and upper and lower surface
Concordant semi-insulating polysilicon column；
(5) along the direction etching at the interface that connects perpendicular to the first conductive type semiconductor drift region with semi-insulating polysilicon column
Deep trouth, and filled media material forms deep media slot in the deep trouth；
(6) trench gate structure is formed in the first conductive type semiconductor drift region of deep medium groove side；
(7) is formed in the first conductive type semiconductor drift region top layer between deep medium groove and trench gate structure
Two conductive type semiconductor base areas, the junction depth of the second conductive type semiconductor base area are less than longitudinal depth of trench gate structure；
(8) top layer in the second conductive type semiconductor base area forms the first conductive type semiconductor source area and second and leads
Electric type semiconductor contact zone；
(9) the first conductive type semiconductor drift region top layer in the deep medium groove other side forms the first conduction type half
Conductor drain region, or the first conductive type semiconductor drift region top layer the first conduction type of formation in the deep medium groove other side
The area semiconductor Buffer and the second conductive type semiconductor collecting zone；
(10) dielectric layer deposited, photoetching, hole etching；Source electrode metal and drain metal are formed, overturning device is overleaf
Form underlayer electrode metal.
Further, substrate can directly select soi layer in the present invention, and the soi layer specifically includes from bottom to top successively
Second conductive type semiconductor layer 15, buried oxide layer 14 and the formation of the first conductive type semiconductor buffer layer 13 being stacked, when
First conductive type semiconductor buffer layer 13 of soi layer, which reaches actually required thickness, can omit step 2.
Further, the present invention in semiconductor material can selected from silicon, germanium, silicon carbide, gallium nitride, gallic oxide or
Person's diamond.
The working principle of the invention is specific as follows:
The present invention in drift region by introducing deep medium groove on the basis of lateral MOS type semiconductor power device
And along the deep medium channel lateral extending direction semi-insulating polysilicon column area to connect parallel with drift region as three-dimensional resistive field
Hardened structure, and buffer layer is introduced between drift region and substrate.When source electrode 3, trench gate electrode 1, underlayer electrode 16 connect low electricity
Position, when drain electrode 5 connects high potential, device is in blocking state, at this time since the presence of medium groove deep in drift region makes device
Conductive channel U-shaped conductive channel is become by traditional interconnection, drift is effectively increased in situation under same device length
Move the length in area；Simultaneously because the resistive field plate of three-dimensional with the semi-insulating polysilicon SIPOS column area offer of deep medium groove vertical
Effect, device can form multidimensional depletion action in multiple directions when blocking, and then make drift region and buffer layer in device breakdown
It is before completely depleted, the doping concentration of drift region and buffer layer is improved with this, improves the electric field point of N-type drift region and buffer layer
Cloth；Exactly because simultaneously also the present invention overcomes the problem that the brought drift region of deep trench can not be completely depleted, thus it is of the invention
Device without using traditional technology for the means for maintaining deep media slot certain depth to deepen trench gate structure, thus can be real
Existing shallow ridges slot grid structure, and then the gate capacitance of device is reduced, improve devices switch speed；Also, due to deep medium channel medium
Relatively high critical breakdown electric field, device is while obtaining high-breakdown-voltage, ratio conducting resistance/conduction voltage drop for reducing.
Meanwhile half different from drift region doping type are introduced with respect to the other side in semi-insulating polysilicon SIPOS column area in N-type drift region
Conductive region forms super-junction structure, can further provide for three-dimensional charge compensation effect, the electric field in drift region is made to form class ladder
Shape distribution, overcomes the problem that drift region brought by thick drift region and deep trench can not be completely depleted, further improves device
The doping concentration of part drift region；Due to semi-insulating polysilicon SIPOS column area and the semiconductor region different from drift region doping type
The three-dimensional depletion action that domain provides, makes the drift sector width of deep trench two sides be not limited in high doping concentration by dopant dose
Under wide width can be used, improving the conducting resistance that device is reduced while device pressure resistance.In addition, further in deep medium
Trenched side-wall and bottom wall introduce high concentration N-type buffer layer, can make full use of back buries oxide layer and deep trench dielectric layer provides
Reduction surface field RESURF act on to improve drift doping concentration, while also inhibiting substrate and deep medium groove two
Side assisted depletion as caused by current potential difference, improves the electricity between the different semiconductor regions of doping type in super-junction structure
Lotus equilibrium response, while high concentration N-type buffer layer further reduced conducting resistance, improve the Performance And Reliability of device.
Compared with prior art, beneficial effects of the present invention are as follows:
The present invention in drift region by introducing deep medium groove and along deep medium channel lateral extending direction and drift
The semi-insulating polysilicon column area that area connects in parallel makes the conductive channel of device by traditional transverse direction as three-dimensional resistive field plate structure
Channel becomes U-shaped conductive channel, increases the effective length of drift region under certain device length, and by when blocking
Multiple directions, which form multidimensional depletion action, makes N-type drift region and N-type the buffer layer fully- depleted before device breakdown, is obtaining high device
While part breakdown voltage, reduces and compare conducting resistance；Simultaneously N-type buffer layer introducing make full use of back buries oxide layer and
Deep trench dielectric layer provide reduction surface field RESURF effect improve drift doping concentration while, it is suppressed that substrate with
And deep trench two sides assisted depletion as caused by current potential difference, the pressure resistance of device is further improved, and reduce than conducting
Resistance has saved chip area, reduces costs.
Detailed description of the invention
Fig. 1 is traditional deep trench LDMOS device structural schematic diagram；Wherein: 1 is trench gate electrode, and 2 be groove gate medium
Layer, 3 be source electrode, and 4 be deep medium groove, and 5 be drain electrode, and 6 be N+ source area, and 7 be p-type base area, and 8 be the contact zone P+, and 9 be N
Type drain region, 10 be N-type drift region, and 15 be p type semiconductor layer, and 16 be underlayer electrode.
Fig. 2 is a kind of structural schematic diagram of the LDMOS device of embodiment 1；
Fig. 3 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 1 along AB；
Fig. 4 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 1 along CD；
Fig. 5 is a kind of three dimensional structure diagram of the LDMOS device of embodiment 2；
Fig. 6 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 2 along AB；
Fig. 7 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 2 along CD；
Fig. 8 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 2 along EF；
Fig. 9 is a kind of three dimensional structure diagram of the LDMOS device of embodiment 3；
Figure 10 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 3 along AB；
Figure 11 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 3 along CD；
Figure 12 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 3 along EF；
Figure 13 is a kind of three dimensional structure diagram of the LDMOS device of embodiment 4；
Figure 14 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 4 along AB；
Figure 15 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 4 along CD；
Figure 16 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 4 along EF；
Figure 17 is a kind of three dimensional structure diagram of the LDMOS device of embodiment 5；
Figure 18 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 5 along AB；
Figure 19 is a kind of diagrammatic cross-section of the LDMOS device of embodiment 5 along CD；
In Fig. 2 to 19: 1 is trench gate electrode, and 2 be groove gate dielectric layer, and 3 be source electrode, and 4 be deep medium groove, and 104 are
First field plate, 402 be the second field plate, and 5 be drain electrode, and 6 be N+ source area, and 7 be p-type base area, and 8 be the contact zone P+, and 9 leak for N-type
Area, 10 be N-type drift region, and 11 be semi-insulating polysilicon.12 be insulating medium layer, and 13 be N-type buffer layer, and 14 be buried oxide layer, 15
It is underlayer electrode for p type semiconductor layer, 16,17 be the area PXing Zhu, and 18 be side N-type buffer layer, and 19 be bottom surface N-type buffer layer.
Specific embodiment
To enable those skilled in the art to understand the present invention program and principle, in the following with reference to the drawings and specific embodiments into
Row detailed description.The contents of the present invention are not limited to any specific embodiment, and also not representing is most preferred embodiment, art technology
General substitution known to personnel is also encompassed within the scope of the invention.
Embodiment 1:
The present embodiment provides a kind of LDMOS device, structure cell as shown in Fig. 2, structure cell shown in Fig. 2 along AB line and
The schematic diagram of the section structure difference of CD line is as shown in Figures 3 and 4, and from the point of view of Fig. 2 to 4, the structure cell includes: longitudinal under
And underlayer electrode 16, p type semiconductor layer 15, buried oxide layer 14, N-type buffer layer 13 and the N-type drift region 10 of upper stacking；N-type drift
10 surface side of area is provided with N-type drain region 9；The 10 surface other side of N-type drift region is provided with MOS structure, and the MOS structure includes
The area PXing Ti 7, N+ source area 6, the contact zone P+ 8, trench gate structure and source electrode 3, wherein trench gate structure includes trench gate electrode
1 and the groove gate dielectric layer 2 of 1 side of trench gate electrode and bottom surface is set, the area PXing Ti 7 be arranged close to 9 side of N-type drain region and
It is in contact with trench gate structure, the top layer in the area PXing Ti 7 is arranged in the N+ source area 6 and the contact zone P+ 8, and N+ source area 6 leans on
Nearly trench gate structure side setting；It is characterized by:
The depth by being filled with dielectric material is provided in N-type drift region 10 between the trench gate structure and N-type drain region 9
Slot is formed by deep medium groove 4；The side of deep medium groove 4 is in contact with the contact zone P+ 8 and the area PXing Ti 7；The N-type drift
Move the semi-insulating polysilicon column 11 being additionally provided in area 10 along the setting of deep 4 transverse extension direction of medium groove；Semi-insulating polysilicon
Column 11, the area PXing Ti 7 and N-type drift region 10 are contacted with trench gate electrode 1 by groove gate dielectric layer 2；Semi-insulating polysilicon 11,
Insulating medium layer 12, N+ source area 6, the contact zone P+ 8 upper surface be arranged active electrode 3；Source electrode 3 and trench gate electrode 1 are logical
Dielectric layer is crossed to be isolated；The upper surface in semi-insulating polysilicon 11 and N-type drain region 9 is provided with drain electrode 5.
N-type buffer layer 13 with a thickness of 0.5~2 μm in the present embodiment；Doping concentration is 1015~1017A/cm3；N-type drift
Moving the width of area 10 in the z-direction is 0.5~2 μm, and depth in the y-direction is 5~25 μm, and width in the x-direction is 4~20 μm；
Doping concentration is 1015~1017A/cm3；Longitudinal depth is 5~20 μm to deep medium groove 4 along the y-axis direction, along the x-axis direction
Width is 2~10 μm.
Embodiment 2:
The present embodiment provides a kind of LDMOS device, structure cell as shown in figure 5, structure cell shown in Fig. 5 along AB line,
The schematic diagram of the section structure of CD line and EF line is respectively as shown in Fig. 6,7 and 8, and from the point of view of Fig. 5 to 8, the present embodiment is to implement
On the basis of example 1, the area PXing Zhu 17, the area PXing Zhu are equipped in the side that the drift region N- 10 is relatively distant from semi-insulating polysilicon column 11
17 lower surface is in contact with N- buffer layer 13；The area PXing Zhu 17 is flat along deep 4 transverse extension direction of medium groove and the drift region N- 10
Row connects and is alternately arranged to form super-junction structure.The width of the area the present embodiment ZhongPXing Zhu 17 along the z-axis direction is 0.5~1.5 μm,
Longitudinal depth is 5~25 μm along the y-axis direction, and width along the x-axis direction is 4~20 μm, doping concentration 1015~1017A/
cm3.The introducing in the area PXing Zhu 17 further provides three-dimensional charge compensation effect, and the electric field in N-type drift region 10 is made to form class ladder
Shape distribution, further improves the doping concentration and breakdown voltage of device drift region.
Embodiment 3:
The present embodiment provides a kind of LDMOS device, structure cell as shown in figure 9, structure cell shown in Fig. 9 along AB line,
The schematic diagram of the section structure of CD line and EF line respectively as shown in Figure 10,11 and 12, the present embodiment be on the basis of embodiment 2,
The side N-type buffering of deep 4 side wall of medium groove is close in setting in N-type drift region 10 and the area PXing Zhu 17 below N-type drain region 9
Layer 18, the doping concentration of side N-type buffer layer 18 are not less than the doping concentration of N-type drift region 10.The side N-type buffer layer 18
Doping concentration can be Uniform Doped, be also possible to successively decrease from top to bottom.The introducing of side N-type buffer layer 18 can inhibit by
Influence of the assisted depletion to 17 charge balance of N-type drift region 10 and the area PXing Zhu caused by deep trench two sides current potential is different, is mentioning
While high device pressure resistance, the conducting resistance of device is further decreased.
Embodiment 4:
The present embodiment provides a kind of LDMOS devices, and structure cell is as shown in figure 13, and structure cell is along AB shown in Figure 13
For the schematic diagram of the section structure of line, CD line and EF line respectively as shown in Figure 14,15 and 16, the present embodiment is on the basis of embodiment 3
On, the bottom surface for being close to deep 4 bottom wall of medium groove is additionally provided in the N-type drift region 10 and the area PXing Zhu 17 below deep medium groove 4
N-type buffer layer 19, the doping concentration of bottom surface N-type buffer layer 19 are greater than the doping concentration of N-type drift region 10.The bottom surface N-type is slow
The doping concentration for rushing layer 19 can be Uniform Doped, is also possible to right-to-left and successively decreases.The introducing of bottom surface N-type buffer layer 19 can be with
Inhibit as zanjon trench bottom it is different from source potential caused by assisted depletion to 17 charge balance of N-type drift region 10 and P column
It influences, while improving device pressure resistance, further decreases the conducting resistance of device.
Embodiment 5:
The present embodiment provides a kind of LDMOS devices, and structure cell is as shown in figure 17, and structure cell shown in Figure 17 is along AB line
It is as shown in Figures 18 and 19 with the schematic diagram of the section structure difference of CD line.The present embodiment is on the basis of embodiment 1, in deep medium
The first field plate 401 and the second field plate along the direction setting that connects parallel with semi-insulating polysilicon column 11 of the area NXing Zhu 10 are introduced in slot 4
402, longitudinal depth of first field plate 401 and the second field plate 402 is less than longitudinal depth of deep medium groove 4.First field plate
401 and second field plate 402 and deep 4 edge of medium groove thickness of dielectric layers it is adjustable, it may be assumed that it is uniform that thickness of dielectric layers can be used
Stepped field plate can be used in field plate, can also by the way that the position of the first field plate 401 and the second field plate 402 is rationally arranged, both make with
The thickness of dielectric layers at 4 edge of adjacent side depth medium groove is that y-axis direction shown in figure is incremented by along the longitudinal direction.First field plate
401 and second the introducing of field plate 402 can further adjust deep 4 two sides N-type drift region 10 of medium groove and semi-insulating polysilicon
Electric field in column 11 further increases device pressure resistance.
Embodiment 6:
The present embodiment provides a kind of LDMOS devices, N-type drift region on the basis of embodiment 4, below the area PXing Ti 7
The side p-type buffer layer of deep 4 side wall of medium groove is close in setting in 10.The doping concentration of side p-type buffer layer can be uniformly
Doping, is also possible to successively decrease from top to bottom.The introducing of side p-type buffer layer can be further suppressed due to deep trench two sides current potential
Influence of the assisted depletion caused by difference to super-junction structure charge balance further decreases device while improving device pressure resistance
The conducting resistance of part.
Embodiment 7:
The present embodiment provides a kind of LDMOS devices, on the basis of embodiment 1, omit the semi-insulating polysilicon column 11
With the insulating medium layer 12 between deep medium groove 4, N-type buffer layer 13 and N-type drift region 10, i.e., semi-insulating polysilicon column 11 with
Deep medium groove 4, N-type buffer layer 13 and N-type drift region 10 directly contact.It in this way can be into one on the basis of retainer member characteristic
It walks and simplifies technique, reduce cost.
Embodiment 8:
A kind of LIGBT device, the structure cell include: longitudinal underlayer electrode 16, P-type semiconductor being laminated from bottom to top
Layer 15, buried oxide layer 14, N-type buffer layer 13 and N-type drift region 10；10 surface side of N-type drift region be provided with it is mutually indepedent and N
The area type Buffer and the p-type collecting zone that the area N-type Buffer upper surface is set；The p-type collecting zone of the area N-Buffer upper surface with
Deep medium groove 4 contacts；P-type collecting zone is contacted with the metalized drain 5 of top；The 10 surface other side of N-type drift region is provided with
MOS structure, the MOS structure include the area PXing Ti 7, N+ source area 6, the contact zone P+ 8, trench gate structure and source electrode 3, wherein
Trench gate structure includes trench gate electrode 1 and the groove gate dielectric layer 2 that 1 side of trench gate electrode and bottom surface is arranged in, the area PXing Ti
7 are arranged close to the area N-type Buffer and p-type collecting zone side and are in contact with trench gate structure, the N+ source area 6 and P+ contact
The top layer in the area PXing Ti 7 is arranged in area 8, and N+ source area 6 is arranged close to trench gate structure side；It is characterized by:
It is provided in N-type drift region 10 between the trench gate structure and the area N-type Buffer and p-type collecting zone by filling
There is the deep trouth of dielectric material to be formed by deep medium groove 4；The side of deep medium groove 4 and 7 phase of the contact zone P+ 8 and the area PXing Ti
Contact；The semi-insulating polysilicon column along the setting of deep 4 transverse extension direction of medium groove is additionally provided in the N-type drift region 10
(including semi-insulating polysilicon 11 and insulating medium layer 12)；Semi-insulating polysilicon 11, the area PXing Ti 7 and N-type drift region 10 and groove
Gate electrode 1 is contacted by groove gate dielectric layer 2；Semi-insulating polysilicon 11, insulating medium layer 12, N+ source area 6, the contact zone P+ 8
Upper surface be arranged active electrode 3；Source electrode 3 and trench gate electrode 1 are isolated by dielectric layer 2；Semi-insulating polysilicon column p-type
The upper surface of collecting zone is provided with drain electrode 5.
Skilled person will appreciate that all deformations of above embodiments stand good for superjunction IGBT device, herein
Details are not described herein.
Embodiment 9:
A kind of preparation method of lateral MOS type device provided by the invention, comprising the following steps:
Step 1: choosing certain thickness soi layer on demand as substrate, SOI material is by N-type buffer layer, buried oxide layer, p-type
Substrate three parts are constituted, and the doping concentration of N-type buffer layer is 1015~1017A/cm3；The doping concentration of P type substrate is 1014~
1015A/cm3；
Step 2: the certain thickness N-type drift region of extension over the substrate, doping concentration 1015~1017A/cm3；
Step 3: forming groove in drift region photomask surface, etching N-type drift region, and one layer is formed by high-temperature oxydation
Then dielectric layer deposits semi-insulating polysilicon SIPOS film filling groove and forms semi-insulating polysilicon column area；And pass through CMP work
The SIPOS material of skill removal excess surface；
Step 4: layer of oxide layer is grown on drift region surface, using photoetching process along exhausted with half perpendicular to the drift region N-
The direction of edge polysilicon pillar area interface etches to form medium deep trouth, silica dioxide medium is then filled in medium deep trouth, so
The dielectric material of excess surface is removed by CMP process afterwards；
Step 5: the N-type drift region using photoetching process in deep medium groove side etches and to form gate groove, and pass through height
Temperature oxidation forms gate oxide in gate groove surface growth silica, is then filled with polysilicon and forms gate electrode；The grid ditch
The depth of slot is less than the depth of deep medium groove；
Step 6: by ion implanting, simultaneously high annealing forms p-type base area between gate groove and deep medium groove；It is described
The depth of p-type base area is less than the depth of gate groove；
N-type drain region, N-type source region and p-type contact zone are sequentially formed step 7: passing through ion implanting and annealing；
Step 8: dielectric layer deposited, photoetching, hole etching；It deposits metal in device surface and etches and form source electrode and leakage
Electrode；Overturning silicon chip back side metallizes to form underlayer electrode.
Further first step SOI material can also directly select certain thickness P type substrate material, and P type substrate is mixed
Miscellaneous concentration is 1014~1015A/cm3。
It should be strongly noted that the material of substrate of the present invention can be typically chosen SOI substrate material such as embodiment, it can also
With direct P-type semiconductor layer material.Semiconductor material used in device of the present invention can be silicon, germanium, silicon carbide, gallium nitride, three oxidations
Any suitable semiconductor material such as two galliums, diamond.The medium layer insulating filled in depth medium groove of the present invention 4 can be with
Using Single Medium material, the composite material that can also be formed using different dielectric materials is specific such as silica, nitridation
It is any one or more in silicon, sapphire or other suitable insulating dielectric materials.In addition, herein to simplify the description, device junction
Structure and preparation method are to illustrate by taking N-channel LDMOS device as an example, but the present disclosure applies equally to P-channel LDMOS devices.
Embodiment cited by the present invention and compare previous embodiment relationship and it is exhaustive or limitation, those skilled in the art are in the present invention
All technical solutions for being combined multiple technical characteristics on the basis of specification is disclosed are in protection model of the invention
In enclosing, processing step and process conditions in device preparation method of the present invention can carry out additions and deletions and adjustment according to actual needs.
The embodiment of the present invention is elaborated in conjunction with attached drawing above, but the invention is not limited to above-mentioned
Specific embodiment, above-mentioned specific embodiment is only schematical, rather than restrictive, the ordinary skill people of this field
Member under the inspiration of the present invention, can also make many in the case where not departing from present inventive concept and claimed range
Deformation, these belong to protection of the invention.
Claims (10)
1. a kind of lateral MOS type power semiconductor, structure cell includes: substrate, the substrate electricity that substrate back is arranged in
First conductive type semiconductor drift region (10) of pole (16) and substrate face；First conductive type semiconductor drift region (10) top
Layer side is provided with the first conductive type semiconductor drain region (9)；First conductive type semiconductor drift region (10) top layer other side
It is provided with MOS structure, the MOS structure includes the second conductive type semiconductor body area (7), the first conductive type semiconductor source electrode
Area (6), the second conductive type semiconductor contact zone (8), source electrode (3) and trench gate structure；Trench gate structure includes trench gate
Electrode (1) and setting trench gate electrode (1) side and bottom surface groove gate dielectric layer (2)；Second conductive type semiconductor
Body area (7) is arranged between trench gate structure and the first conductive type semiconductor drain region (9) and is arranged close to trench gate structure；The
Two conductive type semiconductor body areas (7) and the first conductive type semiconductor drift region (10) below pass through trench dielectric layer
(2) it is in contact with trench gate electrode (1)；First conductive type semiconductor source area (6) and the contact of the second conductive type semiconductor
Area (8) is disposed side by side on the top layer in the second conductive type semiconductor body area (7), wherein the first conductive type semiconductor source area
(6) it is in contact by the trench dielectric layer (2) of side with trench gate electrode (1)；It is characterized by:
The first conductive type semiconductor buffer layer (13) is provided between substrate and the first conductive type semiconductor drift region (10)；
The lower surface of first conductive type semiconductor buffer layer (13) is overlapped with the upper surface of substrate, the first conductive type semiconductor buffering
The upper surface of layer (13) is overlapped with the lower surface of the first conductive type semiconductor drift region (10)；The trench gate structure and first
Deep medium groove (4) is provided in the first conductive type semiconductor drift region (10) between conductive type semiconductor drain region (9)；
The side of deep medium groove (4) and the second conductive type semiconductor contact zone (8) and second conductive type semiconductor body area (7) phase
Contact；Semi-insulating polysilicon slot, the semi-insulating polycrystalline are additionally provided in first conductive type semiconductor drift region (10)
Silicon slot includes the insulating medium layer (12) of semi-insulating polysilicon (11) and setting in semi-insulating polysilicon (11) side and bottom surface, institute
Semi-insulating polysilicon slot is stated to replace along deep medium groove (4) transverse extension direction with the first conductive type semiconductor drift region (10)
Connect, wherein the upper surface of semi-insulating polysilicon slot is concordant with the upper surface in the first drain region conductive type semiconductor N (9), under
Surface is concordant with the lower surface of the first drift region conductive type semiconductor N (10)；Semi-insulating polysilicon (11) is situated between by trench gate
Matter layer (2) is contacted with trench gate electrode (1), semi-insulating polysilicon (11), insulating medium layer (12), the first conductive type semiconductor
Upper surface setting active electrode (3) of source area (6), the second conductive type semiconductor contact zone (8)；Semi-insulating polysilicon slot
(11) and the upper surface in the first conductive type semiconductor drain region (9) is provided with drain electrode (5).
2. a kind of lateral MOS type power semiconductor according to claim 1, it is characterised in that: led described first
Electric type semiconductor drain region (9) replaces with the mutually independent area first conductive type semiconductor Buffer and setting in the first conduction
Second conductive type semiconductor collecting zone of the area type semiconductor Buffer upper surface；First area conductive type semiconductor Buffer
Second conductive type semiconductor collecting zone of upper surface is contacted with deep medium groove (4)；Second conductive type semiconductor collecting zone
It is contacted with the metalized drain (5) of top, forms IGBT device.
3. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: the first conductive-type
The second conductive type semiconductor column area (17), the second conductive type semiconductor column area are additionally provided in type drift semiconductor area (10)
(17) laterally connect with the first conductive type semiconductor drift region (10) along deep medium groove (4) and be folded in the first conduction of two sides
Between type semiconductor drift region (10), and the second conductive type semiconductor column area (17) and the first conductive type semiconductor float
The upper and lower surfaces for moving area (10) are concordant.
4. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: the depth medium
Longitudinal depth of groove (4) is equal to or more than the junction depth of the first conductive type semiconductor drift region (10).
5. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: the first conductive-type
The in the first conductive type semiconductor drift region (10) below type semiconductor drain region (9) and/or below deep medium groove (4)
The first conduction type in one conductive type semiconductor drift region (10) and/or below the second conductive type semiconductor body area (7)
The buffer layer for being close to deep medium groove (4) wall surface is provided in drift semiconductor area (10).
6. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: trench gate electrode
(1) longitudinal depth is less than longitudinal depth of deep medium groove (4).
7. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: the depth medium
Identical extending direction therewith is provided in groove (4) and symmetrically arranged first field plate (401) and the second field plate (402), first
Longitudinal longitudinal depth for extending depth and being less than deep medium groove (4) of field plate (401) and the second field plate (402).
8. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: described semi-insulating
Polysilicon slot runs through deep medium groove (4).
9. a kind of lateral MOS type power semiconductor according to claim 1 or 2, it is characterised in that: described first leads
Electric type semiconductor is N-type semiconductor.Second conductive type semiconductor is P-type semiconductor or the first conductive type semiconductor
For P-type semiconductor.Second conductive type semiconductor is N-type semiconductor.
10. a kind of preparation method of lateral MOS type power semiconductor, which comprises the steps of:
1) second conductive type semiconductor layer is chosen as substrate；
2) the first conductive type semiconductor buffer layer is formed on second conductive type semiconductor layer；
3) the first conductive type semiconductor drift region is formed on the first conductive type semiconductor buffer layer；
4) by the way that in the first conductive type semiconductor drift region etching groove, wall forms insulating medium layer and described in the trench
Semi-insulating polysilicon material is filled in groove, formed connect with the first conductive type semiconductor drift region and upper and lower surface concordantly
Semi-insulating polysilicon slot；
5) direction along the interface that connects perpendicular to the first conductive type semiconductor drift region with semi-insulating polysilicon slot etches deep trouth,
And filled media material forms deep media slot in the deep trouth；
6) trench gate structure is formed in the first conductive type semiconductor drift region of deep medium groove side；
7) second is formed in the first conductive type semiconductor drift region top layer between deep medium groove and trench gate structure to lead
Electric type semiconductor base area, the junction depth of the second conductive type semiconductor base area are less than longitudinal depth of trench gate structure；
8) top layer in the second conductive type semiconductor base area forms the first conductive type semiconductor source area and the second conductive-type
Type semiconductor contact regions；
9) the first conductive type semiconductor drift region top layer in the deep medium groove other side forms the first conductive type semiconductor
Drain region, or the deep medium groove other side the first conductive type semiconductor drift region top layer formed the first conduction type partly lead
The area body Buffer and the second conductive type semiconductor collecting zone；
10) dielectric layer deposited, photoetching, hole etching；Source electrode metal and drain metal are formed, overturning device overleaf forms lining
Hearth electrode metal.
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