CN104282763B - Radio frequency horizontal dual pervasion field effect transistor preparation method - Google Patents
Radio frequency horizontal dual pervasion field effect transistor preparation method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a kind of radio frequency horizontal dual pervasion field effect transistor, drift region is non-uniform doping structure.The invention also discloses this kind of preparation method of radio frequency horizontal dual pervasion field effect transistor, drift region forms N type junction structure heterogeneous using three N-type ion implantings, first time N-type ion implanting is a self-aligned vertical injection for low dosage medium energy, second N-type ion implanting is an autoregistration oblique angle injection for low dosage low energy, then again by template definition, the position in the drift region for leaving the segment distance of polysilicon gate one carries out third time N-type ion implanting.Radio frequency horizontal dual pervasion field effect transistor of the invention and preparation method thereof, under conditions of thick Faraday shield oxide layer, reduces output capacitance, enhances hot carrier in jection ability and robustness, and manufacturing process is simple.
Description
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of radio frequency horizontal dual pervasion field effect transistor and its making side
Method.
Background technology
With the arrival in 3G epoch, communication field more and more requires the exploitation of more powerful RF devices.Radio frequency is horizontal
To bilateral diffusion field-effect tranisistor (RFLDMOS), because it has power output very high, early in the nineties in last century just
Through being widely used in the amplification of hand-held radio base station power, its applying frequency is 900MHz to 3.8GHz.RFLDMOS and biography
The silicon substrate bipolar transistor of system is compared, with the more preferable linearity, power higher and gain.Nowadays, RFLDMOS is than bipolar
Pipe, and GaAs devices are more favourable.
As shown in figure, this structure has the drift region (LDD) being lightly doped in drain terminal to the structure of current RFLDMOS, so that
Larger breakdown voltage (BV) is made it have, simultaneously because its drift region concentration is thin, larger conducting resistance is made it have
(Rdson).The effect of faraday shield layer is the gate leakage capacitance (Cgd) for reducing feedback, simultaneously because it is in zero in the application
Current potential, can act version of showing up, and reduce surface field, so as to increase the breakdown voltage of device, and can play suppression
The effect of hot carrier in jection.In the design of RFLDMOS, its output capacitance decides the frequency characteristic of device, should in high frequency
Lower output capacitance is required with middle, conducting resistance (Rdson) and saturation current (Idsat) determine the electric current driving energy of device
Power, conducting resistance (Rdson) should be the smaller the better, and saturation current (Idsat) should be the bigger the better, robustness (Ruggedness) energy
Power decides product service life.
Radio frequency horizontal dual pervasion field effect transistor in frequency applications, in order to further reduce the output capacitance of device
(Coss), generally the Faraday shield metal level lower section oxide layer of radio frequency horizontal dual pervasion field effect transistor is thickeied, but
Hot carrier in jection ability (HCI) characteristic and robustness of device are so influenced whether, so as to have influence on the use longevity of device
Life.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of radio frequency horizontal dual pervasion field effect transistor and its making side
Method, under conditions of thick Faraday shield oxide layer, can reduce output capacitance (Coss), improve the hot carrier in jection energy of device
Power (HCI) characteristic and robustness (Ruggedness), and process is simple.
In order to solve the above technical problems, the preparation method of the radio frequency horizontal dual pervasion field effect transistor that the present invention is provided,
Comprise the following steps：
One, growing P-type epitaxial layers in P type substrate, the doping concentration of p-type epitaxial layer is lower than P type substrate；
Two, oxide layers of thermal oxide growth one on p-type epitaxial layer, then deposit one layer of polysilicon, the light in the middle part of silicon chip
Quarter etches polysilicon gate；
Three, retain the photoresist above polysilicon gate, carry out first time N-type ion implanting, and first time N-type ion implanting is
Self-aligned vertical injects；
Four, retain the photoresist above polysilicon gate, carry out second N-type ion implanting, and second N-type ion implanting is
Autoregistration oblique angle injects, second N-type ion implanting depth ratio first time N-type ion implanting depth as shallow；
Five, define third time N-type ion implanted regions by photolithography plate, and third time N-type ion implanted regions are more to leave
The p-type epitaxial layer of crystal silicon grid right side certain distance；Third time N-type ion implanted regions inject N-type ion, third time N-type from
, more than or equal to first time and second N-type ion implanting depth, dosage is less than or equal to first time and second N-type for sub- injection depth
The accumulated dose of ion implanting；
Six, carry out p-type ion implanting, so by template definition p-well region in the p-type epitaxial layer on the left of polysilicon gate
High temperature advances to form p-well afterwards；
Seven, define source N+ regions, in third time N-type ion implanting by reticle in p-well on the left of polysilicon gate
Region right-hand member defines drain terminal N+ regions, and substrate terminal P+ regions are defined in p-well on the left of source N+ regions, in source N+ areas
Domain, drain terminal N+ regions injection N-type impurity；In substrate terminal P+ regions implanting p-type impurity；
Eight, remove photoresist, and one layer of dielectric layer is deposited on silicon chip；
Nine, deposit a metal level on dielectric layer, and by template definition, etching forms faraday shield layer, faraday screen
The bottom of layer is covered for Faraday shield dielectric layer, and top is Faraday shield metal level, and the left part of faraday shield layer is in polycrystalline
The top of Si-gate right part, the right-hand member of Faraday shield metal level is above third time N-type ion implanted regions left part；Faraday screen
The left part for covering layer is higher than right part；
Ten, define position and the size of polysilicon plug or metal closures by template in substrate terminal P+ regions, are etched to
P type substrate, depositing polysilicon or metal, form polysilicon or metal closures.
The radio frequency horizontal dual pervasion field effect crystal that the preparation method of the radio frequency horizontal dual pervasion field effect transistor makes
Pipe, growing P-type epitaxial layer in P type substrate, p-type epitaxial layer middle part top is sequentially formed with grid oxygen and polysilicon gate；
P-well is formed in the p-type epitaxial layer of polysilicon gate lower-left, N-type is formed in the p-type epitaxial layer of polysilicon gate bottom right
Drift region；
The N-type drift region, is from left to right divided into low depth area, middle depth area, high depth area, and low depth area is located at polycrystalline
Si-gate right part lower section, the segment distance of polysilicon gate right-hand member one is left in high depth area；
Polysilicon gate right part and N-type drift region left part top form Faraday shield oxide layer and Faraday shield metal
Layer；
P-well on the left of adjacent polysilicon gate forms source heavy N-type area；
Drain terminal heavy N-type area is formed on N-type drift region right-hand member；
The source heavy N-type area left side forms weight p type island region；
In the heavy p type island region and p-type polysilicon formed below or metal connector, by outside the heavy p type island region, p-well, P
Prolong layer and substrate P is drawn.
The preparation method of radio frequency horizontal dual pervasion field effect transistor of the invention, drift region is using three N-type ion notes
Enter to be formed N type junction structure heterogeneous, first time N-type ion implanting is a self-aligned vertical injection for low dosage medium energy,
Second N-type ion implanting is an autoregistration oblique angle injection for low dosage low energy, is then being left by template definition again
Position in the drift region of the segment distance of polysilicon gate one carries out third time N-type ion implanting.Radio frequency transverse direction double diffusion of the invention
The preparation method of field-effect transistor, the drift region of the device of making is non-uniform doping structure, in the oxidation of thick Faraday shield
Under conditions of layer, output capacitance (Coss) is reduced, increase a photoetching and ion implanting can just improve the heat of device twice
Carrier injectability (HCI) characteristic and robustness (Ruggedness).
Brief description of the drawings
In order to illustrate more clearly of technical scheme, simple is made to the accompanying drawing used required for the present invention below
Introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill people
For member, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the structure of existing RFLDMOS；
Fig. 2 be radio frequency horizontal dual pervasion field effect transistor of the present invention the embodiment epitaxial layer of preparation method one formed after
Device sectional view；
Fig. 3 is one embodiment of preparation method, second N-type ion of radio frequency horizontal dual pervasion field effect transistor of the present invention
Device sectional view after injection；
Fig. 4 is the embodiment third time N-type ion of preparation method one of radio frequency horizontal dual pervasion field effect transistor of the present invention
Device sectional view after injection；
Fig. 5 is the sectional view of the embodiment of radio frequency horizontal dual pervasion field effect transistor one of the present invention；
Fig. 6 is the sectional view of common thin Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor；
Fig. 7 is the sectional view of common thick Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor；
Fig. 8 is the sectional view of thin Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor of the invention；
Fig. 9 is the sectional view of thick Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor of the invention；
The drift region surface electric field distribution curve that it is four kinds of frequency horizontal dual pervasion field effect transistors when puncturing that Figure 10 is
Figure；
Figure 11 is the CV curve maps of four kinds of radio frequency horizontal dual pervasion field effect transistors；
Figure 12 is two kinds of transfer characteristic curves of device when drain voltage is 0.1V；
Figure 13 is two kinds of transfer characteristic curves of device when drain voltage is 28V.
Specific embodiment
Below in conjunction with accompanying drawing, clear, complete description is carried out to the technical scheme in the present invention, it is clear that described
Embodiment is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is general
All other embodiment that logical technical staff is obtained on the premise of creative work is not made, belongs to protection of the present invention
Scope.
Embodiment one
The preparation method of radio frequency horizontal dual pervasion field effect transistor, comprises the following steps：
One, grows on heavily doped P-type substrate 101 and p-type epitaxial layer 102 is lightly doped, as shown in Figure 2；
Two, oxide layers 201 of thermal oxide growth one on p-type epitaxial layer 102, then deposit one layer of polysilicon 202, in
Portion's chemical wet etching goes out polysilicon gate；
Three, retain the photoresist 203 above polysilicon gate, carry out first time N-type ion implanting 301, first time N-type ion
Injection is self-aligned vertical injection；
Four, retain the photoresist 203 above polysilicon gate, carry out second N-type ion implanting 302, second N-type ion
Injection is the injection of autoregistration oblique angle, second N-type ion implanting depth ratio first time N-type ion implanting depth as shallow, such as Fig. 3 institutes
Show；
Five, define third time N-type ion implanted regions 401 by photolithography plate, third time N-type ion implanted regions, be from
Open the p-type epitaxial layer 102 of polysilicon gate right side certain distance；N-type ion is injected in third time N-type ion implanted regions 401, such as
Shown in Fig. 4, third time N-type ion implanting depth more than or equal to for the first time and second N-type ion implanting depth, dosage less than etc.
In first time and second accumulated dose of N-type ion implanting；
Six, carry out p-type ion implanting by template definition p-well region in the p-type epitaxial layer in the left side of polysilicon gate 202,
Then high temperature advances to form p-well 501, as shown in Figure 5；
Seven, define source N+ regions 603, in third time N by reticle in the left side p-well 501 of polysilicon gate 202
The right-hand member of type ion implanted regions 401 defines drain terminal N+ regions 601, and lining is defined in the left side p-well 501 of source N+ regions 603
Bottom P+ regions 602, in source N+ regions 603, the injection of drain terminal N+ regions 601 N-type impurity；P is injected in substrate terminal P+ regions 602
Type impurity；
Eight, remove photoresist, and one layer of dielectric layer is deposited on silicon chip；
Nine, deposit a metal level on dielectric layer, and by template definition, etching forms faraday shield layer, faraday screen
The bottom of layer is covered for Faraday shield dielectric layer, and top is Faraday shield metal level, and the left part of faraday shield layer is in polycrystalline
The top of Si-gate right part, the right-hand member of Faraday shield metal level is above third time N-type ion implanted regions left part；Faraday screen
The left part for covering layer is higher than right part；
Ten, define position and the size of polysilicon plug or metal closures by template in substrate terminal P+ regions, are etched to
P type substrate, depositing polysilicon or metal, form polysilicon or metal closures 801, as shown in Figure 5.
Preferably, described be lightly doped p-type epitaxial layer, bulk concentration is 1e14~1e16/cm3, thickness is 1~10um.
Preferably, the impurity of first time N-type ion implanting is phosphorus or arsenic, energy is 50~200keV, and dosage is 1e12
~1e13/cm2。
Preferably, second implant angle of N-type ion implanting is 2 °~45 °, impurity is phosphorus or arsenic, energy is 30~
100keV, dosage is 1e12~1e13/cm2。
Preferably, the distance that third time N-type ion implanted regions 401 leave on the right side of polysilicon gate is 0.1~1.5um, the
Three impurity of N-type ion implanting are phosphorus or arsenic, and energy is 100~500keV, and dosage is 1e12~5e12/cm2。
Preferably, the impurity of p-well region injection is boron, energy is 30~300keV, and dosage is 1e12~2e14/cm2。
Preferably, injection source N+ regions and drain terminal N+ regions N-type impurity be phosphorus or arsenic, energy be 0keV~
200keV, dosage is 1013~1016/cm2.The p type impurity in injection substrate terminal P+ regions is boron or boron difluoride, and energy is
0keV~100keV, dosage is 1013~1016/cm2。
Preferably, the dielectric layer deposited in step 8 is silica, thickness is 500 angstroms~2000 angstroms.
The preparation method of the radio frequency horizontal dual pervasion field effect transistor of embodiment one, in thick Faraday shield oxide layer
In the case of, in order to improve the hot carrier in jection ability (HCI) and robustness of the difference brought therewith, its drift region uses three N
Type ion implanting forms N type junction structure heterogeneous, and first time N-type ion implanting is that an autoregistration for low dosage medium energy is hung down
Straight injection, second N-type ion implanting is an autoregistration oblique angle injection for low dosage low energy, then fixed by template again
Justice, the position in the drift region for leaving the segment distance of polysilicon gate one carries out third time N-type ion implanting, third time N-type ion
Injection can encase drain terminal N-type heavily doped region, or stand away.The effect of second N-type ion is to increase N-type region domain
With overlapping for polysilicon gate, second N-type ion implanting depth ratio first time N-type ion implanting depth as shallow so that N-type ion point
Cloth is more uniform, so as to reduce polysilicon gate lower section electric-field intensity, plays a part of to suppress hot carrier in jection (HCI).First
Secondary and second N-type ion implanting accumulated dose is too high, can influence the breakdown voltage (BV) of device, or causes hot carrier in jection
Effect becomes strong, so as to influence the service life of device.First time and second N-type ion accumulated dose are too low, or its injection is deep
Depth is spent, then influences the current driving ability of device, cause conducting resistance (Rdson) to increase, and saturation current (Idsat) drop
It is low.Third time N-type ion implanting is located too close to polysilicon gate, and it is too strong to also result in its fringe field, so as to influence device
Breakdown voltage (BV), or hot carrier in jection ability (HCI), third time N-type ion implanting position from polysilicon gate too away from, then
Influence the current driving ability of device.Third time N-type ion implanting depth cannot be below first time and second N-type ion implanting
Depth, its dosage also should not be higher than first time and second accumulated dose of N-type ion implanting, deeper and thin third time N-type
Ion implanting, helps to reduce output capacitance (Coss).The concentration of the N-type ion superposition that drift region is three times is denseer, it is possible to increase
The current driving ability of device so that conducting resistance declines, saturation current is improved.
The preparation method of the radio frequency horizontal dual pervasion field effect transistor of embodiment one, the drift region of the device of making is non-
Uniform Doped structure, under conditions of thick Faraday shield oxide layer, reduces output capacitance (Coss), increase a photoetching and
Ion implanting can just improve hot carrier in jection ability (HCI) characteristic and robustness (Ruggedness) of device twice.
Embodiment two
Radio frequency horizontal dual pervasion field effect transistor, as shown in figure 5, growing P-type epitaxial layer 102, p-type in P type substrate 101
The middle part of epitaxial layer 102 top is sequentially formed with grid oxygen 201 and polysilicon gate 202；
P-well 501 is formed in the p-type epitaxial layer of the lower-left of polysilicon gate 202, in the p-type epitaxial layer of the bottom right of polysilicon gate 202
Middle formation N-type drift region；
The N-type drift region, is from left to right divided into low depth area, middle depth area, high depth area, and low depth area is located at polycrystalline
Si-gate right part lower section, the segment distance of 202 right-hand member of polysilicon gate one is left in high depth area；
The right part of polysilicon gate 202 and N-type drift region left part top form Faraday shield oxide layer with Faraday shield gold
Category layer；
P-well 501 on the left of adjacent polysilicon gate forms source heavy N-type area 603；
Drain terminal heavy N-type area 601 is formed on N-type drift region right-hand member；
The source heavy N-type area left side forms weight p type island region；
In the heavy p type island region and p-type polysilicon formed below or metal connector 801, by the heavy p type island region, p-well, P
Epitaxial layer and substrate P are drawn.
Preferably, the one 0.1~1.5um of right-hand member of polysilicon gate 202 is left in the high depth area of the N-type drift region.
The radio frequency horizontal dual pervasion field effect transistor of embodiment two, p-well is used to form raceway groove, and drift region is mixed for non-homogeneous
Miscellaneous structure, under conditions of thick Faraday shield oxide layer, reduces output capacitance (Coss), and hot carrier in jection ability
(HCI) characteristic and robustness (Ruggedness) are strong.
The radio frequency horizontal dual pervasion field effect transistor of embodiment two is emulated using TCAD simulation softwares, Fig. 6
It is the sectional view of common thin Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor；Fig. 7 is common thick method
Draw the sectional view of screen oxide radio frequency horizontal dual pervasion field effect transistor；Fig. 8 is thin Faraday shield oxygen of the invention
Change the sectional view of layer radio frequency horizontal dual pervasion field effect transistor；Fig. 9 is that thick Faraday shield oxide layer radio frequency of the invention is horizontal
To the sectional view of bilateral diffusion field-effect tranisistor.
Drift region surface electric field distribution curve map of the four kinds of radio frequency horizontal dual pervasion field effect transistors when puncturing is such as
Shown in Figure 10, wherein first peak value is polysilicon gate edge lower section electric field, second peak value is Faraday shield metal level side
Edge lower section electric field, although having thickeied Faraday shield oxide layer can reduce output capacitance, but thick Faraday shield oxide layer
Device can bring polysilicon gate lower section have stronger electric-field intensity, so as to influence the breakdown voltage (BV) of device, Huo Zhere
Carrier injectability (HCI).The radio frequency horizontal dual pervasion field effect transistor of embodiment two, relative to common thin faraday
Screen oxide radio frequency horizontal dual pervasion field effect transistor, polysilicon gate lower section electric field than relatively low, therefore, it is possible to improve heat resistanceheat resistant
Carrier injects (HCI) effect, and can suppress parasitic triode ON, so as to improve the reliability of device.
Figure 11 is the CV curve maps of four kinds of radio frequency horizontal dual pervasion field effect transistors, it can be seen that commonly
Thickening Faraday shield oxide layer radio frequency horizontal dual pervasion field effect transistor, relative to the radio frequency transverse direction of general thickness
Bilateral diffusion field-effect tranisistor, its output capacitance decreases；The embodiment two of the Faraday shield oxide layer of same thickness
Radio frequency horizontal dual pervasion field effect transistor, relative to common radio frequency horizontal dual pervasion field effect transistor, its output capacitance
Decrease.Therefore, the radio frequency horizontal dual pervasion field effect transistor for thickening the embodiment two of faraday's screen oxide can
Obtain minimum output capacitance.
Figure 12, Figure 13 are two kinds of transfer characteristic curves of device, it can be seen that thickening faraday's screen oxide
Embodiment two radio frequency horizontal dual pervasion field effect transistor, its linear current and saturation current be relative to common radio frequency
Horizontal dual pervasion field effect transistor, is greatly improved.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (8)
1. a kind of preparation method of radio frequency horizontal dual pervasion field effect transistor, it is characterised in that comprise the following steps：
One, growing P-type epitaxial layers in P type substrate, the doping concentration of p-type epitaxial layer is lower than P type substrate；
Two, oxide layers of thermal oxide growth one on p-type epitaxial layer, then deposit one layer of polysilicon, and photoetching is carved in the middle part of silicon chip
Lose polysilicon gate；
Three, retain the photoresist above polysilicon gate, carry out first time N-type ion implanting, and first time N-type ion implanting is from right
Quasi- vertical injection；
Four, retain the photoresist above polysilicon gate, carry out second N-type ion implanting, and second N-type ion implanting is from right
Quasi- oblique angle injection, second N-type ion implanting depth ratio first time N-type ion implanting depth as shallow；
Five, define third time N-type ion implanted regions, third time N-type ion implanted regions, to leave polysilicon by photolithography plate
The p-type epitaxial layer of grid right side certain distance；N-type ion, third time N-type ion note are injected in third time N-type ion implanted regions
Enter depth more than or equal to first time and second N-type ion implanting depth, dosage is less than or equal to first time and second N-type ion
The accumulated dose of injection；
Six, carry out p-type ion implanting, Ran Hougao by template definition p-well region in the p-type epitaxial layer on the left of polysilicon gate
Temperature propulsion forms p-well；
Seven, define source N+ regions, in third time N-type ion implanted regions by reticle in p-well on the left of polysilicon gate
Right-hand member defines drain terminal N+ regions, and substrate terminal P+ regions are defined in p-well on the left of source N+ regions, in source N+ regions, leakage
End N+ regions injection N-type impurity；In substrate terminal P+ regions implanting p-type impurity；
Eight, remove photoresist, and one layer of dielectric layer is deposited on silicon chip；
Nine, deposit a metal level on dielectric layer, and by template definition, etching forms faraday shield layer, faraday shield layer
Bottom be Faraday shield dielectric layer, top be Faraday shield metal level, the left part of faraday shield layer is in polysilicon gate
The top of right part, the right-hand member of Faraday shield metal level is above third time N-type ion implanted regions left part；Faraday shield layer
Left part be higher than right part；
Ten, define position and the size of polysilicon plug or metal closures by template in substrate terminal P+ regions, are etched to p-type
Substrate, depositing polysilicon or metal, form polysilicon or metal closures.
2. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
The p-type epitaxial layer, bulk concentration is 1e14~1e16/cm3, thickness is 1~10um.
3. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
The impurity of first time N-type ion implanting is phosphorus or arsenic, and energy is 50~200keV, and dosage is 1e12~1e13/cm2。
4. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
Second implant angle of N-type ion implanting is 2 °~45 °, and impurity is phosphorus or arsenic, and energy is 30~100keV, dosage
It is 1e12~1e13/cm2。
5. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
Third time N-type ion implanted regions, leave the distance on the right side of polysilicon gate for 0.1~1.5um, third time N-type ion note
The impurity for entering is phosphorus or arsenic, and energy is 100~500keV, and dosage is 1e12~5e12/cm2。
6. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
The impurity of p-well region injection is boron, and Implantation Energy is 30~300keV, and dosage is 1e12~2e14/cm2。
7. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
The N-type impurity in injection source N+ regions and drain terminal N+ regions is phosphorus or arsenic, and energy is 0keV~200keV, and dosage is 1013
~1016/cm2；
The p type impurity in injection substrate terminal P+ regions is boron or boron difluoride, and energy is 0keV~100keV, and dosage is 1013~
1016/cm2。
8. the preparation method of radio frequency horizontal dual pervasion field effect transistor according to claim 1, it is characterised in that
The dielectric layer deposited in step 8 is silica, and thickness is 500 angstroms~2000 angstroms.
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| CN103035681A (en) * | 2012-08-13 | 2013-04-10 | 上海华虹Nec电子有限公司 | Radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component and manufacture method |
| CN103050532A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
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| CN103035681A (en) * | 2012-08-13 | 2013-04-10 | 上海华虹Nec电子有限公司 | Radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component and manufacture method |
| CN103050532A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
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