CN111863608B - High-power transistor resistant to single particle burning and manufacturing method thereof - Google Patents
High-power transistor resistant to single particle burning and manufacturing method thereof Download PDFInfo
- Publication number
- CN111863608B CN111863608B CN202010735726.5A CN202010735726A CN111863608B CN 111863608 B CN111863608 B CN 111863608B CN 202010735726 A CN202010735726 A CN 202010735726A CN 111863608 B CN111863608 B CN 111863608B
- Authority
- CN
- China
- Prior art keywords
- epitaxial layer
- ion implantation
- heavy metal
- power transistor
- resistant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002245 particle Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 62
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 55
- 238000002513 implantation Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 238000011282 treatment Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000002360 preparation method Methods 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 40
- -1 gold ion Chemical class 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 claims description 3
- 229910001431 copper ion Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 235000012489 doughnuts Nutrition 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 16
- 230000008569 process Effects 0.000 abstract description 11
- 230000006798 recombination Effects 0.000 abstract description 8
- 238000005215 recombination Methods 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a high-power transistor resistant to single particle burning and a preparation method thereof. The preparation method of the high-power transistor comprises the following steps: providing a substrate and forming an epitaxial layer on the substrate; performing oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window; and carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation region formed by the heavy metal ion implantation at the last time is positioned above an ion implantation region formed by the heavy metal ion implantation at the previous time. According to the invention, the epitaxial layer is subjected to multiple heavy metal ion injections, so that the recombination rate of electron hole pairs induced by the radiation of the epitaxial layer is increased, the charge collection efficiency under a high electric field is reduced, the single particle burnout resistance of the transistor is improved, and the high performance index of the transistor can be ensured. In addition, the method is compatible with the conventional transistor preparation method in process, and is simple in steps and easy to operate.
Description
Technical Field
The invention relates to the technical field of electronic devices, in particular to a high-power transistor resistant to single particle burnout and a preparation method thereof.
Background
Power devices are a type of electronic device that is widely used in a radiating environment. However, as the power device has multiple types of materials and complex structures, various complex radiation damage effects such as a single event effect, an ionization effect, a displacement effect, an ionization/displacement synergistic effect and the like can be generated under the action of a radiation environment, so that the power device becomes a damage sensitive part of an equipment electronic system, and the service life and the reliability of the equipment are further affected.
For many years, attention has been paid to how to effectively improve the single-particle burnout resistance of a high-power transistor in a radiation environment, and currently, radiation-resistant reinforcement measures are performed on the transistor, wherein the improvement degree of the single-particle burnout resistance is limited, and the performance index of the transistor is reduced to a certain extent.
Disclosure of Invention
The invention solves the problem of effectively improving the single particle burning resistance of the high-power transistor in the radiation environment and ensuring the performance index of the high-power transistor.
In order to solve at least one aspect of the above problems, the present invention provides a method for manufacturing a high-power transistor resistant to single particle burnout, including:
providing a substrate and forming an epitaxial layer on the substrate;
performing oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
and carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation region formed by the heavy metal ion implantation at the last time is positioned above an ion implantation region formed by the heavy metal ion implantation at the previous time.
Preferably, the number of times of implantation of the heavy metal ions is 3-5.
Preferably, a plurality of layers of the ion implantation regions are formed in the epitaxial layer, the ion implantation regions are distributed at intervals along the depth direction of the epitaxial layer, and the distance between adjacent ion implantation regions is 1-3 μm.
Preferably, the concentration of the heavy metal ions injected each time is 1e17cm -2 -1e20cm -2 。
Preferably, the distribution form of the heavy metal ions in the epitaxial layer is conical, cylindrical, square or cuboid.
Preferably, the cross-sectional shape of the ion implantation region is circular, annular, rectangular, square or trapezoid.
Preferably, the oxidizing the epitaxial layer includes: oxidizing oxygen at the surface of the epitaxial layer remote from the substrateA chemical layer, the thickness of the oxide layer is 0.1 μm-3 μm, wherein the oxidation atmosphere is N 2 、O 2 And H 2 At least one of the components is oxidized at 800-1300 ℃ for 2-200 min.
Preferably, the heavy metal ions include at least one of gold ions, copper ions, and platinum ions.
Compared with the prior art, the preparation method of the high-power transistor resistant to single particle burning has the following beneficial effects:
according to the invention, the epitaxial layer is subjected to multiple heavy metal ion injections, and the heavy metal ion impurities are deep energy level impurities, so that a recombination center can be generated, the recombination rate of electron hole pairs induced by the radiation of the epitaxial layer is further increased, the collection efficiency of charges under a high electric field is reduced, and the instant high current generated by incident high-energy particles in the transistor is led out of the power device, so that the single particle burnout resistance of the high-power transistor is improved, and the high performance index of the transistor can be ensured. In addition, the method is compatible with the conventional transistor preparation method in process, and is simple in steps and easy to operate.
The invention also provides a high-power transistor resistant to single particle burning, which is manufactured by adopting the preparation method of the high-power transistor resistant to single particle burning.
Preferably, the semiconductor device comprises a substrate, an epitaxial layer formed on the substrate and a plurality of layers of ion implantation areas formed in the epitaxial layer and distributed at intervals along the depth direction of the epitaxial layer, wherein ions implanted in the ion implantation areas are heavy metal ions.
Compared with the prior art, the high-power transistor resistant to single particle burning has the advantages that the preparation method is the same as that of the high-power transistor resistant to single particle burning, and the preparation method is not repeated here.
Drawings
FIG. 1 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which the surface of an epitaxial layer is subjected to a primary oxidation treatment;
FIG. 2 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which a photolithography process is performed on the surface of an epitaxial layer;
fig. 3 is a schematic cross-sectional structure diagram of a high-power transistor according to an embodiment of the present invention, in which heavy metal ions are injected into an epitaxial layer thereof at one time;
FIG. 4 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which the surface of an epitaxial layer is subjected to a secondary oxidation treatment;
FIG. 5 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which the surface of an epitaxial layer is subjected to a secondary photolithography process;
fig. 6 is a schematic cross-sectional structure diagram of a high-power transistor according to an embodiment of the present invention, in which heavy metal ions are secondarily injected into an epitaxial layer thereof;
FIG. 7 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which the surface of an epitaxial layer is oxidized three times;
FIG. 8 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which the surface of an epitaxial layer is subjected to three photolithography processes;
fig. 9 is a schematic cross-sectional structure diagram of a high-power transistor according to an embodiment of the present invention, in which heavy metal ions are implanted three times in an epitaxial layer thereof;
fig. 10 is a schematic cross-sectional structure diagram of a high-power transistor according to an embodiment of the present invention, in which four oxidation treatments are performed on the surface of an epitaxial layer thereof;
fig. 11 is a schematic cross-sectional structure of a high-power transistor according to an embodiment of the present invention, in which four photolithography processes are performed on the surface of an epitaxial layer.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
The embodiment of the invention provides a preparation method of a high-power transistor resistant to single particle burning, which comprises the following steps:
step 1, providing a substrate and forming an epitaxial layer on the substrate;
step 2, performing oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
and 3, carrying out heavy metal ion implantation on the epitaxial layer for a plurality of times through the implantation window, wherein an ion implantation region formed by the heavy metal ion implantation at the last time is positioned above an ion implantation region formed by the heavy metal ion implantation at the previous time, wherein the vertical direction refers to the depth direction of the epitaxial layer, namely the position of the ion implantation region formed by the heavy metal ion implantation at the last time in the epitaxial layer is shallower than the ion implantation region formed by the heavy metal ion implantation at the previous time.
It should be understood that the oxidation and photolithography treatment is performed before each implantation of the heavy metal ions, that is, the step 2 is returned, and the heavy metal ions are implanted after the implantation window is etched.
Under the radiation environment, the power device can generate various complex radiation loss effects, such as a single particle burning effect. When the heavy metal ion impurities enter the epitaxial layer, new defect energy levels are generated in the energy band of the epitaxial layer semiconductor, a large number of defect energy levels become the recombination centers of electron hole pairs, the energy levels are deep energy levels near the center of a forbidden band, the energy levels are effective recombination centers, the recombination effect is achieved on electrons and holes generated by radiation induction, the collection influence of charges is reduced, the irradiation current is reduced, and instantaneous heavy current generated in the device by high-energy particles incident in space is led out. The high performance index of the high-power device is guaranteed, the single particle burning resistance of the power device can be effectively improved, and the purpose of slowing down radiation damage of the power device is achieved.
Wherein, the heavy metal ions comprise at least one of gold ions (Au), copper ions (Cu), platinum ions (Pt) and the like, and the heavy metal ions are used as common metals in the manufacture of semiconductor devices and have good process compatibility with the manufacturing process of the semiconductor devices.
According to the embodiment, the epitaxial layer is subjected to multiple heavy metal ion injections, so that the recombination rate of electron hole pairs induced by the radiation of the epitaxial layer is effectively increased, the collection efficiency of charges under a high electric field is reduced, and the single particle burning resistance of the power device is effectively improved. And the method is compatible with the conventional preparation method of the power device, has simple steps and is easy to operate. The high-power transistor device prepared by the method provided by the embodiment can greatly improve the radiation resistance of the transistor, has great significance for ground simulation application and research of materials and device space and nuclear radiation environmental effects, and has obvious advantages in space and nuclear radiation environmental effect research and radiation resistance reinforcement technology application.
Further, the substrate provided in this embodiment may be N-type or P-type, as shown in fig. 1, an N-type epitaxial layer is grown on the N-type substrate, oxidation treatment is performed on the surface of the N-type epitaxial layer, an oxide layer is grown, the thickness of the oxide layer is 0.1 μm-3 μm, the oxide layer growth method includes one of dry oxygen, wet oxygen and dry/wet oxygen mixing method, and the oxidation atmosphere is N 2 、O 2 And H 2 At least one of the components is oxidized at 800-1300 ℃ for 2-200 min.
As shown in fig. 2, the surface of the oxide layer is subjected to photolithography, and an implantation window is etched, wherein the center of the implantation window is aligned to the center of the epitaxial layer, and the etching mode can be dry etching, wet etching or plasma etching.
As shown in fig. 3, the epitaxial layer is subjected to multiple heavy metal ion implantations through the implantation window, and a multi-layer ion implantation region is formed in the epitaxial layer. In this embodiment, the number of times of heavy metal ion implantation is 3-5, and it should be noted that oxidation and photolithography treatment are performed on the epitaxial layer before each time of heavy metal ion implantation, and multiple layers of ion implantation regions are formed in the epitaxial layer at intervals along the depth direction of the epitaxial layer according to the number of times of heavy metal ion implantation, and the distance between two adjacent layers of ion implantation regions is 1 μm-3 μm. The heavy metal ion impurities injected in the ion implantation region generate new defect energy levels in the epitaxial layer, and form a recombination center of electron hole pairs so as to reduce charge collection efficiency.
Preferably, the concentration of heavy metal ions injected each time is 1e17cm -2 -1e20cm -2 Of course, it can be smaller than 1e17cm -2 Or greater than 1e20cm -2 This is mainly related to the type of device, for which the current is relatively large, the amount of implantation or diffusion per time is relatively large, for devicesIn the case of devices with relatively small current, the amount of implantation or diffusion per time is relatively small, but this embodiment only gives that the amount of implantation or diffusion per time is 1e17cm for most devices -2 -1e20cm -2 。
The epitaxial layer comprises a plurality of layers of ion implantation regions arranged along the depth direction, and the cross section of each layer of ion implantation region can be round, circular, rectangular, square or trapezoidal. The overall distribution form of the heavy metal ion impurities in the epitaxial layer can be conical, cylindrical, square or cuboid, for example, the cross section of each layer of ion implantation area is circular, and the cross section area of each layer of ion implantation area is equal, so that the heavy metal ion impurities are in cylindrical distribution in the epitaxial layer. If the cross-sectional shape of each layer of ion implantation region is circular, but the cross-sectional area of the ion implantation region gradually decreases from one side close to the substrate to one side far away from the substrate, the heavy metal ion impurities are distributed in a conical shape in the epitaxial layer, wherein the size of the cross-sectional area of the ion implantation region can be controlled by changing the size of the implantation window. The distribution form of heavy metal ion impurities in the epitaxial layer can be changed by adjusting the energy of the injected heavy metal ions.
The following detailed description will proceed with reference to specific embodiments.
Example 1
As shown in FIG. 1, after an N-type epitaxial layer is formed on an N-type substrate, a single oxidation treatment is performed on the upper surface of the epitaxial layer to grow an oxide layer in an oxidizing atmosphere of N 2 The oxidation temperature is 1300 ℃, the oxidation time is 40min, the oxide layer grows in a dry oxygen mode, and the thickness of the grown oxide layer is 50nm;
as shown in fig. 2, performing a photolithography process on the surface of the oxide layer to etch a first injection window, wherein the cross-sectional area of the first injection window is 4/5 of that of the epitaxial layer, and the etching mode is dry etching;
as shown in FIG. 3, the first heavy metal ion impurity implantation is performed through the first implantation window, the implanted heavy metal ion is Au, the implantation position is positioned at the bottom of the epitaxial layer, and the implantation concentration is 1e18cm -2 Forming a first ion implantation region in the epitaxial layer;
as shown in fig. 4, the upper surface of the epitaxial layer is subjected to a secondary oxidation treatment in the same manner as the primary oxidation treatment;
as shown in fig. 5, performing a second lithography process on the surface of the oxide layer, etching a second implantation window, wherein the cross-sectional area of the second implantation window is 3/5 of the area of the epitaxial layer, and the etching mode is the same as that of the first lithography process;
as shown in fig. 6, the second heavy metal ion impurity implantation is performed through the second implantation window, the implantation position is 1 μm away from the first ion implantation region, the type and concentration of the implanted ions are the same as those of the first implantation, a second ion implantation region is formed in the epitaxial layer, and the second ion implantation region is located above the first ion implantation region;
as shown in fig. 7, three oxidation treatments are performed on the upper surface of the epitaxial layer, and the oxidation mode is the same as the primary oxidation mode;
as shown in fig. 8, three times of photoetching treatment are performed on the surface of the oxide layer, a third injection window is etched, the cross-sectional area of the third injection window is 2/5 of the area of the epitaxial layer, and the etching mode is the same as that of one time of photoetching treatment;
as shown in fig. 9, the third heavy metal ion impurity implantation is performed through the third implantation window, the implantation position is 1 μm away from the second ion implantation region, the type and concentration of the implanted ions are the same as those of the first implantation, a third ion implantation region is formed in the epitaxial layer, and the third ion implantation region is located above the second ion implantation region;
as shown in fig. 10, four times of oxidation treatment are performed on the upper surface of the epitaxial layer, and the oxidation mode is the same as the primary oxidation mode;
as shown in fig. 11, four photolithography processes are performed on the oxide layer surface, and the entire upper surface of the epitaxial layer is exposed by etching.
Example 2
This embodiment is different from embodiment 1 in that the number of times of metal ion implantation is 5.
Example 3
This example is different from example 1 in that the concentration of the heavy metal ions implanted is 1e20cm -2 。
Example 4
This example is different from example 1 in that the concentration of the heavy metal ion implanted is 1e17cm -2 。
Example 5
This example is different from example 1 in that the concentration of the heavy metal ions implanted is less than 1e17cm -2 。
Example 6
The present embodiment is different from embodiment 1 in that the ion implantation region formed by implanting heavy metal ions each time has the same sectional shape and sectional area.
Although the present disclosure is described above, the scope of protection of the present disclosure is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and these changes and modifications will fall within the scope of the invention.
Claims (9)
1. The preparation method of the high-power transistor resistant to single particle burning is characterized by comprising the following steps of:
providing a substrate and forming an epitaxial layer on the substrate;
performing oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation region formed by the heavy metal ion implantation at the last time is positioned above an ion implantation region formed by the heavy metal ion implantation at the previous time; the epitaxial layer is internally provided with a plurality of layers of ion implantation areas, the plurality of layers of ion implantation areas are distributed at intervals along the depth direction of the epitaxial layer, and the distance between every two adjacent ion implantation areas is 1 mu m-3 mu m.
2. The method for manufacturing a high-power transistor resistant to single particle burn-out according to claim 1, wherein the number of times of implantation of the heavy metal ions is 3-5.
3. The high power transistor of claim 1 that is resistant to single event burn outCharacterized in that the concentration of the heavy metal ions injected each time is 1e17cm -2 -1e20cm -2 。
4. The method for manufacturing a high-power transistor resistant to single particle burn-out according to claim 1, wherein the distribution form of the heavy metal ions in the epitaxial layer is conical, cylindrical, square or rectangular.
5. The method for manufacturing a high-power transistor resistant to single particle burn-out according to claim 1, wherein the cross-sectional shape of the ion implantation region is a circle, a doughnut, a rectangle, a square or a trapezoid.
6. The method for manufacturing a high power transistor resistant to single particle burn out according to any one of claims 1 to 5, wherein the oxidizing the epitaxial layer comprises: oxidizing the surface of the epitaxial layer far away from the substrate to form an oxide layer with the thickness of 0.1-3 mu m, wherein the oxidizing atmosphere is N 2 、O 2 And H 2 At least one of the components is oxidized at 800-1300 ℃ for 2-200 min.
7. The method for manufacturing a high-power transistor resistant to single particle burn out according to any one of claims 1 to 5, wherein the heavy metal ion includes at least one of gold ion, copper ion and platinum ion.
8. A high-power transistor resistant to single-particle burn-out, characterized in that the high-power transistor resistant to single-particle burn-out is manufactured by adopting the manufacturing method of the high-power transistor resistant to single-particle burn-out as claimed in any one of claims 1 to 7.
9. The high-power transistor of claim 8, comprising a substrate, an epitaxial layer formed on the substrate, and a plurality of layers of ion implantation regions formed in the epitaxial layer and spaced apart along the depth of the epitaxial layer, wherein the ions implanted in the ion implantation regions are heavy metal ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010735726.5A CN111863608B (en) | 2020-07-28 | 2020-07-28 | High-power transistor resistant to single particle burning and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010735726.5A CN111863608B (en) | 2020-07-28 | 2020-07-28 | High-power transistor resistant to single particle burning and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111863608A CN111863608A (en) | 2020-10-30 |
| CN111863608B true CN111863608B (en) | 2023-05-19 |
Family
ID=72947789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010735726.5A Active CN111863608B (en) | 2020-07-28 | 2020-07-28 | High-power transistor resistant to single particle burning and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111863608B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049238A (en) * | 1998-07-29 | 2000-02-18 | Oki Electric Ind Co Ltd | Manufacture of non-volatile semiconductor storage device |
| CN101916724A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for manufacturing transistor |
| WO2011066746A1 (en) * | 2009-12-04 | 2011-06-09 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| JP2012089560A (en) * | 2010-10-15 | 2012-05-10 | Fuji Electric Co Ltd | Method of manufacturing inverse prevention type igbt equipped with inclined side surface |
| WO2013086902A1 (en) * | 2011-12-14 | 2013-06-20 | 中国科学院微电子研究所 | Method for improving irradiation resisting performance of soi structure |
| CN103928309A (en) * | 2014-04-21 | 2014-07-16 | 西安电子科技大学 | Method for manufacturing N-channel silicon carbide insulated gate bipolar transistor |
| CN109712873A (en) * | 2019-02-11 | 2019-05-03 | 哈尔滨工业大学 | Metal-oxide-semiconductor field effect transistor resist displacement Radiation Hardened method based on deep ion injection mode |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4181538A (en) * | 1978-09-26 | 1980-01-01 | The United States Of America As Represented By The United States Department Of Energy | Method for making defect-free zone by laser-annealing of doped silicon |
| US6198116B1 (en) * | 1998-04-14 | 2001-03-06 | The United States Of America As Represented By The Secretary Of The Air Force | Complementary heterostructure integrated single metal transistor fabrication method |
| JP2001196373A (en) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | Producing method for semiconductor device and semiconductor device |
| US7294563B2 (en) * | 2000-08-10 | 2007-11-13 | Applied Materials, Inc. | Semiconductor on insulator vertical transistor fabrication and doping process |
| JP3916386B2 (en) * | 2000-08-28 | 2007-05-16 | シャープ株式会社 | Semiconductor device manufacturing method and photolithography mask |
| KR20060096177A (en) * | 2003-10-29 | 2006-09-08 | 스미토모덴키고교가부시키가이샤 | Method of manufacturing n-type semiconductor diamond, and n-type semiconductor diamond |
| CN100570886C (en) * | 2007-12-28 | 2009-12-16 | 中国电子科技集团公司第五十五研究所 | Reduce the structure and the manufacture method of transistor extension electrode electric capacity |
| US9024344B2 (en) * | 2010-06-15 | 2015-05-05 | California Institute Of Technology | Surface passivation by quantum exclusion using multiple layers |
| US8877594B2 (en) * | 2011-11-14 | 2014-11-04 | Peking University | CMOS device for reducing radiation-induced charge collection and method for fabricating the same |
| CN102437087B (en) * | 2011-12-14 | 2015-02-18 | 中国科学院微电子研究所 | SOI structure with reinforced anti-irradiation performance and manufacturing method thereof |
| CN103887154B (en) * | 2014-04-04 | 2016-08-17 | 哈尔滨工业大学 | A kind of anti-ionizing radiation reinforcement means of bipolar device based on passivation layer ion implanting mode |
| CN104282763B (en) * | 2014-09-15 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Radio frequency horizontal dual pervasion field effect transistor preparation method |
| US10522349B2 (en) * | 2017-11-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Anti-reflective coating by ion implantation for lithography patterning |
| CN110112217A (en) * | 2019-04-15 | 2019-08-09 | 杭州电子科技大学 | Anti-single particle burns LDMOS device |
| CN111081761B (en) * | 2019-12-16 | 2022-05-03 | 电子科技大学 | Low-power-consumption transistor device with anti-radiation reinforcing structure and preparation method thereof |
-
2020
- 2020-07-28 CN CN202010735726.5A patent/CN111863608B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049238A (en) * | 1998-07-29 | 2000-02-18 | Oki Electric Ind Co Ltd | Manufacture of non-volatile semiconductor storage device |
| WO2011066746A1 (en) * | 2009-12-04 | 2011-06-09 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN101916724A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for manufacturing transistor |
| JP2012089560A (en) * | 2010-10-15 | 2012-05-10 | Fuji Electric Co Ltd | Method of manufacturing inverse prevention type igbt equipped with inclined side surface |
| WO2013086902A1 (en) * | 2011-12-14 | 2013-06-20 | 中国科学院微电子研究所 | Method for improving irradiation resisting performance of soi structure |
| CN103928309A (en) * | 2014-04-21 | 2014-07-16 | 西安电子科技大学 | Method for manufacturing N-channel silicon carbide insulated gate bipolar transistor |
| CN109712873A (en) * | 2019-02-11 | 2019-05-03 | 哈尔滨工业大学 | Metal-oxide-semiconductor field effect transistor resist displacement Radiation Hardened method based on deep ion injection mode |
Non-Patent Citations (1)
| Title |
|---|
| 半导体器件辐射效应及抗辐射加固;李致远;;现代电子技术(第19期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111863608A (en) | 2020-10-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102760791A (en) | Method for forming a doped region, solar cell and manufacturing method thereof | |
| CN106601826B (en) | Fast recovery diode and manufacturing method thereof | |
| CN111863606B (en) | Anti-radiation power transistor and preparation method thereof | |
| JPH0642542B2 (en) | High-voltage semiconductor device manufacturing method | |
| CN104617148B (en) | Isolated form NLDMOS device and its manufacture method | |
| CN111863608B (en) | High-power transistor resistant to single particle burning and manufacturing method thereof | |
| CN110828559A (en) | High early voltage transverse transistor structure and preparation method thereof | |
| CN114464667A (en) | Shielding gate trench MOSFET structure capable of optimizing terminal electric field and manufacturing method thereof | |
| CN110828560A (en) | Base region ring-doped anti-radiation transverse PNP transistor and preparation method thereof | |
| CN112054050B (en) | Transient voltage suppression diode structure and manufacturing method thereof | |
| CN115223868B (en) | High-voltage fast recovery diode and preparation method thereof | |
| CN111863941A (en) | Anti-radiation VDMOS device and preparation method thereof | |
| JP2012174783A (en) | Photodiode and photodiode array | |
| CN113013728B (en) | Vertical cavity surface emitting laser and ion implantation method | |
| CN106558624B (en) | Fast recovery diode and manufacturing method thereof | |
| CN111863607B (en) | Anti-radiation power transistor and preparation method thereof | |
| CN113540204A (en) | Preparation method of semiconductor device structure | |
| CN113540205A (en) | Semiconductor device structure | |
| CN107275391B (en) | Composite terminal structure for silicon carbide semiconductor power device and preparation method | |
| JP2016111174A (en) | Insulated gate bipolar transistor and method of manufacturing the same | |
| CN110246888A (en) | Super junction device structure and preparation method thereof | |
| CN114203829B (en) | FRD structure and manufacturing method and application thereof | |
| CN216980575U (en) | Fast recovery diode | |
| TWI725729B (en) | Diode structure and manufacturing method thereof | |
| CN114203830B (en) | FRD structure and manufacturing method and application thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |