CN104617148B - Isolated form NLDMOS device and its manufacture method - Google Patents
Isolated form NLDMOS device and its manufacture method Download PDFInfo
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- CN104617148B CN104617148B CN201510048190.9A CN201510048190A CN104617148B CN 104617148 B CN104617148 B CN 104617148B CN 201510048190 A CN201510048190 A CN 201510048190A CN 104617148 B CN104617148 B CN 104617148B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000005516 deep trap Effects 0.000 claims abstract description 106
- 238000002347 injection Methods 0.000 claims abstract description 68
- 239000007924 injection Substances 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 45
- 239000001301 oxygen Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 48
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 5
- 238000000605 extraction Methods 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- -1 aluminium) Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of isolated form NLDMOS device, two independent N-type deep traps are formed with P-type silicon substrate；Left N-type deep trap left part is formed with a p-well；Above p-well right part and above left N-type deep trap right part, gate oxide is formed with；Left N-type deep trap is with the P-type silicon substrate top between right N-type deep trap, and above right N-type deep trap left part, is formed with an oxygen；In P-type silicon substrate and right N-type deep trap below the oxygen of field, drift p-type injection region is formed with；Inter-level dielectric is covered in device surface；At on the left of the nearly right N-type deep trap in p-type of drifting about injection region, the drift region metal through inter-level dielectric, field oxygen and right N-type deep trap is connect；The drift region metal, has oxide layer isolation between right N-type deep trap.The invention also discloses the manufacture method of this kind of isolated form NLDMOS device.The present invention, when isolated form NLDMOS device drain terminal add AC signal by high voltage drop to low-voltage when, can realize that output current is no-delay.
Description
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of isolated form NLDMOS device and its manufacture method.
Background technology
LDMOS (LDMOS) is due to high pressure resistant, high current drive capability, extremely low power dissipation
And can with CMOS it is integrated the advantages of, be widely adopted at present in electric power management circuit.
Isolated form NLDMOS device, both with discrete device high-voltage great-current feature, has drawn low-voltage ic high again
The advantage of density intelligent logical control, single-chip realizes the function that original multiple chips could be completed, and greatly reduces area, drops
Low cost, improves efficiency, meets Modern Power Electronic Devices miniaturization, intelligent, the developing direction of low energy consumption.Breakdown potential
Pressure and conducting resistance are to weigh the key parameter of isolated form NLDMOS device.
A kind of existing isolated form NLDMOS (N-type LDMOS) device, cellular construction such as Fig. 1 institutes
Show, the independent N-type deep trap of left N-type deep trap 102a, right N-type deep trap 102b two is formed with P-type silicon substrate 101, and left N-type is deep
Trap 102a left parts are formed with p-well 104, and the left part of p-well 104 is formed with p-type heavily doped region 109 and source N-type heavily doped region 108a, P
The right part of trap 104, left N-type deep trap 102a upper right side are formed with gate oxide 106, left N-type deep trap 102a with right N-type deep trap 102b it
Between the top of P-type silicon substrate 101, and be formed with an oxygen 103, right N-type deep trap 102b right part shapes above right N-type deep trap 102b left parts
Into there is drain terminal N-type heavily doped region 108b, the left part of field oxygen 103 and the top of gate oxide 106 are formed with grid polycrystalline silicon 107a, field oxygen
Drain terminal polysilicon field plate 107b is formed with above 103 right parts, inter-level dielectric 110 is covered in device surface, p-type heavily doped region 109
And source N-type heavily doped region 108a is shorted together by a metal 111 of metal 111 through inter-level dielectric 110, drain terminal N-type
Heavily doped region 108b is shorted together with drain terminal polysilicon field plate 107b by another metal 111 through inter-level dielectric 110, field
It is formed with drift p-type injection region 105b, p-well 104 and is formed in the P-type silicon substrate 101 and right N-type deep trap 102b of the lower section of oxygen 103
There is a source p-type injection region 105a.
Isolated form NLDMOS device shown in Fig. 1, the drift p-type injection region 105b of its drift region injection can accelerate drift
Move area to exhaust, breakdown device voltage is increased (more than 700V can be reached).But, when drain terminal high voltage, drift region is complete
Exhaust, when drain terminal plus low-voltage, due to the drift p-type injection region 105b floatings of drift region, complete depletion of drift region
It can not recover immediately, therefore output current has delay, thus in actual applications, when drain terminal plus AC signal, output electricity
Stream has delay.
The content of the invention
The technical problem to be solved in the present invention is, isolated form NLDMOS device when drain terminal add AC signal by high voltage drop to
During low-voltage, realize that output current is no-delay.
In order to solve the above technical problems, the isolated form NLDMOS device that the present invention is provided, is formed with a left side in P-type silicon substrate
The independent N-type deep trap of N-type deep trap, right N-type deep trap two；
The left N-type deep trap, left part is formed with a p-well；
The p-well, left part is formed with a p-type heavily doped region and a source N-type heavily doped region；
Above the p-well right part and above the left N-type deep trap right part, gate oxide is formed with；
The left N-type deep trap is with above P-type silicon substrate between the right N-type deep trap, and on the right N-type deep trap left part
Side, is formed with an oxygen；
The right N-type deep trap, right part is formed with a drain terminal N-type heavily doped region；
Above the field oxygen left part and above the gate oxide, grid polycrystalline silicon is formed with；
In P-type silicon substrate and right N-type deep trap below the field oxygen, drift p-type injection region is formed with；
Inter-level dielectric is covered in device surface；
The p-type heavily doped region is with the source N-type heavily doped region, with the source metal connect through inter-level dielectric；
The drain terminal N-type heavily doped region, connects the drain terminal metal through inter-level dielectric；
At on the left of the nearly right N-type deep trap in drift p-type injection region, the drift through inter-level dielectric, field oxygen and right N-type deep trap is connect
Move area's metal；
The drift region metal, has oxide layer isolation between right N-type deep trap.
Preferably, being formed with drain terminal polysilicon field plate above the field oxygen right part；
The drain terminal N-type heavily doped region is with the drain terminal polysilicon field plate with the drain terminal metal connect through inter-level dielectric.
Preferably, P-type silicon substrate, p-well, drift p-type injection region, p-type heavily doped region, p-type doping concentration increase successively；
The n-type doping concentration of left N-type deep trap, right N-type deep trap, less than source N-type heavily doped region, drain terminal N-type heavily doped region
N-type doping concentration.
Preferably, being formed with a source p-type injection region in the p-well.
In order to solve the above technical problems, the manufacture method for the isolated form NLDMOS device that the present invention is provided, including following step
Suddenly：
It is deep that one, forms the independent N-type of left N-type deep trap, right N-type deep trap two in P-type silicon substrate by N-type ion implanting
Trap；
Two, utilize active area photoetching, open field oxygen region, etching Chang Yang areas, in left N-type deep trap between right N-type deep trap
P-type silicon substrate above, and above right N-type deep trap left part, raw long field oxide；
Trap injection zone is opened in three, photoetching, in left N-type deep trap left part implanting p-type ion formation p-well；
Four, carry out shape in P-type silicon substrate and right N-type deep trap below p-type ion implanting, oxygen on the scene below the field oxygen
Into there is drift p-type injection region；
Five, grow gate oxide, depositing polysilicon on substrate by thermal oxidation process；Then polysilicon gate quarter is carried out
Erosion, forms the grid polycrystalline silicon of isolated form NLDMOS device；
The grid polycrystalline silicon, it is left positioned at p-well right part top, the left N-type deep trap right part top and the field oxygen
Above portion；
The carry out source and drain ion implanting of six, selectivity, p-type heavily doped region and source N-type are formed in the p-well left part respectively
Heavily doped region, in the right N-type deep trap right part formation drain terminal N-type heavily doped region；
Seven, deposit inter-level dielectric on substrate；
Eight, etchings remove inter-level dielectric, field oxygen, the right N above on the left of the nearly right N-type deep trap in drift p-type injection region
Moldeed depth trap body silicon, forms an exit orifice for exposing drift p-type injection region；
9th, at the exit orifice of drift p-type injection region, oxide layer is grown；
Ten, selective etch, etch p-type heavily doped region and source N-type heavy doping contact hole, drain terminal N-type heavy doping
Area's contact hole, and drift p-type injection region contact hole；
The contact hole of the drift p-type injection region, the exit orifice with the drift p-type injection region is concentric, the drift p-type
The contact hole of injection region is isolated with there is annular oxide layer between the right N-type deep trap；
11, deposit metal, then etch required pattern, form the source and background region for drawing isolated form NLDMOS device
Source metal, draw the drain terminal metal of drain terminal, draw the drift region metal of drift p-type injection region, finally complete this NLDMOS
Making.
Preferably, in step 4, while carrying out p-type ion implanting in the p-well, a source is formed with the p-well
Hold p-type injection region.
Preferably, in step 4, the p-type ion of injection is boron ion, and Implantation Energy is 1000kev to 1500kev, injection
Dosage is 1E12 to 1E14 every square centimeter.
Preferably, in step 5, on substrate, gate oxide, depositing polysilicon are grown by thermal oxidation process；Then enter
Row polysilicon gate etching, forms the grid polycrystalline silicon and drain terminal polysilicon field plate of isolated form NLDMOS device；
The grid polycrystalline silicon, it is left positioned at p-well right part top, the left N-type deep trap right part top and the field oxygen
Above portion；
The drain terminal polysilicon field plate, above the field oxygen right part；
In step 10, the contact hole of drain terminal polysilicon field plate is also etched；
In step 11, metal is deposited, metal is deposited, then etches required pattern, is formed and draws isolated form NLDMOS devices
The source of part and the source metal of background region, drain terminal metal, the extraction drift p-type injection for drawing drain terminal and drain terminal polysilicon field plate
The drift region metal in area, finally completes this NLDMOS making.
The isolated form NLDMOS device of the present invention, is drawn in drift p-type injection region close to source side by drift region metal,
Drift region metal is with there is oxide layer isolation between right N-type deep trap (N-type drift region), drift region metal is used for connecting to neutral current potential.Work as leakage
End plus AC signal by high voltage drop to low-voltage when, complete depletion of drift region can recover immediately, electronics and hole
It is quick compound, realize that output current is no-delay.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, simple is made to the accompanying drawing used required for the present invention below
Introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill people
For member, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of existing isolated form NLDMOS device sectional view；
Fig. 2 is the embodiment sectional view of isolated form NLDMOS device one of the present invention；
Fig. 3 is that the embodiment N-type deep trap of manufacture method one of the isolated form NLDMOS device of the present invention forms rear sectional view；
Fig. 4 is that the embodiment oxygen of manufacture method one of the isolated form NLDMOS device of the present invention forms rear sectional view；
Fig. 5 is that the embodiment p-well of manufacture method one of the isolated form NLDMOS device of the present invention forms rear sectional view；
Fig. 6 is that the embodiment p-type injection region of manufacture method one of the isolated form NLDMOS device of the present invention forms rear sectional view；
Fig. 7 is that the embodiment grid polycrystalline silicon of manufacture method one of the isolated form NLDMOS device of the present invention forms rear section
Figure；
Fig. 8 be the present invention isolated form NLDMOS device the embodiment source and drain ion implanting of manufacture method one after sectional view；
Fig. 9 is that the embodiment of manufacture method one of the isolated form NLDMOS device of the present invention deposits sectional view after inter-level dielectric；
Figure 10 is that the embodiment of the manufacture method one drift p-type injection region exit orifice of the isolated form NLDMOS device of the present invention is formed
Sectional view afterwards；
Figure 11 is given birth at the embodiment of the manufacture method one drift p-type injection region exit orifice of the isolated form NLDMOS device of the present invention
Sectional view after long oxide layer；
Figure 12 is that the embodiment contact hole of manufacture method one of the isolated form NLDMOS device of the present invention forms rear sectional view.
Embodiment
Below in conjunction with accompanying drawing, clear, complete description is carried out to the technical scheme in the present invention, it is clear that described
Embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is general
All other embodiment that logical technical staff is obtained on the premise of creative work is not made, belongs to protection of the present invention
Scope.
Embodiment one
Isolated form NLDMOS device, cellular construction in P-type silicon substrate 101 as shown in Fig. 2 be formed with left N-type deep trap
102a, right N-type deep trap 102b two independent N-type deep trap；
The left N-type deep trap 102a, left part is formed with a p-well 104；
The p-well 104, left part is formed with a p-type heavily doped region 109 and a source N-type heavily doped region 108a；
Above the right part of p-well 104 and above the left N-type deep trap 102a right parts, gate oxide 106 is formed with；
The left N-type deep trap 102a is with the top of P-type silicon substrate 101 between the right N-type deep trap 102b, and the right N
Above moldeed depth trap 102b left parts, an oxygen 103 is formed with；
The right N-type deep trap 102b, right part is formed with a drain terminal N-type heavily doped region 108b；
Above the left part of the field oxygen 103 and top of the gate oxide 106, is formed with grid polycrystalline silicon 107a；
In the P-type silicon substrate 101 and right N-type deep trap 102b of the lower section of field oxygen 103, drift p-type injection region is formed with
105b；
Inter-level dielectric 110 is covered in device surface；
The p-type heavily doped region 109 is with the source N-type heavily doped region 108a, with the source connect through inter-level dielectric 110
Metal 111；
The drain terminal N-type heavily doped region 108b, connects the drain terminal metal through inter-level dielectric 110；
At on the left of the nearly right N-type deep traps of drift p-type injection region 105b, connect through inter-level dielectric 110, field oxygen 103, right N
Moldeed depth trap 102b drift region metal；
The drift region metal, has oxide layer isolation between right N-type deep trap 102b.
Preferably, being formed with drain terminal polysilicon field plate 107b above the right part of field oxygen 103；
The drain terminal N-type heavily doped region 108b is connect through inter-level dielectric 110 together with the drain terminal polysilicon field plate 107b
Drain terminal metal.
Preferably, P-type silicon substrate 101, p-well 104, drift p-type injection region 105b, p-type heavily doped region 109, p-type doping are dense
Degree increases successively；
Left N-type deep trap 102a, right N-type deep trap 102b n-type doping concentration, less than source N-type heavily doped region 108a, drain terminal
N-type heavily doped region 108b n-type doping concentration.
Preferably, being formed with a source p-type injection region 105a in the p-well 104.
The isolated form NLDMOS device of embodiment one, drift region gold is passed through in drift p-type injection region 105b close to source side
Category is drawn, and drift region metal is with there is oxide layer isolation between right N-type deep trap 102b (N-type drift region), drift region metal is used to connect
Zero potential.When drain terminal plus AC signal by high voltage drop to low-voltage when, complete depletion of drift region can recover immediately,
Electronics is quickly combined with hole, realizes that output current is no-delay.Wherein, drift p-type injection region 105b exits must be close to a left side
Side source metal, because peak electric field occurs in the addition of drift p-type injection region 105b exits, the peak value electric field can reach quickly
Puncture to critical electric field, and it is minimum close to electric-field intensity at source, and the peak electric field occurred here is also minimum.
Embodiment two
The manufacture method of the isolated form NLDMOS device of embodiment one, is comprised the following steps that：
One, forms left N-type deep trap 102a, right N-type deep trap 102b two in P-type silicon substrate 101 by N-type ion implanting
Independent N-type deep trap, as shown in Figure 3；
Two, utilize active area photoetching, open field oxygen region, etching Chang Yang areas, in left N-type deep trap 102a with right N-type deep trap
The top of P-type silicon substrate 101 between 102b, and above right N-type deep trap 102b left parts, raw long field oxide 103, as shown in Figure 4；
Trap injection zone is opened in three, photoetching, forms p-well 104 in left N-type deep trap 102a left part implanting p-type foreign ion, such as
Shown in Fig. 5, p-well 104 as isolated form NLDMOS device background region；
Four, carry out p-type ion implanting below the field oxygen, and the P-type silicon substrate 101 and right N-type of the lower section of oxygen 103 on the scene are deep
Drift p-type injection region 105b is formed with trap 102b, as shown in Figure 6；
Five, grow gate oxide 106, depositing polysilicon 107 on substrate by thermal oxidation process；Then polycrystalline is carried out
Si-gate is etched, and forms the grid polycrystalline silicon 107a of isolated form NLDMOS device, as shown in Figure 7；
The grid polycrystalline silicon 107a, above the right part of p-well 104, above the left N-type deep trap 102a right parts and
Above the left part of field oxygen 103；
The source and drain ion implanting of the progress routine of six, selectivity, p-type heavily doped region is formed in the left part of p-well 104 respectively
109 and source N-type heavily doped region 108a, in right N-type deep trap 102b right parts formation drain terminal N-type the heavily doped region 108b, such as Fig. 8
It is shown；
Seven, deposit inter-level dielectric 110, as shown in Figure 9 on substrate；
Eight, etchings remove the inter-level dielectric above drift p-type injection region 105b right parts (on the left of nearly right N-type deep trap)
110th, field oxygen 103, right N-type deep trap 102b body silicon, form an exit orifice for exposing drift p-type injection region 105b, as shown in Figure 10；
9th, at drift p-type injection region 105b exit orifice, oxide layer is grown, as shown in figure 11；
Ten, selective etch, etch p-type heavily doped region 109 and source N-type heavily doped region 108a contact holes, drain terminal N
Type heavily doped region 108b contact holes, and drift p-type injection region 105b contact hole, as shown in figure 12；
The contact hole of the drift p-type injection region 105b, the exit orifice with the drift p-type injection region 105b is concentric, institute
Drift p-type injection region 105b contact hole is stated with there is annular oxide layer to isolate between the right N-type deep trap 102b；
11, deposit metals (such as aluminium), then required pattern is etched, form the source for drawing isolated form NLDMOS device
Source metal 111, the drain terminal metal of extraction drain terminal and the drift region metal for drawing drift p-type injection region with background region, such as Fig. 2
It is shown, finally complete this NLDMOS making.
Preferably, in step 4, while carrying out p-type ion implanting in the p-well 104, being formed in the p-well 104
There is a source p-type injection region 105a.
Preferably, in step 4, the p-type ion of injection is boron ion, and Implantation Energy is 1000kev to 1500kev, injection
Dosage is 1E12 to 1E14 every square centimeter.
Preferably, in step 5, on substrate, gate oxide 106, depositing polysilicon 107 are grown by thermal oxidation process；
Then polysilicon gate etching is carried out, the grid polycrystalline silicon 107a and drain terminal polysilicon field plate of isolated form NLDMOS device is formed
107b, as shown in Figure 7；
The grid polycrystalline silicon 107a, above the right part of p-well 104, above the left N-type deep trap 102a right parts and
Above the left part of field oxygen 103；
The drain terminal polysilicon field plate 107b, above the right part of field oxygen 103；
In step 10, drain terminal polysilicon field plate 107b contact hole is also etched, as shown in figure 12；
In step 11, metal (such as aluminium) is deposited, then etches required pattern, the source of isolated form NLDMOS device is formed
The extraction metallic plate for drawing metallic plate, drain terminal and drain terminal polysilicon field plate 107b, the drift p-type injection region 105b of end and background region
Extraction metallic plate, as shown in Fig. 2 finally completing this NLDMOS making.
The manufacture method of the isolated form NLDMOS device of embodiment two, drift p-type injection region 105b exits pass through etching
Inter-level dielectric, field oxygen and body silicon realize that regrowth layer of oxide layer ensures metal and N-type drift region (right N-type deep trap after etching
102b) isolate.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (8)
1. a kind of isolated form NLDMOS device, it is characterised in that left N-type deep trap, right N-type deep trap are formed with P-type silicon substrate
Two independent N-type deep traps；
The left N-type deep trap, left part is formed with a p-well；
The p-well, left part is formed with a p-type heavily doped region and a source N-type heavily doped region；
Above the p-well right part and above the left N-type deep trap right part, gate oxide is formed with；
The left N-type deep trap is with above P-type silicon substrate between the right N-type deep trap, and above the right N-type deep trap left part,
It is formed with an oxygen；
The right N-type deep trap, right part is formed with a drain terminal N-type heavily doped region；
Above the field oxygen left part and above the gate oxide, grid polycrystalline silicon is formed with；
In P-type silicon substrate and right N-type deep trap below the field oxygen, drift p-type injection region is formed with；
Inter-level dielectric is covered in device surface；
The p-type heavily doped region is with the source N-type heavily doped region, with the source metal connect through inter-level dielectric；
The drain terminal N-type heavily doped region, connects the drain terminal metal through inter-level dielectric；
At on the left of the nearly right N-type deep trap in drift p-type injection region, connect through the drift region of inter-level dielectric, field oxygen and right N-type deep trap
Metal；
The drift region metal, has oxide layer isolation between right N-type deep trap.
2. isolated form NLDMOS device according to claim 1, it is characterised in that
Drain terminal polysilicon field plate is formed with above the field oxygen right part；
The drain terminal N-type heavily doped region is with the drain terminal polysilicon field plate with the drain terminal metal connect through inter-level dielectric.
3. isolated form NLDMOS device according to claim 1, it is characterised in that
P-type silicon substrate, p-well, drift p-type injection region, p-type heavily doped region, p-type doping concentration increase successively；
The n-type doping concentration of left N-type deep trap, right N-type deep trap, less than the N-type of source N-type heavily doped region, drain terminal N-type heavily doped region
Doping concentration.
4. isolated form NLDMOS device according to claim 1, it is characterised in that
A source p-type injection region is formed with the p-well.
5. a kind of manufacture method of isolated form NLDMOS device, it is characterised in that comprise the following steps：
One, forms the independent N-type deep trap of left N-type deep trap, right N-type deep trap two in P-type silicon substrate by N-type ion implanting；
Two, utilize active area photoetching, open field oxygen region, etching Chang Yang areas, in left N-type deep trap with the p-type between right N-type deep trap
Above silicon substrate, and above right N-type deep trap left part, raw long field oxide；
Trap injection zone is opened in three, photoetching, in left N-type deep trap left part implanting p-type ion formation p-well；
Four, carry out being formed with P-type silicon substrate and right N-type deep trap below p-type ion implanting, oxygen on the scene below the field oxygen
P-type of drifting about injection region；
Five, grow gate oxide, depositing polysilicon on substrate by thermal oxidation process；Then polysilicon gate etching, shape are carried out
Into the grid polycrystalline silicon of isolated form NLDMOS device；
The grid polycrystalline silicon, above the p-well right part, above the left N-type deep trap right part and on the field oxygen left part
Side；
The carry out source and drain ion implanting of six, selectivity, forms p-type heavily doped region in the p-well left part and source N-type is heavily doped respectively
Miscellaneous area, in the right N-type deep trap right part formation drain terminal N-type heavily doped region；
Seven, deposit inter-level dielectric on substrate；
Inter-level dielectric, field oxygen above on the left of the nearly right N-type deep trap in the eight, etching removals drift p-type injection region, right N-type are deep
Trap body silicon, forms an exit orifice for exposing drift p-type injection region；
9th, at the exit orifice of drift p-type injection region, oxide layer is grown；
Ten, selective etch, etch p-type heavily doped region and source N-type heavy doping contact hole, drain terminal N-type heavily doped region connect
Contact hole, and drift p-type injection region contact hole；
The contact hole of the drift p-type injection region, the exit orifice with the drift p-type injection region is concentric, the drift p-type injection
The contact hole in area is isolated with there is annular oxide layer between the right N-type deep trap；
11, deposit metal, then etch required pattern, form the source of the source for drawing isolated form NLDMOS device and background region
Metal is held, the drain terminal metal of drain terminal is drawn, draws the drift region metal of drift p-type injection region, this NLDMOS system is finally completed
Make.
6. the manufacture method of isolated form NLDMOS device according to claim 5, it is characterised in that
In step 4, while carrying out p-type ion implanting in the p-well, a source p-type injection region is formed with the p-well.
7. the manufacture method of isolated form NLDMOS device according to claim 5, it is characterised in that
In step 4, the p-type ion of injection is boron ion, and Implantation Energy is 1000kev to 1500kev, and implantation dosage is 1E12
It is every square centimeter to 1E14.
8. the manufacture method of isolated form NLDMOS device according to claim 5, it is characterised in that
In step 5, on substrate, gate oxide, depositing polysilicon are grown by thermal oxidation process；Then polysilicon gate is carried out
Etching, forms the grid polycrystalline silicon and drain terminal polysilicon field plate of isolated form NLDMOS device；
The grid polycrystalline silicon, above the p-well right part, above the left N-type deep trap right part and on the field oxygen left part
Side；
The drain terminal polysilicon field plate, above the field oxygen right part；
In step 10, the contact hole of drain terminal polysilicon field plate is also etched；
In step 11, metal is deposited, metal is deposited, then etches required pattern, is formed and draws isolated form NLDMOS device
The source metal of source and background region, the drain terminal metal for drawing drain terminal and drain terminal polysilicon field plate, draw drift p-type injection region
Drift region metal, finally completes this NLDMOS making.
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| CN105514040A (en) * | 2015-12-22 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | LDMOS device integrated with JFET and technical method |
| CN106057870A (en) * | 2016-06-24 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | High-voltage NLDMOS device and technique thereof |
| CN109888016B (en) * | 2019-01-08 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | NLDMOS device and manufacturing method thereof |
| CN111244156B (en) * | 2020-01-19 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Structure for adjusting pinch-off voltage of JFET and manufacturing method |
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| CN103579313A (en) * | 2012-08-10 | 2014-02-12 | 上海华虹Nec电子有限公司 | Structure for improving breakdown voltages of high-voltage LDMOS device |
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