CN102931093A - N-channel depletion type power MOSFET device and manufacturing method thereof - Google Patents
N-channel depletion type power MOSFET device and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an N-channel depletion type power MOSFET device and a manufacturing method thereof. The manufacturing method comprises the following steps: executing ion injection and annealing processes to form P-type well regions in an active region between grids, and executing oxide process between the steps of ion injection and annealing processes; and executing electron irradiation process to form a depletion layer between two close source regions in two adjacent P-type well regions, wherein via the electron irradiation process, electrons generated via electron irradiation form an electronic conductive channel on the silica surface of a device, namely the depletion layer is formed, the formed MOSFET device has shorter reverse recovery time, and the performance of product is further improved; and in addition, the added electron irradiation process method is compatible with the manufacturing process of a common power MOSFET device, and independent screen is needed to add to execute a channel injection process, and further process steps are saved, production efficiency is improved and production cost is lowered.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, relate in particular to a kind of N channel depletion type power MOSFET device and manufacture method.
Background technology
MOSFET (mos field effect transistor) can be divided into enhancement mode and depletion type, wherein enhancement mode refers to when VGS (gate source voltage) is 0, pipe is cut-off state, after adding suitable VGS, majority carrier attracted to grid, thereby the charge carrier under the polycrystalline grid is strengthened, form conducting channel, this metal-oxide-semiconductor is called the enhancement mode metal-oxide-semiconductor.Depletion type refers to namely have raceway groove when VGS=0, when adding suitable VGS, can make majority carrier flow out raceway groove, and the carrier depletion pipe turns to cut-off.N channel depletion type power MOSFET is when VGS=0, and the raceway groove between the drain-source exists, so as long as add VDS (drain-source voltage), ID (electric current) circulation is just arranged.If increase forward gate source voltage VGS, the electric field between grid and the substrate will make the more electronics of induction in the raceway groove, the raceway groove thickening, and the electricity of raceway groove is led increase.If add negative voltage at grid, namely VGS＜0 will induce positive charge at the device surface of correspondence, and these positive charges are offset the electronics in the N raceway groove, thereby produces a depletion layer at substrate surface, and raceway groove is narrowed down, and channel conduction reduces.When minus gate voltage increased to a certain voltage Vp, depletion region expanded to whole raceway groove, and raceway groove even at this moment VDS still exists, can not produce drain current, i.e. ID=0 fully by pinch off (namely exhausting) yet.Then Vp is called pinch-off voltage or threshold voltage, its value usually-1V～-10V between.General making depletion type MOS FET process is to carry out separately primary ions at channel region to inject to form raceway groove.
How further to improve the MOSFET performance of devices and become the industry problems of concern.
Summary of the invention
The purpose of this invention is to provide a kind of structure and manufacture method that can make N channel depletion type power MOSFET device have short reverse recovery time.
The invention provides a kind of manufacture method of N channel depletion type power MOSFET device, comprising:
Semiconductor substrate is provided, and forms epitaxial loayer in described Semiconductor substrate, described epitaxial loayer comprises that potential dividing ring forms district and active area;
In described active area, carry out ion field injection technology and annealing process, to form the ion field injection region;
Form grid at described active area;
Carry out Implantation and annealing process, with formation P type well region in the active area between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology;
In described P type well region, form the other N+ source region in P type contact zone and P type contact zone; And
Described Semiconductor substrate is carried out Electron irradiation technology, to form depletion layer between the two N+ source regions of in two adjacent P type well regions, closing on mutually.
Further, described Semiconductor substrate and described epitaxial loayer are N-type.
Further, carry out carrying out the field injection technology of phosphonium ion in the step of ion field injection technology and annealing process in described active area, to form injection region, phosphonium ion field, Implantation Energy is 60～180KEV.
Further, carry out in described active area in the step of ion field injection technology and annealing process, the annealing temperature of described annealing process is 1100 ℃～1200 ℃, and annealing time is 60～180 minutes.
Further, the step at described active area formation grid comprises: form gate oxide at described active area; Deposit spathic silicon layer on described gate oxide; Described polysilicon layer is carried out photoetching and etching, to form grid conductive layer.
Further, the thickness of described gate oxide is 4000 dusts～8000 dusts.
Further, form in deposition between the step of polysilicon layer and formation grid conductive layer, also comprise, described polysilicon layer is carried out ion doping.
Further, described polysilicon layer is being carried out in the step of ion doping, adopting phosphorus oxychloride diffusion or phosphonium ion to inject.
Further, in the step that forms P type well region, adopt the boron Implantation, Implantation Energy is 60～180KEV, and implantation dosage is 1.0E12～5.0E13.
Further, in the step that forms P type well region, the oxidizing temperature of described oxidation technology is 1000 ℃～1100 ℃, and oxidization time is 60～180 minutes.
Further, in the step that forms P type well region, described annealing process is annealed in 1000 ℃～1150 ℃ nitrogen atmosphere, and annealing time is 60～180 minutes.
Further, the formation step of described P type contact zone comprises: carry out the boron Implantation, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～1E16; Carry out annealing process, annealing temperature is 800 ℃～1000 ℃, and annealing time is 30～180 minutes.
Further, the forming process in described N+ source region comprises: carry out arsenic ion and inject, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～2E16; Carry out annealing process, 800 ℃～1000 ℃, annealing time is 30～180 minutes.
Further, in the step of carrying out Electron irradiation technology, irradiation energy is 1MeV～10MeV, and dosage is 1Mrad ~ 50Mrad.
Further, in the step that forms P type contact zone, N+ source region with carry out also comprising blanket dielectric layer on described epitaxial loayer between the processing step of electron irradiation; In described dielectric layer, form the fairlead window; Carry out front-side metallization technique at described dielectric layer, to form the front metal lead-in wire.
Further, the material of described dielectric layer is boron-phosphorosilicate glass.
Further, after the step of carrying out Electron irradiation technology, also comprise, described Semiconductor substrate is carried out thinning back side and back side metallization technology, and in the vacuum alloying furnace, anneal, wherein annealing temperature is 250 ℃～360 ℃, annealing time is 30～90 minutes.
The present invention also provides a kind of N channel depletion type power MOSFET device, comprising: Semiconductor substrate and the epitaxial loayer that is located thereon, described epitaxial loayer comprise that potential dividing ring forms district and active area; Grid is formed on the described active area; P type well region is formed in the active area between described grid; The N+ source region that P type contact zone and P type contact zone are other all is formed in the described P type well region; Also comprise depletion layer, described depletion layer is formed between the two N+ source regions of closing on mutually in two adjacent P type well regions.
Further, described Semiconductor substrate and described epitaxial loayer are N-type.
Further, described grid comprises: gate oxide is formed on the described active area; Grid conductive layer is formed on the described gate oxide.
Further, the thickness of described gate oxide is 4000 dusts～8000 dusts.
Further, N channel depletion type power MOSFET device also comprises, dielectric layer is covered on the described epitaxial loayer; The fairlead window is formed in the described dielectric layer; The front metal lead-in wire is formed on the described dielectric layer.
Further, the material of described dielectric layer is boron-phosphorosilicate glass.
Further, described N channel depletion type power MOSFET device comprises that also metal layer on back, described metal layer on back are formed at one side relative with described epitaxial loayer on the described Semiconductor substrate.
In sum, the manufacture method of N channel depletion type power MOSFET device of the present invention, by in the power MOSFET manufacture craft process, form in the process of P type well region in the active area between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology, described oxidation technology makes epi-layer surface form the interface of silicon dioxide and silicon, thereby in follow-up step of carrying out Electron irradiation technology, make the interface of the silicon dioxide of device and silicon and near silicon dioxide layer in produce defective and trap, by suitable Electron irradiation technology, the electronics that is produced by electron irradiation forms the electronic conduction raceway groove at the silicon face of device, namely form depletion layer, thereby being exhausted, the hole produces N channel depletion type power MOSFET device, make the MOSFET device of formation have short reverse recovery time, and then promoted the performance of product.
Simultaneously owing to adopt Electron irradiation technology, the structure cell forming process of N channel depletion type power MOSFET device is consistent with conventional process, do not need to increase separately version and regulate channel dopant dosage, simultaneously, the method that increases Electron irradiation technology is compatible mutually with the manufacturing process of conventional power MOSFET device, and then increased technological flexibility, saved technological process and production cost.
The structure of N channel depletion type power MOSFET device of the present invention is by forming depletion layer, described depletion layer is formed between the two N+ source regions of closing on mutually in two adjacent P type well regions, make the MOSFET device of formation have short reverse recovery time, and then promoted the performance of product.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of N channel depletion type power MOSFET device in one embodiment of the invention.
Fig. 2～Fig. 7 is the structural representation of the manufacture process of N channel depletion type power MOSFET device in one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the schematic flow sheet of the manufacture method of N channel depletion type power MOSFET device in one embodiment of the invention.The invention provides a kind of manufacture method of N channel depletion type power MOSFET device, may further comprise the steps:
Step S101: Semiconductor substrate is provided, and forms epitaxial loayer in described Semiconductor substrate, described epitaxial loayer comprises that potential dividing ring forms district and active area;
Step S102: in described active area, carry out ion field injection technology and annealing process, to reduce conducting resistance;
Step S103: form grid at described active area;
Step S104: carry out Implantation and annealing process, with formation P type well region in the active area between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology;
Step S105: in described P type well region, form the other N+ source region in P type contact zone and P type contact zone; And
Step S106: carry out Electron irradiation technology, to form depletion layer between the two N+ source regions of in two adjacent P type well regions, closing on mutually.
Fig. 2～Fig. 7 is the structural representation of the manufacture process of N channel depletion type power MOSFET device in one embodiment of the invention.Below in conjunction with Fig. 1～Fig. 7, describe the manufacture method of N channel depletion type power MOSFET device of the present invention in detail.
As shown in Figure 2, in step S101, described Semiconductor substrate 10 and described epitaxial loayer 12 are N-type.Wherein preferably select heavy doping N-type＜100〉Semiconductor substrate 100 of crystal orientation direction, at the epitaxial loayer 12 of described Semiconductor substrate 100 growth one deck N-types, concrete epitaxial loayer 12 thickness and resistivity specification are withstand voltage and the conducting resistance specification is specifically selected according to product.Described epitaxial loayer 12 comprises that potential dividing ring forms district 100 and active area 200, then form to distinguish at described potential dividing ring to form P type ring 1-1 in 100, and the potential dividing ring around described P type ring 1-1 forms district 100 formation field oxide 1-2.
Then, as shown in Figure 3, in step S102, in described active area 200, carry out ion field injection technology and annealing process, form in order to reduce the injection region 3, field of conducting resistance, particularly, carry out the field injection technology of phosphonium ion, better Implantation Energy is 60～180KEV, and injection region, described phosphonium ion field 3 can further reduce the conducting resistance of device, improves performance of devices.In preferred embodiment, in described active area 200, to carry out in the step of ion field injection technology and annealing process, the annealing temperature of described annealing process is 1100 ℃～1200 ℃, annealing time is 60～180 minutes.
Then as shown in Figure 4, in step S103, form grid 4 at described active area 200, described grid 4 comprises gate oxide 4-1 and grid conductive layer 4-2, and the step that forms grid 4 at described active area 200 specifically comprises: form gate oxide 4-1 at described active area 200; Deposit spathic silicon layer on described gate oxide 4-1 (not indicating among the figure); Described polysilicon layer is carried out photoetching and etching, to form grid conductive layer 4-2.Wherein, the better thickness of described gate oxide 4-1 is 4000 dusts～8000 dusts.Form in deposition between the step of polysilicon layer and formation grid conductive layer, also comprise described polysilicon layer is carried out ion doping, polysilicon layer is carried out the performance that ion doping can improve the grid conductive layer of follow-up formation.Wherein, preferably phosphorus oxychloride (POCL3) diffusion or phosphonium ion inject.
In conjunction with Fig. 5, in step S104, carry out Implantation and annealing process, with formation P type well region 5 in the active area 200 between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology, wherein in the step that forms P type well region 5, can adopt the boron Implantation, Implantation Energy is 60～180KEV, and implantation dosage is 1.0E12～5.0E13.Further, in the step that forms P type well region 5, the oxidizing temperature of described oxidation technology is 1000 ℃～1100 ℃, and oxidization time is 60～180 minutes.Further, in the step that forms P type well region 5, described annealing process is annealed in 1000 ℃～1150 ℃ nitrogen atmosphere, and annealing time is 60～180 minutes.
Continuation in step S105, forms the N+ source region 7 on P type contact zone 6 and 6 sides, P type contact zone with reference to figure 5 in described P type well region 5, described N+ source region 7 is N-type heavy doping source region.Further, the formation step of described P type contact zone 6 comprises: carry out the boron Implantation, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～1E16; Then carry out annealing process, annealing temperature is 800 ℃～1000 ℃, and annealing time is 30～180 minutes.And the forming process in described N+ source region 7 comprises: carry out arsenic ion and inject, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～2E16; Then carry out annealing process, 800 ℃～1000 ℃, annealing time is 30～180 minutes.
As shown in Figure 6, between the processing step that carries out electron irradiation of the step in the formation P of step S105 type contact zone 6, N+ source region 7 and step S106, also comprise blanket dielectric layer 8 on described epitaxial loayer 12; Then, in described dielectric layer 8, form the fairlead window; Carry out front-side metallization technique at described dielectric layer 8, to form front metal lead-in wire 9, described metal lead wire 9 is drawn described P type contact zone 6 by the fairlead window.What the material of described dielectric layer was better is boron-phosphorosilicate glass.
Continuation in step S106, is carried out Electron irradiation technology with reference to figure 6, to form depletion layer 13 between the two N+ source regions of closing on mutually in two adjacent P type well regions 7.Further, in the step of carrying out Electron irradiation technology, irradiation energy is 1MeV～10MeV, and dosage is 1Mrad～50Mrad (Megarad).Electron irradiation (Electron irradiation) be exactly adopt high-power electron beam shine material, to improve a kind of technology of material property.In microelectric technique, electron irradiation namely is the purpose that realizes controlling minority carrier lifetime with high energy electron irradiation semiconductor.Electron irradiation owing to causing the crystal atoms displacement, high-energy electron irradiation produces the complex centre of deep energy level, so can be used to control carrier lifetime.For example, electron irradiation can produce two energy levels in silicon, one be the above 0.4eV of top of valence band be subjected to the principal mode energy level, another is the donor-type energy level of following 0.36eV at the bottom of conduction band.
Thereafter, as shown in Figure 7, after the step of carrying out Electron irradiation technology of step S106, also comprise, described Semiconductor substrate 10 is carried out thinning back side and back side metallization technology, with the back side in described Semiconductor substrate, and in the vacuum alloying furnace, anneal, wherein annealing temperature is 250 ℃～360 ℃, and annealing time is 30～90 minutes, namely forms metal layer on back 14 in the one side relative with described epitaxial loayer place.
In sum, the manufacture method of N channel depletion type power MOSFET device of the present invention, by in the power MOSFET manufacture craft process, form in the process of P type well region in the active area between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology, described oxidation technology makes epi-layer surface form the interface of silicon dioxide and silicon, thereby in follow-up step of carrying out Electron irradiation technology, make the interface of the silicon dioxide of device and silicon and near silicon dioxide layer in produce defective and trap, Electron irradiation technology can inspire electron hole pair in silicon dioxide, the very fast silicon dioxide that moves out of of electronics enters silicon face, a hole part is also moved out of silicon dioxide, and a part of being captured by the hole trap in the silicon dioxide becomes positive electric charge.By suitable Electron irradiation technology, the electronics that is produced by electron irradiation forms the electronic conduction raceway groove at the silicon face of device, it is depletion layer, thereby being exhausted, the hole produces N channel depletion type power MOSFET device, and in conjunction with oxidation technology, can further improve the combination of depletion layer, thereby make the MOSFET device of formation have short reverse recovery time, and then promote the performance of product.
Simultaneously owing to adopt Electron irradiation technology, the structure cell forming process of N channel depletion type power MOSFET device is consistent with conventional process, do not need to increase separately version and regulate channel dopant dosage, simultaneously, the method that increases Electron irradiation technology is compatible mutually with the manufacturing process of conventional power MOSFET device, and then increased technological flexibility, saved technological process and production cost.
In conjunction with Fig. 7, the present invention also provides a kind of N channel depletion type power MOSFET device, comprising: Semiconductor substrate 10 and the epitaxial loayer 12 that is located thereon, described epitaxial loayer 12 comprise that potential dividing ring forms district 100 and active area 200; Grid 4 is formed on the described active area 200; P type well region 5 is formed in the active area 200 between described grid 4; The N+ source region 7 on P type contact zone 6 and 6 sides, P type contact zone all is formed in the described P type well region 5; Also comprise depletion layer 13, described depletion layer 13 is formed between the two N+ source regions 7 of closing on mutually in two adjacent P type well regions 5.
The structure of described N channel depletion type power MOSFET device is by forming depletion layer, described depletion layer is formed between the two N+ source regions 7 of closing on mutually in two adjacent P type well regions, make the MOSFET device of formation have short reverse recovery time, and then promoted the performance of product.
In preferred embodiment, described Semiconductor substrate 10 and described epitaxial loayer 12 are N-type.Described grid 4 comprises: gate oxide 4-1 is formed on the described active area 200; Grid conductive layer 4-2 is formed on the described gate oxide 4-1.Further, the better thickness of described gate oxide 4-1 is 4000 dusts～8000 dusts.In preferred embodiment, described N channel depletion type power MOSFET device also comprises, dielectric layer 8, fairlead window and front metal lead-in wire 9, and described dielectric layer 8 is covered on the described epitaxial loayer; Described fairlead window-shaped is formed in the described dielectric layer 8; Described front metal lead-in wire 9 is formed on the described dielectric layer 8.Wherein said dielectric layer 8 better materials are boron-phosphorosilicate glass.N channel depletion type power MOSFET device of the present invention can adopt aforementioned manufacture method to form.
In preferred embodiment, metal layer on back 14, described metal layer on back 14 are formed on the described Semiconductor substrate 10 one side relative with described epitaxial loayer 12.The signal that described metal layer on back 14 is used for Semiconductor substrate 10 back sides is drawn.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (24)
1. the manufacture method of a N channel depletion type power MOSFET device comprises
Semiconductor substrate is provided, and forms epitaxial loayer in described Semiconductor substrate, described epitaxial loayer comprises that potential dividing ring forms district and active area;
In described active area, carry out ion field injection technology and annealing process, to form the ion field injection region;
Form grid at described active area;
Carry out Implantation and annealing process, with formation P type well region in the active area between described grid, and between the step of carrying out Implantation and annealing process, carry out oxidation technology;
In described P type well region, form the other N+ source region in P type contact zone and P type contact zone;
Described Semiconductor substrate is carried out Electron irradiation technology, to form depletion layer between the two N+ source regions of in two adjacent P type well regions, closing on mutually.
2. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, described Semiconductor substrate and described epitaxial loayer are N-type.
3. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1, it is characterized in that, in described active area, carry out in the step of ion field injection technology and annealing process, carry out the field injection technology of phosphonium ion, to form injection region, phosphonium ion field, Implantation Energy is 60～180KEV.
4. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1, it is characterized in that, carry out in described active area in the step of ion field injection technology and annealing process, the annealing temperature of described annealing process is 1100 ℃～1200 ℃, and annealing time is 60～180 minutes.
5. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, the step that forms grid at described active area comprises:
Form gate oxide at described active area;
Deposit spathic silicon layer on described gate oxide;
Described polysilicon layer is carried out photoetching and etching, to form grid conductive layer.
6. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 5 is characterized in that, the thickness of described gate oxide is 4000 dusts～8000 dusts.
7. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 6 is characterized in that, forms in deposition between the step of polysilicon layer and formation grid conductive layer, also comprises, described polysilicon layer is carried out ion doping.
8. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 7 is characterized in that, described polysilicon layer is being carried out in the step of ion doping, adopts phosphorus oxychloride diffusion or phosphonium ion to inject.
9. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, in the step that forms P type well region, adopts the boron Implantation, and Implantation Energy is 60～180KEV, and implantation dosage is 1.0E12～5.0E13.
10. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, in the step that forms P type well region, the oxidizing temperature of described oxidation technology is 1000 ℃～1100 ℃, and oxidization time is 60～180 minutes.
11. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1, it is characterized in that, in the step that forms P type well region, described annealing process is annealed in 1000 ℃～1150 ℃ nitrogen atmosphere, and annealing time is 60～180 minutes.
12. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, the formation step of described P type contact zone comprises:
Carry out the boron Implantation, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～1E16;
Carry out annealing process, annealing temperature is 800 ℃～1000 ℃, and annealing time is 30～180 minutes.
13. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, the forming process in described N+ source region comprises:
Carry out arsenic ion and inject, Implantation Energy is 60～150KEV, and implantation dosage is 1E15～2E16;
Carry out annealing process, 800 ℃～1000 ℃, annealing time is 0～180 minute.
14. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, in the step of carrying out Electron irradiation technology, irradiation energy is 1MeV～10MeV, and dosage is 1Mrad～50Mrad.
15. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, in the step that forms P type contact zone, N+ source region with carry out also comprising between the processing step of electron irradiation,
Blanket dielectric layer on described epitaxial loayer;
In described dielectric layer, form the fairlead window;
Carry out front-side metallization technique at described dielectric layer, to form the front metal lead-in wire.
16. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 15 is characterized in that, the material of described dielectric layer is boron-phosphorosilicate glass.
17. the manufacture method of N channel depletion type power MOSFET device as claimed in claim 1 is characterized in that, after the step of carrying out Electron irradiation technology, also comprises,
Described Semiconductor substrate is carried out thinning back side and back side metallization technology, and anneal in the vacuum alloying furnace, wherein annealing temperature is 250 ℃～360 ℃, and annealing time is 30～90 minutes.
18. a N channel depletion type power MOSFET device comprises
Semiconductor substrate and the epitaxial loayer that is located thereon, described epitaxial loayer comprise that potential dividing ring forms district and active area;
Grid is formed on the described active area;
P type well region is formed in the active area between described grid;
The source region that P type contact zone and P type contact zone are other all is formed in the described P type well region; It is characterized in that, also comprise
Depletion layer, described depletion layer are formed between the two N+ source regions of closing on mutually in two adjacent P type well regions.
19. N channel depletion type power MOSFET device as claimed in claim 18 is characterized in that described Semiconductor substrate and described epitaxial loayer are N-type.
20. N channel depletion type power MOSFET device as claimed in claim 18 is characterized in that described grid comprises:
Gate oxide is formed on the described active area;
Grid conductive layer is formed on the described gate oxide.
21. N channel depletion type power MOSFET device as claimed in claim 20 is characterized in that, the thickness of described gate oxide is 4000 dusts～8000 dusts.
22. N channel depletion type power MOSFET device as claimed in claim 18 is characterized in that, also comprises,
Dielectric layer is covered on the described epitaxial loayer;
The fairlead window is formed in the described dielectric layer;
The front metal lead-in wire is formed on the described dielectric layer.
23. N channel depletion type power MOSFET device as claimed in claim 22 is characterized in that the material of described dielectric layer is boron-phosphorosilicate glass.
24. N channel depletion type power MOSFET device as claimed in claim 22 is characterized in that, also comprises,
Metal layer on back, described metal layer on back are formed at one side relative with described epitaxial loayer on the described Semiconductor substrate.
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| CN107887287A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method of testing |
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| CN109742030A (en) * | 2019-01-21 | 2019-05-10 | 东南大学 | The electron irradiation of threshold voltage stabilization restores SJ-VDMOS preparation method fastly |
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