CN107887287B - Test method - Google Patents
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- CN107887287B CN107887287B CN201610877477.7A CN201610877477A CN107887287B CN 107887287 B CN107887287 B CN 107887287B CN 201610877477 A CN201610877477 A CN 201610877477A CN 107887287 B CN107887287 B CN 107887287B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Automation & Control Theory (AREA)
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Abstract
The invention discloses a test method. According to the test method provided by the invention, a reference pinch-off voltage is obtained through the reference unit during testing; and obtaining a test pinch-off voltage through the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage. Therefore, the temperature condition of the epitaxial layer during formation can be visually detected, and the quality of the epitaxial layer can be better grasped, so that abnormal products can be adjusted in time, and the conditions of probe detection and low final detection yield are avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test method.
Background
Currently, in the fabrication of devices such as CMOS, a common choice is to form a P-type epitaxial layer on a P-type substrate and then complete the fabrication of the source, the drain and the gate, so as to improve the device performance and reduce the leakage current.
However, how the quality of the epitaxial layer, and particularly whether the epitaxial layer is maintained within a desired temperature range during formation, directly limits whether the device can meet the standards.
However, considering the high temperature during the epitaxial layer preparation, it is not convenient for the offline detection (offline monitor) of the manufacturing department, and there is no effective WAT (wafer acceptance test) test structure.
Disclosure of Invention
The invention aims to provide a test method so as to detect whether the temperature of an epitaxial layer is normal during preparation.
In order to solve the above technical problem, the present invention provides a testing method, which utilizes a testing structure to perform testing, wherein the testing structure comprises a reference unit and a testing unit; the reference cell includes a first substrate; a first epitaxial layer on the first substrate; the first source/drain electrode is positioned in the first epitaxial layer, and the first grid electrode is positioned between the first source/drain electrode on the first epitaxial layer; the first substrate is electrically connected with the first grid, the first source electrode is grounded, and the first drain electrode is connected with an external power supply; the test unit includes a second substrate; a second epitaxial layer on the second substrate; a second source/drain on the second epitaxial layer, a second gate on the second epitaxial layer between the second source/drain; the test method comprises the following steps:
obtaining a reference pinch-off voltage by using the reference unit;
and measuring the test pinch-off voltage of the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage.
Optionally, for the test method, a reference pinch-off voltage range is determined according to the reference pinch-off voltage, and if the test pinch-off voltage exceeds the reference pinch-off voltage range, it is determined that the temperature of the second epitaxial layer is abnormal during formation.
Optionally, for the test method, if the test pinch-off voltage is greater than the maximum value of the reference pinch-off voltage range, it is determined that the temperature of the second epitaxial layer is too low during formation.
Optionally, for the test method, if the test pinch-off voltage is smaller than the minimum value of the reference pinch-off voltage range, it is determined that the temperature of the second epitaxial layer is too high during formation.
Optionally, for the test method, if the test clamp off voltage is within the reference clamp off voltage range, it is determined that the temperature of the second epitaxial layer is normal when the second epitaxial layer is formed.
Optionally, for the test method, the obtaining a reference pinch-off voltage by using the reference unit includes:
applying a first voltage on the first drain;
applying a voltage which is gradually changed to the first grid electrode to enable the drain current to reach a reference current value; at this time, the voltage between the first gate and the first source is the reference pinch-off voltage.
Optionally, for the testing method, the voltage of the gradual transformation is 0 to-10V, and the change amount is-0.1V to-0.3V.
Optionally, for the testing method, the reference current value is less than or equal to 0.5 μ a.
Optionally, for the testing method, the first substrate and the second substrate are both P-type substrates.
Optionally, for the testing method, the first epitaxial layer and the second epitaxial layer are both P-type epitaxial layers.
Optionally, for the testing method, the doping concentrations of the first substrate and the second substrate are both greater than the doping concentrations of the first epitaxial layer and the second epitaxial layer.
According to the test method provided by the invention, a reference pinch-off voltage is obtained through the reference unit during testing; and obtaining a test pinch-off voltage through the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage. Therefore, the temperature condition of the epitaxial layer during formation can be intuitively detected, the quality of the epitaxial layer can be better grasped, abnormal products can be adjusted in time, and the conditions of probe detection and low final detection yield are avoided as far as possible.
Drawings
FIG. 1 is a schematic diagram of a test structure according to the present invention;
FIG. 2 is a flow chart of a test method of the present invention;
FIG. 3 is a graph of experimental data using the test method of the present invention.
Detailed Description
The test method of the present invention will now be described in more detail with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As previously mentioned, the fabrication of semiconductor devices (e.g., CMOS, etc.) is currently accomplished by forming an epitaxial layer on a substrate, primarily considering that the resistivity of the epitaxial layer is about 28.5 Ω -cm, which is a value greater than 8-12 Ω -cm of the substrate, meaning that the concentration of dopant ions (e.g., boron ions) in the epitaxial layer is less than the concentration of dopant ions (e.g., boron ions) in the substrate. Also due to this, dopant ions can easily diffuse from the substrate into the epitaxial layer, which can adversely affect the quality of the device.
Temperature is an important factor influencing ion diffusion, and if the temperature is too high in the preparation process of the epitaxial layer, more doped ions are likely to be diffused into the epitaxial layer. After long-term research, the inventor finds that after doping ions diffuse into an epitaxial layer, a depletion layer is formed at the contact position of the bottom of the epitaxial layer and a substrate, the range size of the depletion layer is directly related to the doping ions diffused into the epitaxial layer, and particularly when the doping ions diffuse close to the epitaxial layer in large quantity, the depletion layer is enlarged, so that a carrier channel is reduced, and in this case, the pinch-off voltage is reduced; when the dopant ions diffuse a small amount near the epitaxial layer, the depletion layer becomes small, so that the carrier channel becomes large, and in this case, the pinch-off voltage becomes large. Therefore, it can be seen that the pinch-off voltage becomes lower when the temperature is too high in the formation of the epitaxial layer, and becomes higher when the temperature is too low in the formation of the epitaxial layer. Then, whether the temperature during the formation of the epitaxial layer meets the standard can be judged by setting a reference threshold and detecting the clamping voltage, so that whether the prepared product is abnormal can be judged in advance.
The test method of the invention uses the test structure as shown in fig. 1 to test, and the test structure comprises a reference unit 10 and a test unit 20;
the reference unit 10 comprises
A first substrate 11;
a first epitaxial layer 12 on the first substrate 11;
a first source/ drain 13, 14 in the first epitaxial layer 12, a first gate 15 between the first source/ drain 13, 14 on the first epitaxial layer 12;
the first substrate 11 is electrically connected to the first gate 15, the first source 13 is grounded, and the first drain 14 is connected to an external power supply;
the test unit 20 comprises
A second substrate 21;
a second epitaxial layer 22 on the second substrate;
a second source/ drain 23, 24 in the second epitaxial layer 22, and a second gate 25 on the second epitaxial layer 22 between the second source/ drain 23, 24.
It will be appreciated that the reference unit 10 may be prepared separately, i.e. may be able to be used as a reference (Baseline) for the same or similar products. For example, the product may be already manufactured, and the electrical parameters are detected and confirmed to be excellent, and then the corresponding connection is realized according to the above description. Of course, for products with different specifications, such as MOS devices, diode devices (diode), resistance-capacitance devices (RC), etc., a product with good electrical parameters after detection can be selected, and then the corresponding connection is implemented according to the above description to serve as a reference.
In the embodiment of the present invention, the first substrate 11 and the second substrate 21 are both P-type substrates, for example, doped with boron as an impurity ion. The first epitaxial layer 12 and the second epitaxial layer 22 are both P-type epitaxial layers, and the doping concentration of the first substrate 11 and the doping concentration of the second substrate 21 are both greater than the doping concentration of the first epitaxial layer 12 and the second epitaxial layer 22.
The first source/ drain 13, 14, the first gate 15, the second source/ drain 23, 24, and the second gate 25 can be fabricated according to the prior art, which is not described in detail herein.
Moreover, for the same or similar products, the setting of the manufacturing process is the same, so that the detection invalidation caused by the inconsistency of the process is avoided.
The following description will be made with reference to fig. 2 for a testing method using the test structure of the present invention.
As shown in fig. 2, the testing method includes:
step S11, obtaining a reference pinch-off voltage by using the reference cell;
and step S12, measuring the test pinch-off voltage of the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage.
Specifically, for step S11, a first voltage is first applied to the first drain 14, and it is understood that the first voltage is a fixed value; at this time, a voltage difference is generated between the first source 13 and the first drain 14, so that the first source is turned on, and a drain current is detected. Then, a gradually changing voltage is applied to the first gate 15, so that the drain current reaches a reference current value; the voltage between the first gate 15 and the first source 13 is the reference pinch-off voltage.
For example, the voltage of the stepwise transformation may be 0 to-10V, and the amount of change is-0.1V to-0.3V, e.g., 0.2V. The reference current value is 0.5 muA or less. Referring to fig. 1, in the case of gradually changing the voltage on the first gate 15, the depletion layer 16 will gradually expand, so that the detected drain current gradually decreases, when the reference current is reached (or is smaller than) the source-drain current can be considered as being pinched off, and since the reference cell 10 is trusted, the obtained voltage between the first gate 15 and the first source 13 is also correct as the reference pinch-off voltage.
Referring to fig. 1, the test unit 20 is tested for the test pinch-off voltage in step S12, which is well known in the art and will not be described in detail.
During the test, depletion layer 26 will vary, and when depletion layer 26 reaches a certain width, the pinch-off voltage is obtained, and it is important to ensure that the test pinch-off voltage is the same (or approximately the same) as the reference pinch-off voltage, whether depletion layer 26 has been affected during the fabrication of second epitaxial layer 22.
If the doping concentration in the second epitaxial layer 22 changes due to the abnormal temperature during the preparation of the epitaxial layer 22 as described above, the depletion layer 26 changes accordingly, which is different from the width that the depletion layer should have under normal conditions, and the test pinch-off voltage obtained during the test is also different from the reference pinch-off voltage, so that the temperature can be determined to be abnormal during the formation of the second epitaxial layer 22 according to the measured test pinch-off voltage.
It can be appreciated that each parameter fluctuates during semiconductor processing and is acceptable within a certain fluctuation range, and thus, in the present invention, a reference pinch-off voltage range can be determined based on the reference pinch-off voltage, and if the test pinch-off voltage exceeds the reference pinch-off voltage range, it is determined that the temperature of the second epitaxial layer is abnormal when it is formed.
Specifically, if the temperature is too high during the formation of the second epitaxial layer 22, more dopant ions will diffuse from the second substrate 21 into the second epitaxial layer 22, and the depletion layer 26 has a large initial width and is more easily pinched off, i.e., the measured test pinch-off voltage is smaller than the reference pinch-off voltage (for the case of setting the reference pinch-off voltage range, if the test pinch-off voltage is smaller than the minimum value of the reference pinch-off voltage range). Thus, by determining that the measured test pinch-off voltage is lower than the reference pinch-off voltage, it can be determined that the temperature is too high when the second epitaxial layer 22 is formed.
Specifically, if the temperature is too low during the formation of the second epitaxial layer 22, and less dopant ions are diffused from the second substrate 21 into the second epitaxial layer 22, the initial width of the depletion layer 26 is small, and the depletion layer is less likely to be pinched off, i.e., the measured test pinch-off voltage is greater than the reference pinch-off voltage (for the case of setting the reference pinch-off voltage range, if the test pinch-off voltage is greater than the maximum value of the reference pinch-off voltage range). Thus, by the fact that the measured test pinch-off voltage is greater than the reference pinch-off voltage, it can be determined that the temperature is too low when the second epitaxial layer 22 is formed.
It will be appreciated that if the second epitaxial layer 22 is formed at a normal temperature, then the test pinch-off voltage will be equal to (or approximately equal to) the reference pinch-off voltage (i.e., the test pinch-off voltage is within the reference pinch-off voltage range).
Further, in order to verify the detection method of the present invention, the inventors conducted the following detection experiment. The temperatures at which epitaxial layers (having the same thickness) at 1050 ℃ and 1100 ℃ are formed are set, device formation is performed a plurality of times, and then the pinch-off voltage is detected, as shown in fig. 3, each dot represents a sample, and after samples with normal distribution outside the (μ -3 σ, μ +3 σ) region (μ is expected, i.e., mean value; σ is standard deviation STD) are excluded for both temperatures, it is found that for products with high temperature at epitaxial layer formation, the pinch-off voltage is low, i.e., for epitaxial layers with a formation temperature of 1050 ℃, the mean value of the pinch-off voltage of the corresponding product is 15 (standard deviation STD is 0.266), and for epitaxial layers with a formation temperature of 1100 ℃, the mean value of the pinch-off voltage of the corresponding product is 14.6 (standard deviation STD is 0.321), and the standard deviation STD is both small, indicating that the mean value of the measured pinch-off voltage is reliable. Thereby proving the authenticity and reliability of the detection structure and the detection method of the present invention.
In summary, the testing method provided by the present invention utilizes a testing structure to perform testing, where the testing structure includes a reference unit and a testing unit; the reference cell includes a first substrate; a first epitaxial layer on the first substrate; the first source/drain electrode is positioned in the first epitaxial layer, and the first grid electrode is positioned between the first source/drain electrode on the first epitaxial layer; the first substrate is electrically connected with the first grid, the first source electrode is grounded, and the first drain electrode is connected with an external power supply; the test unit includes a second substrate; a second epitaxial layer on the second substrate; a second source/drain on the second epitaxial layer, and a second gate on the second epitaxial layer between the second source/drain. When testing, obtaining a reference pinch-off voltage through the reference unit; and obtaining a test pinch-off voltage through the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage. Therefore, the temperature condition of the epitaxial layer during formation can be intuitively detected, the quality of the epitaxial layer can be better grasped, abnormal products can be adjusted in time, and the conditions of probe detection and low final detection yield are avoided as far as possible.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A test method is used for testing by utilizing a test structure, wherein the test structure comprises a reference unit and a test unit; the reference cell includes a first substrate; a first epitaxial layer on the first substrate; the first source/drain electrode is positioned in the first epitaxial layer, and the first grid electrode is positioned on the first epitaxial layer and between the first source/drain electrodes; the first substrate is electrically connected with the first grid, the first source electrode is grounded, the first drain electrode is connected with an external power supply, and the electrical parameters of the reference unit are qualified; the test unit includes a second substrate; a second epitaxial layer on the second substrate; a second source/drain on the second epitaxial layer, a second gate on the second epitaxial layer between the second source/drain; the test method comprises the following steps:
obtaining a reference pinch-off voltage by using the reference unit;
and measuring the test pinch-off voltage of the test unit, and judging the temperature condition of the second epitaxial layer during formation according to the test pinch-off voltage and the reference pinch-off voltage.
2. The test method of claim 1, wherein a reference pinch-off voltage range is determined according to the reference pinch-off voltage, and if the test pinch-off voltage exceeds the reference pinch-off voltage range, the temperature anomaly of the second epitaxial layer during formation is determined.
3. The test method of claim 2, wherein if the test pinch-off voltage is greater than a maximum value of the reference pinch-off voltage range, it is determined that the temperature of the second epitaxial layer is too low when formed.
4. The test method of claim 2, wherein if the test pinch-off voltage is less than a minimum value of the reference pinch-off voltage range, it is determined that the second epitaxial layer is at an excessive temperature during formation.
5. The test method of claim 2, wherein if the test pinch-off voltage is within the reference pinch-off voltage range, the temperature of the second epitaxial layer is determined to be normal during formation.
6. The test method of claim 1, wherein the obtaining a reference pinch-off voltage using the reference cell comprises:
applying a first voltage on the first drain;
applying a voltage which is gradually changed to the first grid electrode to enable the drain current to reach a reference current value; at this time, the voltage between the first gate and the first source is the reference pinch-off voltage.
7. The test method according to claim 6, wherein the voltage of the stepwise transformation is 0 to-10V and the amount of change is-0.1V to-0.3V.
8. The test method according to claim 6, wherein the reference current value is 0.5 μ a or less.
9. The test method of claim 1, wherein the first substrate and the second substrate are both P-type substrates.
10. The test method of claim 9, wherein the first epitaxial layer and the second epitaxial layer are both P-type epitaxial layers.
11. The test method of claim 10, wherein the doping concentration of the first and second substrates are both greater than the doping concentration of the first and second epitaxial layers.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516460A (en) * | 1978-07-21 | 1980-02-05 | Nec Corp | Crystal growing method |
| JPS639943A (en) * | 1986-06-30 | 1988-01-16 | Nec Kansai Ltd | Thermometric method of semiconductor wafer |
| US4803533A (en) * | 1986-09-30 | 1989-02-07 | General Electric Company | IGT and MOSFET devices having reduced channel width |
| JPH05283620A (en) * | 1992-03-31 | 1993-10-29 | Mitsubishi Electric Corp | Semiconductor device and test method of semiconductor device |
| JP3405682B2 (en) * | 1998-07-15 | 2003-05-12 | 日本電信電話株式会社 | Nondestructive inspection method for semiconductor epitaxial film |
| JP2005183666A (en) * | 2003-12-19 | 2005-07-07 | Hitachi Cable Ltd | Gallium nitride-based compound semiconductor and its manufacturing method |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| CN103063729A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Method for detecting epitaxial silicon defects |
| CN103081080A (en) * | 2010-08-25 | 2013-05-01 | 日本碍子株式会社 | Epitaxial substrate for semiconductor element, semiconductor element, method for fabricating epitaxial substrate for semiconductor element, and method for fabricating semiconductor element |
| CN103605388A (en) * | 2013-10-25 | 2014-02-26 | 上海晶盟硅材料有限公司 | Method for detecting temperature of temperature field of epitaxial furnace platform through ion-implanted chip and method for correcting temperature field of epitaxial furnace platform through ion-implanted chip |
| CN103681240A (en) * | 2013-12-12 | 2014-03-26 | 杭州士兰集成电路有限公司 | Epitaxial temperature testing and monitoring structure and forming method |
| US9011599B2 (en) * | 2010-07-14 | 2015-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of temperature determination for deposition reactors |
| CN104576728A (en) * | 2013-10-10 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104810396A (en) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
-
2016
- 2016-09-30 CN CN201610877477.7A patent/CN107887287B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516460A (en) * | 1978-07-21 | 1980-02-05 | Nec Corp | Crystal growing method |
| JPS639943A (en) * | 1986-06-30 | 1988-01-16 | Nec Kansai Ltd | Thermometric method of semiconductor wafer |
| US4803533A (en) * | 1986-09-30 | 1989-02-07 | General Electric Company | IGT and MOSFET devices having reduced channel width |
| JPH05283620A (en) * | 1992-03-31 | 1993-10-29 | Mitsubishi Electric Corp | Semiconductor device and test method of semiconductor device |
| JP3405682B2 (en) * | 1998-07-15 | 2003-05-12 | 日本電信電話株式会社 | Nondestructive inspection method for semiconductor epitaxial film |
| JP2005183666A (en) * | 2003-12-19 | 2005-07-07 | Hitachi Cable Ltd | Gallium nitride-based compound semiconductor and its manufacturing method |
| US9011599B2 (en) * | 2010-07-14 | 2015-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of temperature determination for deposition reactors |
| CN103081080A (en) * | 2010-08-25 | 2013-05-01 | 日本碍子株式会社 | Epitaxial substrate for semiconductor element, semiconductor element, method for fabricating epitaxial substrate for semiconductor element, and method for fabricating semiconductor element |
| CN103063729A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Method for detecting epitaxial silicon defects |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| CN104576728A (en) * | 2013-10-10 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103605388A (en) * | 2013-10-25 | 2014-02-26 | 上海晶盟硅材料有限公司 | Method for detecting temperature of temperature field of epitaxial furnace platform through ion-implanted chip and method for correcting temperature field of epitaxial furnace platform through ion-implanted chip |
| CN103681240A (en) * | 2013-12-12 | 2014-03-26 | 杭州士兰集成电路有限公司 | Epitaxial temperature testing and monitoring structure and forming method |
| CN104810396A (en) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
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