CN103063729A - Method for detecting epitaxial silicon defects - Google Patents
Method for detecting epitaxial silicon defects Download PDFInfo
- Publication number
- CN103063729A CN103063729A CN2011103220438A CN201110322043A CN103063729A CN 103063729 A CN103063729 A CN 103063729A CN 2011103220438 A CN2011103220438 A CN 2011103220438A CN 201110322043 A CN201110322043 A CN 201110322043A CN 103063729 A CN103063729 A CN 103063729A
- Authority
- CN
- China
- Prior art keywords
- silicon chip
- silicon
- epitaxial
- thermal oxide
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a method for detecting epitaxial silicon defects. The method comprises the following steps of: growing thermal oxidation layers on an epitaxial layer of a silicon slice, wherein the epitaxial layer of the silicon slice and a silicon slice substrate are in a same type; injecting charges to the surface of the silicon slice, and measuring a surface voltage, thus obtaining the defect service life of a thermal oxidation layer on each part of the silicon slice and shallow thermal oxidation layers of an epitaxial layer interface; generating induced charges on the surface of the thermal oxidation layer, thus obtaining the recombination service life of the induced charge of each part of the silicon slice in a similar way; and if the defect service life of the shallow thermal oxidation layer of each part of the silicon slice is greater than a setting value, indicating the defect degree of the epitaxial layer of each part of the silicon slice by the length of the recombination service life of the induced charge of each part of the silicon slice. The method for detecting the epitaxial silicon defects provided by the invention can make a qualitative and quantitative judgment on the degrees and the positions of the defects of the epitaxial layers of the silicon slice, and thus the judgment is more exact and complete.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of method that detects the epitaxial silicon defective.
Background technology
Epitaxy technique is very important in semiconductor, and various high tension apparatus, high-frequency element all need to use epitaxy technique, as burial layer or improve the voltage breakdown etc. of bipolar device collector.Because in the technique that is widely used in numerous device keys of epitaxial loayer, so the quality of epitaxial loayer film is very important.
The quality of epitaxial loayer film can run into many-sided problem of being permitted usually, such as particle, defective etc.Wherein for the detection of defective owing to being the reflection of lattice level, and with silicon chip substrate be material of the same race, therefore be difficult to solve with common optical method measurement means.Usually for the evaluation of defective, mainly be by acid system corrosion after the thick epitaxial growth, then confirm at microscopically.Although this method is comparatively simple and clear, still exist some unavoidable problems.At first, the monitoring of acid corrosion law limitation is had relatively high expectations for the technician of operation, otherwise it is very accurate to be difficult to assurance.Secondly, acid corrosion is owned by France measures in the silicon chip destruction, and silicon chip can't continue to use after finishing.In addition, the problem that acid corrosion method also will face is exactly cannot the face distribution situation of a small amount of defective be detected.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that detects the epitaxial silicon defective, can be qualitative, quantitatively judge degree and position that silicon chip epitaxial loayer defective produces, and more accurate, more comprehensively.
For solving the problems of the technologies described above, the method for detection epitaxial silicon defective of the present invention may further comprise the steps:
One. in the silicon chip epitaxial loayer thermal oxide layer of growing, silicon chip epitaxial loayer and silicon chip substrate homotype;
Two. to the silicon chip surface iunjected charge, then obtain the thermal oxide layer of each position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface by measuring surface voltage;
Produce induced charge on the thermal oxide layer surface, obtain equally the induced charge recombination lifetime of each position of silicon chip by measuring surface voltage;
Three. if the thermal oxide superficial defects life-span of this each position of silicon chip is greater than setting value, then represents the defect level of the silicon chip epitaxial loayer of each position with the length of the induced charge recombination lifetime of each position on this silicon chip.
The thickness range of described thermal oxide layer is at 400 dusts～2500 dusts, and the film-forming temperature scope is 800 ℃～1200 ℃.
Institute's iunjected charge scope is-15e-06～15e-06 (C/CM
2).
The method of detection epitaxial silicon defective of the present invention, by the thicker and membranous preferably thermal oxide layer of growing at the silicon chip epitaxial loayer, make the superficial defects that brings owing to thermal oxide layer in minimum zone, when the thermal oxide superficial defects of each position of silicon chip hour, represent again the defect level of the silicon chip epitaxial loayer of this each position of silicon chip with the length of the induced charge recombination lifetime of each position of silicon chip.Because the thermal oxide superficial defects depends primarily on ripe thermal oxidation technology, general defective is few, thereby the length of the induced charge recombination lifetime of each position of silicon chip can represent the defect level of the silicon chip epitaxial loayer of this each position of silicon chip, the method of detection epitaxial silicon defective of the present invention, can detect respectively the defect level of the silicon chip epitaxial loayer of each position of silicon chip, can be qualitative, quantitatively judge degree and position that silicon chip epitaxial loayer defective produces, more accurate, more comprehensively.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment.
Fig. 1 is the method one embodiment process flow diagram of detection epitaxial silicon defective of the present invention;
Fig. 2 is at silicon chip epitaxial loayer growth thermal oxide layer schematic diagram;
Fig. 3 is the voltage schematic diagram over time of silicon chip one position.
Embodiment
Method one embodiment of detection epitaxial silicon defective of the present invention as Fig. 1 with shown in, may further comprise the steps:
One. at silicon chip epitaxial loayer 2 growth thermal oxide layers 3, silicon chip epitaxial loayer 2 and silicon chip substrate 1 homotype (be all N-type or be all the P type), as shown in Figure 2;
Two. to the silicon chip surface iunjected charge, then obtain the thermal oxide layer of each position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface by measuring surface voltage;
Produce induced charge on the thermal oxide layer surface, obtain equally the induced charge recombination lifetime of each position of silicon chip by measuring surface voltage;
Three. if the thermal oxide superficial defects life-span of this each position of silicon chip is greater than setting value, then represents the defect level of the silicon chip epitaxial loayer of each position with the length of the induced charge recombination lifetime of each position on this silicon chip.
One preferred embodiment:
The thickness range of described thermal oxide layer is at 400 dusts～2500 dusts, and the film-forming temperature scope is 800 ℃～1200 ℃;
Utilize the xenon lamp of Quantox board to produce induced charge on the thermal oxide layer surface;
Utilize Quantox to the accurate iunjected charge of silicon chip surface, better, institute's iunjected charge scope is-15e-06～15e-06 (C/CM
2);
Utilize voltage that Kelvin probe (Kelvin Probe) the induction test of Quantox board obtains each position of silicon chip surface over time;
According to the voltage of each position of silicon chip surface after producing induced charge on thermal oxide layer surface over time, obtain the induced charge recombination lifetime of this each position of silicon chip; The voltage of silicon chip one position over time as shown in Figure 3, the time period of the voltage acute variation in the dotted line i.e. the induced charge recombination lifetime of this this position of silicon chip;
According to the voltage of each position of silicon chip surface after the silicon chip surface iunjected charge over time, obtain the thermal oxide layer of this each position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface, the time period of silicon chip surface one position voltage acute variation i.e. the thermal oxide layer of this this position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface.
If the thermal oxide superficial defects life-span of this each position of silicon chip is greater than setting value (such as 500 microseconds), represent that then this silicon chip thermal oxide superficial defects is less, can represent with the length of the induced charge recombination lifetime of each position of silicon chip the defect level of the silicon chip epitaxial loayer of this each position of silicon chip.
As shown in table 1.The minimum thermal oxidation superficial defects life-span of each position of 3 silicon chips is all grown (greater than 500 microseconds), thereby can judge 3 silicon chips thermal oxide layer membranous all better, reliability is higher, can represent with the length of the induced charge recombination lifetime of each position on the silicon chip defect level of the silicon chip epitaxial loayer of each position.And standard film 1,2 and the length of the shortest induced charge recombination lifetime of defective sheet 3 comparatively significantly difference is arranged, very short (less than 800 microseconds) of the shortest induced charge recombination lifetime of defective sheet 3, thus can judge that defective sheet 3 silicon chip epitaxial loayers have open defect.
Table 1
The method of detection epitaxial silicon defective of the present invention, by the thicker and membranous preferably thermal oxide layer of growing at the silicon chip epitaxial loayer, make the superficial defects that brings owing to thermal oxide layer in minimum zone, when the thermal oxide superficial defects of each position of silicon chip hour, represent again the defect level of the silicon chip epitaxial loayer of this each position of silicon chip with the length of the induced charge recombination lifetime of each position of silicon chip.Because the thermal oxide superficial defects depends primarily on ripe thermal oxidation technology, general defective is few, thereby the length of the induced charge recombination lifetime of each position of silicon chip can represent the defect level of the silicon chip epitaxial loayer of this each position of silicon chip, the method of detection epitaxial silicon defective of the present invention, can detect respectively the defect level of the silicon chip epitaxial loayer of each position of silicon chip, can be qualitative, quantitatively judge degree and position that silicon chip epitaxial loayer defective produces, more accurate, more comprehensively.
The above only is the application's preferred embodiment, and is in order to limit the application, not all within the application's spirit and principle, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of the application's protection.
Claims (7)
1. a method that detects the epitaxial silicon defective is characterized in that, may further comprise the steps:
One. in the silicon chip epitaxial loayer thermal oxide layer of growing, silicon chip epitaxial loayer and silicon chip substrate homotype;
Two. to the silicon chip surface iunjected charge, then obtain the thermal oxide layer of each position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface by measuring surface voltage;
Produce induced charge on the thermal oxide layer surface, obtain equally the induced charge recombination lifetime of each position of silicon chip by measuring surface voltage;
Three. if the thermal oxide superficial defects life-span of this each position of silicon chip is greater than setting value, then represents the defect level of the silicon chip epitaxial loayer of each position with the length of the induced charge recombination lifetime of each position on this silicon chip.
2. the method for detection epitaxial silicon defective according to claim 1 is characterized in that, the thickness range of described thermal oxide layer is at 400 dusts～2500 dusts, and the film-forming temperature scope is 800 ℃～1200 ℃.
3. the method for detection epitaxial silicon defective according to claim 1 is characterized in that, institute's iunjected charge scope is-15e-06～15e-06 (C/CM
2).
4. the method for detection epitaxial silicon defective according to claim 1 is characterized in that, described setting value is 500 microseconds.
5. the method for detection epitaxial silicon defective according to claim 1 is characterized in that,
According to the voltage of each position of silicon chip surface after producing induced charge on thermal oxide layer surface over time, obtain the induced charge recombination lifetime of this each position of silicon chip;
According to the voltage of each position of silicon chip surface after the silicon chip surface iunjected charge over time, obtain the thermal oxide layer of this each position of silicon chip and the thermal oxide superficial defects life-span of epitaxial layer interface.
6. the method for detection epitaxial silicon defective according to claim 5 is characterized in that, utilizes xenon lamp to produce induced charge on the thermal oxide layer surface.
7. the method for detection epitaxial silicon defective according to claim 5 is characterized in that, utilizes Kelvin probe induction test to obtain the change in voltage of each position of silicon chip surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103220438A CN103063729A (en) | 2011-10-21 | 2011-10-21 | Method for detecting epitaxial silicon defects |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103220438A CN103063729A (en) | 2011-10-21 | 2011-10-21 | Method for detecting epitaxial silicon defects |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103063729A true CN103063729A (en) | 2013-04-24 |
Family
ID=48106441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103220438A Pending CN103063729A (en) | 2011-10-21 | 2011-10-21 | Method for detecting epitaxial silicon defects |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103063729A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107887287A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method of testing |
| CN109084957A (en) * | 2018-08-31 | 2018-12-25 | 华南理工大学 | The defects detection and color sorting process and its system of photovoltaic solar crystal-silicon battery slice |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007042950A (en) * | 2005-08-04 | 2007-02-15 | Sumco Corp | Quality evaluating method of epitaxial layer, quality evaluating method of soi (silicon on insulator) layer and manufacturing method of silicon wafer |
| KR100712721B1 (en) * | 2005-12-29 | 2007-05-04 | 주식회사 실트론 | Method of in-situ evaluating defects of a semiconductor epitaxial layer |
| JP2007158314A (en) * | 2005-11-10 | 2007-06-21 | Sumco Corp | Method for pretreating epitaxial layer, method for evaluating epitaxial layer, and apparatus for evaluating epitaxial layer |
| JP2007318029A (en) * | 2006-05-29 | 2007-12-06 | Central Res Inst Of Electric Power Ind | Crystal defect inspection method and crystal defect inspection apparatus of silicon carbide single-crystal wafer |
| CN101110379A (en) * | 2006-07-21 | 2008-01-23 | 上海华虹Nec电子有限公司 | Method for measuring silicon slice extension linear defect |
| KR20100033084A (en) * | 2008-09-19 | 2010-03-29 | 주식회사 실트론 | Evaluate method of defect in silicon epi layer |
| CN101957324A (en) * | 2009-07-16 | 2011-01-26 | 上海华虹Nec电子有限公司 | Method for detecting defects of SiGe epitaxy |
-
2011
- 2011-10-21 CN CN2011103220438A patent/CN103063729A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007042950A (en) * | 2005-08-04 | 2007-02-15 | Sumco Corp | Quality evaluating method of epitaxial layer, quality evaluating method of soi (silicon on insulator) layer and manufacturing method of silicon wafer |
| JP2007158314A (en) * | 2005-11-10 | 2007-06-21 | Sumco Corp | Method for pretreating epitaxial layer, method for evaluating epitaxial layer, and apparatus for evaluating epitaxial layer |
| KR100712721B1 (en) * | 2005-12-29 | 2007-05-04 | 주식회사 실트론 | Method of in-situ evaluating defects of a semiconductor epitaxial layer |
| JP2007318029A (en) * | 2006-05-29 | 2007-12-06 | Central Res Inst Of Electric Power Ind | Crystal defect inspection method and crystal defect inspection apparatus of silicon carbide single-crystal wafer |
| CN101110379A (en) * | 2006-07-21 | 2008-01-23 | 上海华虹Nec电子有限公司 | Method for measuring silicon slice extension linear defect |
| KR20100033084A (en) * | 2008-09-19 | 2010-03-29 | 주식회사 실트론 | Evaluate method of defect in silicon epi layer |
| CN101957324A (en) * | 2009-07-16 | 2011-01-26 | 上海华虹Nec电子有限公司 | Method for detecting defects of SiGe epitaxy |
Non-Patent Citations (3)
| Title |
|---|
| D. K. SCHRODER ET AL: "Silicon Epitaxial Layer Recombination and Generation Lifetime Characterization", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》, vol. 50, no. 4, 30 April 2003 (2003-04-30), XP011072611 * |
| J. E. PARK ET AL: "Silicon Epitaxial Layer Lifetime Characterization", 《JOURNAL OF THE ELECTROCHEMICAL SOCIETY》, vol. 148, no. 8, 3 July 2001 (2001-07-03) * |
| 邓江东: "硅(外延)片表面结构缺陷的光学无损检测", 《半导体学报》, vol. 17, no. 5, 31 May 1996 (1996-05-31) * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107887287A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method of testing |
| CN107887287B (en) * | 2016-09-30 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | Test method |
| CN109084957A (en) * | 2018-08-31 | 2018-12-25 | 华南理工大学 | The defects detection and color sorting process and its system of photovoltaic solar crystal-silicon battery slice |
| CN109084957B (en) * | 2018-08-31 | 2024-03-19 | 华南理工大学 | Defect detection and color sorting method and system for photovoltaic solar crystalline silicon cell |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1932496B (en) | Silicon wafer surface defect evaluation method | |
| US10513798B2 (en) | Method for determining defect region | |
| US8817251B2 (en) | Defect inspection method | |
| CN103063729A (en) | Method for detecting epitaxial silicon defects | |
| CN105552003B (en) | Resistivity monitoring method in the production of p-type epitaxial wafer | |
| JP5439752B2 (en) | Contamination detection monitor wafer, contamination detection method, and epitaxial wafer manufacturing method | |
| JP5018682B2 (en) | Silicon substrate evaluation method, contamination detection method, and epitaxial substrate manufacturing method | |
| US9500694B2 (en) | Method for evaluating wafer defects | |
| CN110047768A (en) | Test condition determination device and test condition determining method | |
| CN103094143B (en) | ion implantation monitoring method | |
| JP2010028011A (en) | Method for measuring thickness of epitaxial layer, method for manufacturing epitaxial wafer and method for controlling manufacturing process of epitaxial wafer | |
| US10983158B2 (en) | Method for evaluating crystal defects | |
| US20230118491A1 (en) | Method for evaluating of defect area of wafer | |
| JPH0862122A (en) | Method for evaluating oxygen precipitation defect density of silicon water | |
| JP6003447B2 (en) | Method for evaluating metal contamination of semiconductor substrate and method for manufacturing semiconductor substrate | |
| KR101302587B1 (en) | Evaluation method for minority carrier lifetime in silicon wafer | |
| US20070069760A1 (en) | System and method for characterizing silicon wafers | |
| US20210131800A1 (en) | Method for manufacturing semiconductor structure, inspection method, and semiconductor structure | |
| KR101464567B1 (en) | A method for obtaining an information of thermal history in cooling ingot | |
| Broisch et al. | Determination of the dopant-related base resistivity in presence of thermal donors | |
| KR102037744B1 (en) | Method for evaluating wafer | |
| JP2017174864A (en) | Methods for evaluating and manufacturing epitaxial wafer | |
| JP6520782B2 (en) | Evaluation method and manufacturing method of epitaxial wafer | |
| CN117790345A (en) | Method for monitoring silicon carbide ion implantation effect | |
| CN100514058C (en) | Method for sensing stability of acid tank and reaction tank |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206 No. 1188, Dongchuan Road, Shanghai, Pudong New Area Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130424 |