CN106409675A - Production method for depletion mode power transistor - Google Patents
Production method for depletion mode power transistor Download PDFInfo
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- CN106409675A CN106409675A CN201610812147.XA CN201610812147A CN106409675A CN 106409675 A CN106409675 A CN 106409675A CN 201610812147 A CN201610812147 A CN 201610812147A CN 106409675 A CN106409675 A CN 106409675A
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- conductive type
- power transistor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000002347 injection Methods 0.000 claims abstract description 44
- 239000007924 injection Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 44
- 150000002500 ions Chemical class 0.000 claims abstract description 32
- 238000001259 photo etching Methods 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 50
- 229910052760 oxygen Inorganic materials 0.000 claims description 50
- 239000001301 oxygen Substances 0.000 claims description 50
- 238000009792 diffusion process Methods 0.000 claims description 34
- 238000002513 implantation Methods 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 230000005669 field effect Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000003892 spreading Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 8
- 230000001413 cellular effect Effects 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- -1 phosphonium ion Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention relates to a production method for a depletion mode power transistor. The method comprises the steps of forming field oxide layers on a first conductive type substrate on a front face of a wafer; carrying out second conductive type photoetching and etching; injecting second conductive type ions and forming second conductive type areas in the first conductive substrate; growing second field oxide layers on the front face of the wafer; carrying out second conductive type well photoetching and etching; injecting the second conductive type ions and forming second conductive type wells at two sides of the second conductive type areas; carrying out depletion layer photoetching and etching; injecting first conductive type ions and forming depletion layers at two sides of the second conductive type areas; forming polycrystalline silicon gates and polycrystalline silicon field plates on the front face of the wafer; and carrying out self-alignment injection on the first conductive type ions by taking the polycrystalline silicon gates and the second field oxide layers as masks, and forming first conductive type areas in the second conductive type wells. According to the method, through utilization of the second field oxide layers as the masks for carrying out the self-alignment injection on the first conductive type ions, a photoetching process can be eliminated.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of manufacture method of depletion type power transistor.
Background technology
Field-effect transistor is divided into depletion type (depletion mode) and two kinds of enhancement mode (enhancement mode).
Depletion mode fet exist in zero gate bias raceway groove, can be conductive；Enhancement mode field effect transistor is in zero gate bias
When do not exist raceway groove, can not be conductive.The cut-in voltage of depletion type N-channel MOS FET (metal oxide semiconductor field effect tube)
VTHIt is negative value, the V of enhancement mode N-channel MOS FETTHBe on the occasion of.
Even if depletion type MOS FET changes the impurity concentration being doped to passage in the fabrication process so that grid does not power up
Pressure, conducting channel there is also.If it is intended to closing raceway groove, then must apply negative voltage (for N-channel MOS FET) in grid.Consumption
Type MOSFET is usually applied to the switch of " normally-off " (normally-off) to the greatest extent, and enhancement mode MOSFET is then used in " open type "
(normally-on) switch.
The weight that the design of depletion type VDMOS (vertical double-diffusion metal-oxide-semiconductor field effect transistor) should solve with manufacture
Point problem is how to carry out manufacturing and designing of depletion layer.Due to there is no depletion layer in enhancement mode VDMOS, therefore can be in the system of polycrystalline
Carry out p-well (P-) injection, N+ injection and P+ injection, and the presence due to depletion layer, this manufacturing process is not suitable for consuming after making
The manufacture of most type VDMOS.
Content of the invention
Based on this it is necessary to provide a kind of manufacture method of depletion type power transistor.
A kind of manufacture method of depletion type power transistor, described depletion type power transistor includes active area and terminal
Area, methods described includes：First oxygen layer is formed on the first conductivity type substrate of wafer frontside；Carry out the second conduction type
Photoetching and etching, first oxygen layer that the second conduction type is injected at window etches away；By described second conduction type note
Enter window to inject the second conductive type ion and spread, in described first conductivity type substrate, form the second conductivity regions；
It is less than second oxygen layer of described first oxygen layer in described wafer frontside growth thickness；Carry out the second conductive type of trap photoetching and
Etching, first oxygen layer that the second conductive type of trap of described active area is injected at window etches away；Lead by described second
Electric type trap injection window injects the second conductive type ion and spreads, and forms second in described second conductivity regions both sides and leads
Electric type trap, and the doping content of described second conductive type of trap is less than the doping content of described second conductivity regions；Carry out
Depletion layer photoetching and etching, first oxygen layer that the depletion layer of described active area is injected at window etches away；By described consumption
Layer injection window injects the first conductive type ion and spreads to the greatest extent, forms depletion layer and expansion in described second conductivity regions both sides
After dissipating, the depth of depletion layer is less than the depth of described second conductive type of trap；Form polysilicon gate and many in described wafer frontside
Crystal silicon field plate；The autoregistration injection of the first conductive type ion is carried out for mask with described polysilicon gate and second oxygen layer,
Form the first conductivity regions in described second conductive type of trap；Carry out dielectric layer, contact hole and just in described wafer frontside
The preparation of face metal level；Carry out the back process of described depletion type power transistor；Described first conduction type and the second conduction
The conduction type of type is contrary.
Wherein in an embodiment, the described step carrying out the second conduction type photoetching and etching, is will be described active
First oxygen layer that second conduction type of area and termination environment injects at window etches away；The substrate bag of described first conduction type
Include substrate layer and epitaxial layer, the described step that first oxygen layer is formed on the first conductivity type substrate of wafer frontside, be
Described epi-layer surface forms first oxygen layer, described form the second conductivity regions in the first conductivity type substrate, be
Form the second conductivity regions in the epitaxial layer of active area and termination environment.
Wherein in an embodiment, described depletion type power transistor is plane grid-type vertical bilateral diffusion metallic oxide
Semiconductor field.
Wherein in an embodiment, described first conduction type is N-type, and described second conduction type is p-type.
Wherein in an embodiment, described window is injected by described depletion layer inject the first conductive type ion expanding
Scattered step, is by N- arsenic ion and injects and spread.
Wherein in an embodiment, described carry out in the step that N- arsenic ion injects and spreads, implantation dosage is
1E11cm-2—5E12cm-2, Implantation Energy is 30Kev 80Kev, and diffusion temperature is 900 DEG C 1000 DEG C, and diffusion time is
100 minutes 250 minutes.
Wherein in an embodiment, described by described second conduction type inject window inject the second conduction type from
Son the step spreading, are by P+ and inject and spread, and implantation dosage is 1E14cm-2—1E15cm-2, Implantation Energy is
60Kev 100Kev, diffusion temperature is 1000 DEG C 1175 DEG C, and diffusion time is 90 minutes 150 minutes.
Wherein in an embodiment, described described wafer frontside growth thickness be less than described first oxygen layer second
The step of field oxygen layer, is second oxygen layer that growth thickness is 4000 angstroms 6000 angstroms.
Wherein in an embodiment, described described wafer frontside growth thickness be less than described first oxygen layer second
The step of field oxygen layer, is the technique using dry oxygen-wet oxygen-dry oxygen.
Wherein in an embodiment, described to carry out first with described polysilicon gate and second oxygen layer for mask conductive
In the step of autoregistration injection of types of ion, implantation dosage is 5E15cm-2—1.3E16cm-2, Implantation Energy is 100Kev
130Kev.
The manufacture method of above-mentioned depletion type power transistor, by the use of second oxygen layer as carrying out the first conductive type ion
Autoregistration injection when mask, one photo-mask process can be saved.Finished laggard in polysilicon preparation using self-registered technology
The injection of row first conductive type ion (rather than in the note of the second conductive type of trap as conventional enhanced power transistor
Carry out after entering and spreading), it is possible to obtain longer depletion layer channel length, make device be easier to press from both sides under negative grid voltage
Disconnected.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
In required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also be attached according to these
Figure obtains the accompanying drawing of other embodiment.
Fig. 1 is the schematic diagram of the active area of depletion type power transistor and termination environment in an embodiment；
Fig. 2 is the flow chart of the manufacture method of depletion type power transistor in an embodiment；
Fig. 3 is termination environment and active area carries out the generalized section that P+ injects and spreads simultaneously；
Fig. 4 a～4g is the generalized section using the depletion type power transistor in the fabrication process of method shown in Fig. 2；
Fig. 5 is the overall generalized section of device cellular after the completion of step S310；
Fig. 6 is the cut-in voltage V of N-channel depletion type VDMOS being produced using method shown in Fig. 2THEmulation schematic diagram.
Specific embodiment
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.In accompanying drawing
Give the first-selected embodiment of the present invention.But, the present invention can realize in many different forms however it is not limited to this paper institute
The embodiment of description.On the contrary, provide the purpose of these embodiments be make more thoroughly comprehensive to the disclosure.
Unless otherwise defined, all of technology used herein and scientific terminology and the technical field belonging to the present invention
The implication that technical staff is generally understood that is identical.The term being used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body is it is not intended that in limiting the present invention.Term as used herein " and/or " include one or more phases
The arbitrary and all of combination of the Listed Items closing.
The technical words that semiconductor applications vocabulary used herein is commonly used for those skilled in the art, such as p-type
And N-type impurity, for distinguishing doping content, simply P+ type is represented the p-type of heavy dopant concentration, the P of doping content in p-type representative
Type, P-type represents the p-type that concentration is lightly doped, and N+ type represents the N-type of heavy dopant concentration, the N-type of doping content, N- in N-type representative
Type represents the N-type that concentration is lightly doped.
Referring to Fig. 1, it includes active area 100 and the termination environment 200 of active area 100 periphery.Fig. 2 is to exhaust in an embodiment
The flow chart of the manufacture method of type power transistor, comprises the steps：
S110, forms first oxygen layer in the first conductivity type substrate of wafer frontside.
In the present embodiment, the first conduction type is N-type, and correspondingly, the second conduction type is p-type.Substrate includes N+ lining
The N- epitaxial layer 10 that on bottom 90 and N+ substrate layer 90, extension obtains, referring to Fig. 3.With the plane grid-type of depletion type in the present embodiment
It is introduced as a example the manufacture process of vertical double-diffusion metal-oxide-semiconductor field effect transistor.It should be understood that the present invention is same
Sample is applied to the other kinds of depletion type power transistor of manufacture, but traditional trench gate depletion type MOS FET is due on silicon chip
The technology difficulty carrying out etching groove is big, particularly extremely difficult in the etching of channel bottom circular arc type pattern.Entered using planar technology
The manufacture of row depletion type VDMOS, compared with groove-shaped technique, greatly reduces technology difficulty, is conducive to the system of depletion type VDMOS
Make and promote.
S120, carries out the second conduction type photoetching and etching.
Carry out photoetching in wafer frontside coating photoresist, need after photoetching to form the photoresist quilt above the position in P+ area 22
Dissolving, forms P+ injection window, and first oxygen layer 32 that after etching, P+ injects at window is etched away.
Conventional enhancement mode VDMOS is to carry out P+ injection after the N+ injection of active area, to increase avalanche capability EAS, prevents
Only device occurs breech lock to lead to overheated because electric current is excessive and burn.Mesohigh enhancement mode field effect transistor is during fabrication usually
First carry out the P+ injection of termination environment and spread, after carry out the P+ injection of active area and spread, P+ injection technology step is more.At this
In embodiment, active area carried out P+ injection and diffusion with termination environment before p-well injection simultaneously, the P+ injection of terminal field limiting ring with
The P+ of cellular completes in same photoetching, etching and implantation step, increases avalanche capability EAS of device, and decreases system
The operation made, can save manufacturing cost.
S130, injection the second conductive type ion simultaneously spreads, and forms the second conduction type in the first conductivity type substrate
Area.
In the present embodiment, it is window implanting p-type ion to be injected by P+ and carries out thermal diffusion, shape in N- epitaxial layer 10
Become P+ area 22.Fig. 3 is termination environment and active area carries out the generalized section that P+ injects and spreads simultaneously.
S140, grows second oxygen layer in wafer frontside.
It is less than second oxygen layer 34 of first oxygen layer 32 in wafer frontside growth thickness.Fig. 4 a is using said method system
Make the generalized section of device cellular after the completion of step S140 during depletion type power transistor.May be appreciated.Giving birth to
During long second oxygen layer 34, the surface of first oxygen layer 32 equally also can grow oxide layer, be equivalent to first oxygen layer 32 and added
This is omitted in Fig. 4 a by thickness.
S150, carries out the second conductive type of trap photoetching and etching.
Coat photoresist 41 in wafer frontside and carry out photoetching, need after photoetching to form the photoresist above the position of p-well 24
41 are dissolved, and form p-well injection window, as shown in Figure 4 b.The field oxide that after etching, p-well is injected at window is etched away.
S160, injection the second conductive type ion simultaneously spreads, and forms the second conduction type in the second conductivity regions both sides
Trap.
In the present embodiment, it is window implanting p-type ion to be injected by p-well and carries out thermal diffusion, in P+ area 22 both sides shape
Become p-well 24.Fig. 4 c is the generalized section of device cellular after the completion of step S160.
S170, carries out depletion layer photoetching and etching.
Coat photoresist 43 in wafer frontside and carry out photoetching, need after photoetching to form the photoetching above the position of depletion layer 25
Glue 43 is dissolved, and forms depletion layer injection window, as shown in figure 4d.
S180, injection the first conductive type ion simultaneously spreads, and forms depletion layer in the second conductivity regions both sides.
In the present embodiment, it is to inject window by depletion layer to inject N-type ion and carry out thermal diffusion, the two of P+ area 22
P-well 24 top of side forms the depletion layer 25 of N-.The Main Function of depletion layer 25 is the formation electric current when power transistor is opened
Passage；And when power transistor turns off because the raceway groove of depletion layer 25 is very shallow it is easy to pinch off.When being spread due to p-well, in N-
Epitaxial layer 10 surface, the doping content of p-well near P+ area 22 position to the position (i.e. inside-out) away from P+ area 22 by
Decrescence little, therefore the thickness of depletion layer 25 is also gradually thickening inside-out, as shown in fig 4e.
If as traditional enhancement mode VDMOS carries out N+ injection after p-well injection with diffusion, depletion layer is then adopted to note again
Enter technique and carry out N- injection, the channel length of depletion layer is just shorter, make device be more difficult to pinch off under negative grid voltage.Therefore on
State in embodiment and be adjusted to after depletion layer N- injection carry out by N+ injection.After above-mentioned technique completes, just complete p-type in cellular
The injection of N-type ion (N-) and diffusion in ion (including P+ and P-) and depletion layer.Next proceed to introduce follow-up manufacture stream
Journey.
S210, forms polysilicon gate and polysilicon field plate in wafer frontside.
Referring to Fig. 4 f, depletion layer 25 preparation carries out the growth of grid oxygen 36, the polysilicon gate 52 of active area and terminal after finishing
The preparation of the polysilicon field plate (not showing in Fig. 4 f) in area.
S220, carries out the autoregistration injection of the first conductive type ion, forms first conductive in the second conductive type of trap
Class area.
The mask being injected for autoregistration with polysilicon gate 52 and second oxygen layer 34, forms N+ area 27 in p-well 24.N+
The junction depth in area 27 is more than the junction depth of depletion layer 25.Fig. 4 g is the generalized section of device cellular after the completion of step S220, wherein N+
Area 27, depletion layer 25 and N- epitaxial layer 10 are n-type doping, therefore it are not demarcated.
S230, carries out the preparation of dielectric layer, contact hole and front metal layer in wafer frontside.
S310, carries out the back process of depletion type power transistor.
Fig. 5 is the overall generalized section of device cellular after the completion of step S310.
The manufacture method of above-mentioned depletion type power transistor, by the use of second oxygen layer as carrying out the first conductive type ion
Autoregistration injection when mask, one photo-mask process can be saved.Finished laggard in polysilicon preparation using self-registered technology
The injection of row first conductive type ion (rather than in the note of the second conductive type of trap as conventional enhanced power transistor
Carry out after entering and spreading), it is possible to obtain longer depletion layer channel length, make device be easier to press from both sides under negative grid voltage
Disconnected.
Wherein in an embodiment, the implantation dosage of step S130 is 1E14cm-2—1E15cm-2, Implantation Energy is
60Kev 100Kev, diffusion temperature is 1000 DEG C 1175 DEG C, and diffusion time is 90 minutes 150 minutes.
Wherein in an embodiment, the thickness of second oxygen layer 34 of step S140 growth is 4000 angstroms 6000 angstroms,
Thermally grown temperature is 950 DEG C 1050 DEG C.Preferably, the technique of dry oxygen-wet oxygen-dry oxygen can be adopted to grow second oxygen layer
34.
Wherein in an embodiment, the implantation dosage of step S160 is 3E13cm-2—1E14cm-2, Implantation Energy is
60Kev 80Kev, diffusion temperature is 1100 DEG C 1150 DEG C, and diffusion time is 60 minutes 150 minutes.
Wherein in an embodiment, step S180 is by the injection of N- arsenic ion.Using the benefit that arsenic ion injects it is
The diffusion coefficient very little of arsenic, the thickness very little of depletion layer 25 so after thermal diffusion, it is easy to the switch control to depletion type VDMOS
System, makes the cut-in voltage V of deviceTHEasily controllable.After the injection of depletion layer can be injected it is also possible to remove photoresist for band glue (photoresist)
Injected.
Wherein in an embodiment, the implantation dosage of step S180 is 1E11cm-2—5E12cm-2, Implantation Energy is
30Kev 80Kev, diffusion temperature is 900 DEG C 1000 DEG C, and diffusion time is 100 minutes 250 minutes.
Wherein in an embodiment, the gate oxide growth of step S210 adopts the technique of dry oxygen-wet oxygen-dry oxygen, oxidation temperature
Spend for 800 DEG C 1000 DEG C.Then carry out polycrystalline silicon deposit, N-type ion (such as phosphonium ion) diffusion of polysilicon (or N-type from
Son injection, such as phosphonium ion injection), polysilicon photoetching and etching polysilicon.The polysilicon thickness of deposit is 6000 angstrom 10000
Angstrom, the diffusion temperature of polysilicon phosphorus diffusion is 800 DEG C 1000 DEG C, and the square resistance of polysilicon is 10 Ω/ -25 Ω/.
Wherein in an embodiment, the implantation dosage of step S220 is 5E15cm-2—1.3E16cm-2, Implantation Energy is
100Kev—130Kev.Because phosphorus diffusion velocity is very fast, wherein in an embodiment, the injection of step S220 can be not be used in
Carry out N+ phosphorus diffusion immediately afterwards, but be diffused using the pyroprocess in subsequent fabrication steps.In the present embodiment, step
The diffusion temperature of the N+ diffusion of S220 is 900 DEG C 1000 DEG C, and diffusion time is 90 minutes 120 minutes.
Wherein in an embodiment, step S230 dielectric layer deposited 62 is using low-pressure chemical vapor phase deposition (LPCVD)
Technique, the dielectric layer 62 of deposit can be PSG (phosphorosilicate glass), or USG (not glass of p-doped) plus PSG, dielectric layer 62 total
Thickness is 10000 angstroms 20000 angstroms.The temperature of dielectric layer 62 backflow is 900 DEG C 1000 DEG C, and the purpose of backflow is to make dielectric layer
62 is smooth and fine and close.Carry out contact hole photoetching and etching after dielectric layer 62 backflow, then carry out metal sputtering and form front metal
Layer 72.
Wherein in an embodiment, step S310 specifically includes the thinning back side of wafer, back side injection and back metal
The step changed, forms metal layer on back 74.
Fig. 6 is the unlatching of N-channel depletion type VDMOS being produced using the manufacture method of above-mentioned depletion type power transistor
Voltage VTHEmulation schematic diagram, as can be seen from the figure VTHIt is equal to -2V.
The manufacture method of above-mentioned depletion type power transistor, taking N-channel depletion type VDMOS is as a example carried out to manufacture process
Introduce.For P-channel depletion type VDMOS, its manufacturing theory is identical.Material therefor is p-type epitaxial wafer, N trap (N-) and N+
Area injects for boron ion and is formed for phosphorus injection or arsenic injection, P- depletion layer.
Embodiment described above only have expressed the several embodiments of the present invention, and its description is more concrete and detailed, but simultaneously
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
Say, without departing from the inventive concept of the premise, some deformation can also be made and improve, these broadly fall into the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be defined by claims.
Claims (10)
1. a kind of manufacture method of depletion type power transistor, described depletion type power transistor includes active area and termination environment,
It is characterized in that, methods described includes：
First oxygen layer is formed on the first conductivity type substrate of wafer frontside；
Carry out the second conduction type photoetching and etching, first oxygen layer that the second conduction type is injected at window etches away；
Inject window by described second conduction type to inject the second conductive type ion and spread, in described first conduction type
Form the second conductivity regions in substrate；
It is less than second oxygen layer of described first oxygen layer in described wafer frontside growth thickness；
Carry out the second conductive type of trap photoetching and etching, the second conductive type of trap of described active area is injected first at window
Field oxygen layer etches away；
Inject window by described second conductive type of trap to inject the second conductive type ion and spread, in described second conductive-type
Type area both sides form the second conductive type of trap, and the doping content of described second conductive type of trap is less than described second conduction type
The doping content in area；
Carry out depletion layer photoetching and etching, first oxygen layer that the depletion layer of described active area is injected at window etches away；
Inject window by described depletion layer to inject the first conductive type ion and spread, in described second conductivity regions both sides
After forming depletion layer and spreading, the depth of depletion layer is less than the depth of described second conductive type of trap；
Form polysilicon gate and polysilicon field plate in described wafer frontside；
The autoregistration injection of the first conductive type ion is carried out for mask with described polysilicon gate and second oxygen layer, described
Form the first conductivity regions in second conductive type of trap；
Carry out the preparation of dielectric layer, contact hole and front metal layer in described wafer frontside；
Carry out the back process of described depletion type power transistor；Described first conduction type and the conductive-type of the second conduction type
Type is contrary.
2. the manufacture method of depletion type power transistor according to claim 1 is it is characterised in that described carry out second and lead
The step with etching for the electric type photoetching, is first injecting the second conduction type of described active area and termination environment at window
Oxygen layer etches away；The substrate of described first conduction type includes substrate layer and epitaxial layer, described the first conduction in wafer frontside
The step forming first oxygen layer in type substrates, is to form first oxygen layer in described epi-layer surface, described leads first
Form the second conductivity regions in electric type substrates, be to form the second conduction type in the epitaxial layer of active area and termination environment
Area.
3. the manufacture method of depletion type power transistor according to claim 1 is it is characterised in that described depletion type power
Transistor is plane grid-type vertical double-diffusion metal-oxide-semiconductor field effect transistor.
4. the manufacture method of depletion type power transistor according to claim 1 is it is characterised in that described first conductive-type
Type is N-type, and described second conduction type is p-type.
5. depletion type power transistor according to claim 4 manufacture method it is characterised in that described by described consumption
Layer injects window and injects the first conductive type ion the step spreading to the greatest extent, is by N- arsenic ion and injects and spread.
6. depletion type power transistor according to claim 5 manufacture method it is characterised in that described carry out N- arsenic from
In the step that son injects and spreads, implantation dosage is 1E11cm-2—5E12cm-2, Implantation Energy is 30Kev 80Kev, diffusion
Temperature is 900 DEG C 1000 DEG C, and diffusion time is 100 minutes 250 minutes.
7. depletion type power transistor according to claim 4 manufacture method it is characterised in that described by described
Two conduction types inject window and inject the second conductive type ion the step spreading, and are by P+ and inject and spread, injectant
Measure as 1E14cm-2—1E15cm-2, Implantation Energy is 60Kev 100Kev, and diffusion temperature is 1000 DEG C 1175 DEG C, during diffusion
Between be 90 minutes 150 minutes.
8. depletion type power transistor according to claim 1 manufacture method it is characterised in that described in described wafer
Front growth thickness be less than described first oxygen layer second oxygen layer step, be growth thickness be 4000 angstroms 6000 angstroms
Second oxygen layer.
9. the depletion type power transistor according to claim 1 or 8 manufacture method it is characterised in that described described
The step that wafer frontside growth thickness is less than second oxygen layer of described first oxygen layer, is the work using dry oxygen-wet oxygen-dry oxygen
Skill.
10. depletion type power transistor according to claim 1 manufacture method it is characterised in that described with described many
Polysilicon gate and second oxygen layer are carried out for mask in the step of autoregistration injection of the first conductive type ion, and implantation dosage is
5E15cm-2—1.3E16cm-2, Implantation Energy is 100Kev 130Kev.
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| CN108198759A (en) * | 2017-12-04 | 2018-06-22 | 重庆中科渝芯电子有限公司 | A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen |
| CN109244123A (en) * | 2018-09-21 | 2019-01-18 | 无锡新洁能股份有限公司 | Depletion type MOS FET device and its manufacturing method |
| CN110176401A (en) * | 2019-06-13 | 2019-08-27 | 深圳市锐骏半导体股份有限公司 | A method of reducing VDMOS production cost |
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| CN109244123B (en) * | 2018-09-21 | 2024-02-09 | 无锡新洁能股份有限公司 | Depletion type MOSFET device and manufacturing method thereof |
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