CN111244157B - Lateral semiconductor device and manufacturing method thereof - Google Patents

Lateral semiconductor device and manufacturing method thereof Download PDF

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CN111244157B
CN111244157B CN202010066930.2A CN202010066930A CN111244157B CN 111244157 B CN111244157 B CN 111244157B CN 202010066930 A CN202010066930 A CN 202010066930A CN 111244157 B CN111244157 B CN 111244157B
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CN111244157A (en
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胡浩
朱斌
陈荣昕
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University of Electronic Science and Technology of China
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Abstract

A horizontal semiconductor device and a manufacturing process thereof belong to the field of semiconductor devices. The semiconductor device comprises a first conductive type semiconductor substrate, a second conductive type doping region, a first semiconductor type doping region, a first conductive type heavily doping region, a second conductive type heavily doping source region, a second conductive type heavily doping drain region, a source S, a grid G and a drain D, wherein a plurality of strip-shaped first conductive type doping regions which are located on the same horizontal plane are arranged inside the second conductive type doping region, one side of each first conductive type doping region is connected with the first conductive type semiconductor substrate, and the other side of each first conductive type doping region is located inside the second conductive type doping region. The horizontal semiconductor device provided by the invention reduces the local surface electric field intensity of the device, improves the withstand voltage of the device, and has smaller specific on-resistance and larger on-current density.

Description

Lateral semiconductor device and manufacturing method thereof
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a transverse semiconductor device and a manufacturing process thereof.
Background
In the semiconductor technology industry, power electronic devices, especially high-voltage devices, need to be artificially provided with a low-doped region in order to improve the surface breakdown voltage, so that the electric field near the surface of a planar p-n junction is uniformly distributed and weakened.
RESURF technology, i.e., surface field reduction technology, is proposed in the literature (j.a. applications and h.m.j.vaes, "High voltage thin layer devices (RESURF devices)", IEDM tech digest, pp.238-241 (1979)). The technology can reduce the surface electric field of the transverse device, improve the breakdown voltage of the device, and enable the transverse device to have higher drift region doping concentration, thereby reducing the on-resistance of the device. In order to further improve the current capability of a lateral device such as an N-type LDMOS, the document (d.r.disney, et al., "a new 800V lateral MOSFET with reduced reduction circuits", proc.of ISPSD, pp.399-402(2001)) discloses a device structure in which the surface field strength of the device is reduced by forming P-type doped regions on and in the drift region, as shown in fig. 1, when the device is turned off, the P-type substrate and the N-type drift region are mutually depleted. However, because the distance between the P-type buried layer 3 and Pbody is too narrow, a large resistance exists at this position to prevent current from entering the lower-layer drift region during conduction, so that two thirds of current must flow into a channel from between the P-type buried layer and Pbody when the device is conducted, which results in too narrow current conduction path of the device and prevents the current capability of the device from being further improved; moreover, since the P buried layer is floating potential, if the distance between the P type buried layer and Pbody is increased to reduce the resistance of the gap, the potential of the P buried layer at the time of withstand voltage is increased, so that the electric field peak appears on the gate field plate on the surface of the device, and the withstand voltage of the device is damaged.
Disclosure of Invention
The present invention is directed to a lateral semiconductor device and a method for manufacturing the same, which has a smaller specific on-resistance and a larger on-current density.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a lateral semiconductor device comprises a first conductivity type semiconductor substrate 1, a second conductivity type doped region 2 on one side of the first conductivity type semiconductor substrate, a first conductivity type doped region 4 on the other side of the first conductivity type semiconductor substrate, a first conductivity type heavily doped region 5 and a second conductivity type heavily doped source region 6 in the first conductivity type doped region 4, a second conductivity type heavily doped drain region 7 in the second conductivity type doped region 2, a source S on the first conductivity type heavily doped region 5 and the second conductivity type heavily doped source region 6, a gate oxide and a gate G on the first conductivity type doped region 4, and a drain D on the second conductivity type heavily doped drain region 7, wherein a plurality of regions, a gate G, a plurality of regions, a plurality of a, And the strip-shaped first conduction type doped region 3 is connected with the first conduction type semiconductor substrate 1 at one side, and is positioned in the second conduction type doped region 2at the other side.
Further, the thickness of the plurality of strip-shaped first conductivity-type doped regions 3 and the distance between adjacent strip-shaped first conductivity-type doped regions are adjusted according to the proportion of the doping impurity dose of the strip-shaped first conductivity-type doped regions to the doping impurity dose of the second conductivity-type doped regions between the strip-shaped first conductivity-type doped regions.
Further, suppose that the dosage of ionized impurities exhausted by the single-side abrupt parallel plane junction made by the same substrate under the highest reverse voltage is D0Then, the impurity dose at which the first conductivity type semiconductor substrate 1 is depleted is D0The ionized impurity dose of the first conductivity type doped region 3 is 4D0For the second conductivity type doped region 2, the ionized impurity dose of the region between the first conductivity type semiconductor substrate 1 and the first conductivity type doped region 3 is 2D0The ionized impurity dose of the region between the adjacent first conductivity type doped regions 3 is 2D0The ionized impurity dose of the region between the upper surfaces of the first conductivity type doped region 3 and the second conductivity type doped region 2 is D0。
A lateral semiconductor device, as shown in FIG. 2, comprises a P-type substrate 1, an N-type doped region 2 located on the upper and right sides of the P-type substrate 1, a first P-type doped region 4 located on the upper and left sides of the P-type substrate, the N-type doped region 2 adjacent to the first P-type doped region 4, a P-type heavily doped region 5 and an N-type heavily doped source region 6 located in the first P-type doped region 4, an N-type heavily doped drain region 7 located in the N-type doped region 2, a source S located on the P-type heavily doped region 5 and the N-type heavily doped source region 6, a gate oxide and a gate G located on the first P-type doped region 4, and a drain D located on the N-type heavily doped drain region 7, wherein a plurality of strip-shaped second P-type doped regions 3 located on the same horizontal plane are arranged in the N-type doped region 2, and one side of the second P-type doped regions 3 is connected to the P-type substrate, the other side is located inside the N-type doped region 2.
Further, suppose that the dosage of ionized impurities exhausted by the single-side abrupt parallel plane junction made by the same substrate under the highest reverse voltage is D0The dosage of the impurity with which the P-type substrate 1 is depleted is D0The ionized impurity dose of the second P-type doped region 3 is 4D0For the N-type doped region 2, the ionized impurity dose of the region between the P-type substrate 1 and the second P-type doped region 3 is 2D0The ionized impurity dose of the region 8 between the adjacent second P-type doped regions 3 is 2D0The ionized impurity dose of the region between the second P-type doped region 3 and the upper surface of the N-type doped region 2 is D0。
Preferably, the width of the strip-shaped second P-type doped region 3 in the Z direction is equal to the distance between two adjacent strip-shaped second P-type doped regions 3.
When the grid of the transverse semiconductor device is turned off, the N-type region 8 between the N-type doped region 2 and the adjacent second P-type doped region 3, the P-type substrate 1 and the second P-type doped region 3 are mutually and completely depleted, so that the surface voltage-resistant region of the transverse semiconductor device has the maximum depletion layer width, the local surface electric field intensity is reduced, and the integral breakdown voltage of the device is improved.
When the grid of the lateral semiconductor device is opened, the second P-type doped regions 3 are mutually independent strips instead of being communicated, and the N-type region 8 sandwiched between two adjacent second P-type doped regions 3 can be doped higher than the N-type doped region 2, so that the lateral semiconductor device has a wider current conduction path and stronger current conduction capability.
A method of fabricating a lateral semiconductor device, comprising the steps of:
step 1, preparing an N-type substrate or a P-type substrate, wherein the resistivity of the substrate is 10-200 ohm cm;
step 2, forming a P-type doped drift region by P-type impurity injection or forming an N-type doped drift region by N-type impurity injection, wherein the injection dosage is 1e12 atom/cm2～1e15 atom/cm2；
Step 3, activating the P-type impurities or the N-type impurities by high-temperature oxidation and knot pushing, wherein the temperature of a furnace tube is 850-1200 ℃, and the duration time is 30-300 min;
and step 4, obtaining an N well or a P well through impurity implantation and performing high-temperature junction pushing, wherein the implantation dosage is 1e12 atom/cm2～1e15 atom/cm2The push-to-knot temperature isThe knot pushing time is 10min to 300min at 850 ℃ to 1200 ℃;
step 5, forming a P-type doped buried layer and an N-type doped buried layer respectively by two times of high-energy impurity implantation with the implantation dosage of 1e12 atom/cm2～1e15 atom/cm2Then, carrying out high-temperature junction pushing to activate doped impurities and growing a field oxide layer;
step 6, growing a gate oxide layer with the thickness of 100A-1200A;
step 7, growing an N-type polycrystalline silicon layer as a grid G by low-pressure chemical vapor deposition after the gate oxide layer is grown;
step 8, forming an N + source drain region or an N well contact region by N-type impurity implantation with the implantation dose of 1e12 atom/cm2～5e15 atom/cm2Or forming P + source/drain regions or P-well contact regions by P-type impurity implantation with an implantation dose of 1e12 atom/cm2～5e15 atom/cm2。
Compared with the prior art, the invention has the beneficial effects that:
1. in the transverse semiconductor device provided by the invention, the strip-shaped second P-type doped region 3 is connected with the P-type substrate, the low potential is kept during voltage resistance, the peak value of an electric field is in the device body, the local surface electric field intensity of the device is reduced, and the voltage resistance of the device is improved. Meanwhile, the second P-type doped regions 3 are arranged into a plurality of strip-shaped structures, and the second P-type doped regions 3 and the N-type doped regions 2 are alternately arranged at the position of the buried layer, so that the N-type region 8 between two adjacent second P-type doped regions 3 can be doped higher than the N-type doped region 2, and the transverse semiconductor device has a wider current conduction path and stronger current conduction capability.
2. In the transverse semiconductor device provided by the invention, the doses of ionized impurities of the substrate of the device, the doses of the ionized impurities of the second conductive type doping region 2 in the surface voltage-withstanding region, the width of the strip-shaped first conductive type doping region 3 in the Z direction and the doses of the ionized impurities are reasonably adjusted, so that the doses of two conductive type depletion doses in voltage withstanding reach better balance, and the transverse device has smaller specific on-resistance and larger on-current density under the condition of not influencing the breakdown voltage of the transverse device.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor device according to the prior art;
fig. 2 is a schematic structural diagram of a lateral semiconductor device according to the present invention;
fig. 3 is a three-dimensional view of a lateral semiconductor device provided by the present invention;
fig. 4 is a top view of a lateral semiconductor device provided in the present invention;
fig. 5 is a schematic structural diagram of a surface voltage-withstanding region of a lateral semiconductor device along the Z-Y direction according to the present invention.
Detailed Description
The technical scheme of the invention is detailed below by combining the accompanying drawings and the embodiment.
As shown in fig. 2, a schematic structural diagram of an N-LDMOS device provided by the present invention includes a P-type substrate 1, N-type doped regions 2 located on the top and right sides of the P-type substrate 1, first P-type doped regions 4 located on the top and left sides of the P-type substrate, the N-type doped regions 2 adjacent to the first P-type doped regions 4, P-type heavily doped regions 5 and N-type heavily doped source regions 6 located in the first P-type doped regions 4, N-type heavily doped drain regions 7 located in the N-type doped regions 2, source electrodes S located on the P-type heavily doped regions 5 and N-type heavily doped source regions 6, a gate oxide and a gate electrode G located on the first P-type doped regions 4, and a drain electrode D located on the N-type heavily doped drain regions 7, wherein a plurality of strip-shaped second P-type doped regions 3 located on the same horizontal plane are disposed inside the N-type doped regions 2, and one side of the second P-type doped regions 3 is connected to the P-type substrate, the other side is located inside the N-type doped region 2. The N-type doped region 2, the N-type region 8 between the adjacent strip-shaped second P-type doped regions and the second P-type doped region 3 form a surface voltage-resisting region of the N-LDMOS device.
When the grid electrode of the LDMOS is turned off, the N-type region 8 between the N-type doped region 2 and the adjacent second P-type doped region 3, the P-type substrate 1 and the second P-type doped region 3 are mutually and completely depleted, so that the surface voltage-resistant region of the LDMOS has the maximum depletion layer width, the local surface electric field intensity of the LDMOS is reduced, and the overall breakdown voltage of the device is improved.
When the gate of the LDMOS is turned on, the second P-type doped regions 3 are mutually independent strips instead of being connected together, and the N-type region 8 sandwiched between two adjacent second P-type doped regions 3 can have higher doping than the N-type doped region 2, so that the LDMOS has a wider current conduction path and thus has stronger current conduction capability.
Examples
A method of manufacturing a lateral semiconductor device, comprising the steps of:
step 1, preparing a P-type substrate, wherein the resistivity of the substrate is 100 ohm cm;
step 2, forming an N-type doped region 2 by N-type impurity implantation with the implantation dosage of 4e12atom/cm2；
Step 3, activating N-type impurities by high-temperature oxidation and knot pushing, wherein the temperature of a furnace tube is 1000 ℃, and the duration time is 120 min;
step 4, obtaining a P trap through impurity implantation and carrying out high-temperature junction pushing, wherein the implantation dosage is 4e12atom/cm2The knot pushing temperature is 1200 ℃, and the knot pushing time is 30 min;
step 5, forming a P-type buried layer region 4 and an N-type buried layer region 8 through two times of high-energy implantation respectively, wherein the implantation doses are 4e12atom/cm respectively2And 2e12atom/cm2Then, carrying out high-temperature junction pushing to activate doped impurities and growing a field oxide layer;
step 6, growing a gate oxide layer with the thickness of 600A;
step 7, growing an N-type polycrystalline silicon layer as a grid G by low-pressure chemical vapor deposition after the gate oxide layer is grown;
and 8, forming an N + source drain region by N-type impurity implantation with the implantation dose of 1e15 atom/cm2Forming a P-well contact region by P-type impurity implantation with an implantation dose of 1e15 atom/cm2And after the impurity is activated, the lateral semiconductor device is obtained.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the technical solutions of the present invention, so long as the technical solutions can be realized on the basis of the above embodiments without creative efforts, which should be considered to fall within the protection scope of the patent of the present invention.

Claims (3)

1. A lateral semiconductor device comprises a first conductivity type semiconductor substrate (1), a second conductivity type doped region (2) located above the first conductivity type semiconductor substrate, the first conductivity type doped region (4) located above the first conductivity type semiconductor substrate, a first conductivity type heavily doped region (5) and a second conductivity type heavily doped source region (6) located within the first conductivity type doped region (4), a second conductivity type heavily doped drain region (7) located within the second conductivity type doped region (2), a source located above the first conductivity type heavily doped region (5) and the second conductivity type heavily doped source region (6), a gate oxide layer and a gate electrode located above the first conductivity type doped region (4), a drain located above the second conductivity type heavily doped drain region (7), the semiconductor device is characterized in that a plurality of strip-shaped first conductivity type doped regions (3) which are located on the same horizontal plane are arranged in the second conductivity type doped region (2), one side of each first conductivity type doped region (3) is connected with the first conductivity type semiconductor substrate (1), and the other side of each first conductivity type doped region is located in the second conductivity type doped region (2);
assuming that the dosage of ionized impurities exhausted by the single-side abrupt parallel plane junction made by the same substrate under the highest reverse voltage is D0The dose of the impurity with which the first conductivity type semiconductor substrate is depleted is D0The ionized impurity dose of the first conductive type doped region is 4D0For the second conductivity type doped region, the ionized impurity dose of the region between the first conductivity type semiconductor substrate and the first conductivity type doped region is 2D0The ionized impurity dose of the region between adjacent first conductivity type doped regions is 2D0The ionized impurity dose of the region between the upper surfaces of the first and second conductivity type doped regions is D0。
2. The lateral semiconductor device of claim 1, wherein a thickness of the plurality of stripe-shaped first conductivity type doped regions, a distance between adjacent stripe-shaped first conductivity type doped regions are adjusted according to a ratio of a doping impurity dose of the stripe-shaped first conductivity type doped regions to a doping impurity dose of the second conductivity type between the stripe-shaped first conductivity type doped regions.
3. A horizontal semiconductor device comprises a P-type substrate (1), an N-type doped region (2) positioned on the P-type substrate, a first P-type doped region (4) positioned on the P-type substrate, the N-type doped region (2) is adjacent to the first P-type doped region (4), a P-type heavily doped region (5) and an N-type heavily doped source region (6) positioned in the first P-type doped region (4), an N-type heavily doped drain region (7) positioned in the N-type doped region (2), sources positioned on the P-type heavily doped region (5) and the N-type heavily doped source region (6), a gate oxide layer and a gate positioned on the first P-type doped region (4), and a drain positioned on the N-type drain region (7), and is characterized in that a plurality of strip-shaped second P-type heavily doped regions (3) positioned on the same horizontal plane are arranged in the N-type doped region (2), one side of the second P-type doped region (3) is connected with the P-type substrate, and the other side of the second P-type doped region is positioned in the N-type doped region (2).
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