CN104882438A - Trap control-based semiconductor capacitor and preparation method and application thereof - Google Patents
Trap control-based semiconductor capacitor and preparation method and application thereof Download PDFInfo
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- CN104882438A CN104882438A CN201510271666.5A CN201510271666A CN104882438A CN 104882438 A CN104882438 A CN 104882438A CN 201510271666 A CN201510271666 A CN 201510271666A CN 104882438 A CN104882438 A CN 104882438A
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Abstract
The invention provides a trap control-based semiconductor capacitor and a preparation method and application thereof. The preparation method of the semiconductor capacitor comprises a step of selecting a highly doped N-type or P-type material, growing an oxide isolation layer on the surface of a substrate, determining a capacitor region, a drain region and a channel region by photoetching, removing an oxide isolation layer on the channel region by etching, forming a P-type substrate or an N-type substrate through an ion injection method or a diffusing method, and etching and oxidizing a part of the substrate to obtain an oxide layer; a step of growing oxide isolation layers on the capacitor region and the drain region; a step of removing oxide isolation layers on a control grid electrode layer and a control drain electrode layer by photoetching and etching; and a step of forming the control grid electrode layer, the control drain electrode layer and a substrate electrode layer respectively through a metal deposition technology. According to the invention, charging and discharging of the capacitor region can be effectively controlled, a basic semiconductor capacitor can be provided for a specific chip with requirements for extremely-low power consumption, and the good compatibility is achieved.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of semicoductor capacitor device based on trap control and preparation method thereof and application.
Background technology
Semiconductor silicon material, in device fabrication processes, creates defect or trap due to technological reason.Trap in these silicon introduces discrete energy level in the forbidden band of semiconductor silicon.This discrete energy level has the carrier transport characteristic of interference semiconductor device, is therefore generally regarded as the principal element bringing degeneration to device performance.
But in forbidden band, there is discrete energy levels just because of trap, therefore they can produce and complex centre as effective, regulate the concentration of two kinds of charge carriers in conduction band and valence band.And this special generation complex effect of trap has good controllability.Therefore, how to utilize this characteristic of trap significant.
Summary of the invention
Primary and foremost purpose of the present invention is to provide a kind of semicoductor capacitor device controlled based on trap, the charging and discharging of the capacitive region controlled for realizing utilizing the generation complex effect of trap.Extremely low charging and discharging currents can be realized control.
Another object of the present invention is the preparation method providing the above-mentioned semicoductor capacitor device based on trap control.
Another object of the present invention is the application process providing the above-mentioned semicoductor capacitor device based on trap control.
The present invention is achieved in that a kind of semicoductor capacitor device controlled based on trap, comprises capacitive region and drain region, is provided with the oxidation insulating layer of mounted on top and the channel region of substrate formation between described capacitive region and drain region; Described capacitive region top capping oxidation separator; Underlayer electrode layer is provided with bottom described channel region; Described oxidation insulating layer top Coverage Control gate electrode layer; Top, described drain region is provided with control drain electrode layer, and described control drain electrode layer periphery is provided with oxidization isolation layer.
Preferably, described substrate is P type substrate.
Preferably, described substrate is N-type substrate.
Invention further provides the preparation method of the above-mentioned semicoductor capacitor device based on trap control, the method comprises the following steps:
(1) highly doped N-type or P-type material is chosen, one deck oxidization isolation layer is grown at substrate surface, by photoetching determination capacitive region, drain region and channel region, etch away the oxidization isolation layer above channel region, P type substrate or N-type substrate is formed by ion implantation or diffusion method, and by a substrate etching part also oxidation formation oxide layer;
(2) in capacitive region and drain region, one deck oxidization isolation layer is grown;
(3) by photoetching and the oxidization isolation layer that etches away control gate electrode layer and control on drain electrode layer position;
(4) by metal deposition process, formation control gate electrode layer, control drain electrode layer and underlayer electrode layer respectively.
Invention further provides the application process of the above-mentioned semicoductor capacitor device based on trap control, the method comprises the following steps:
(1) as drain terminal voltage V
dwhen being greater than 0V, gate voltage is set up corresponding raceway groove spent condition, injects into capacitive region by the hole of generation, is capacitive region charging;
(2) as drain terminal voltage V
dwhen being less than 0V, gate voltage is set up corresponding raceway groove spent condition, and the hole of capacitive region is drawn in channel region and participates in compound, is capacitive region electric discharge.
Compared to the shortcoming and defect of prior art, the present invention has following beneficial effect: the present invention, can the discharge and recharge in very effective control capacitance district by based on the generation complex effect of trap.Compare and traditional capacitor element, this electric capacity minimum running current can be low to moderate skin peace rank, the present invention can be the basic semicoductor capacitor unit component that the special chip with extremely low power dissipation requirement provides.And the device architecture in the present invention, there is good compatibility with traditional CMOS technology.
Accompanying drawing explanation
Fig. 1 is the structural representation of the semicoductor capacitor device that electron conductive type raceway groove of the present invention controls based on trap;
Fig. 2 is the structural representation of the semicoductor capacitor device that hole conduction type raceway groove of the present invention controls based on trap;
In Fig. 3 embodiment of the present invention, N-semiconductor capacitor element is at V
dworking mechanism's principle under >0V situation can be with schematic diagram; Small circle with multiplication sign in figure represents trap level.
Fig. 4 be in the embodiment of the present invention N-semiconductor capacitor element at V
dworking mechanism's principle of <0V situation can be with schematic diagram; Small circle with multiplication sign in figure represents trap level.
N-semiconductor capacitor element charging and discharging currents I in Fig. 5 embodiment of the present invention
dschematic diagram.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Embodiment 1
As shown in Figure 1, the preparation of semicoductor capacitor device that electron conductive type raceway groove of the present invention controls based on trap comprises the following steps:
(1) highly doped n type material is chosen, high temperature oxidation furnace is used to grow one deck oxidization isolation layer at substrate surface under the high temperature of 1000 degrees Celsius is arranged, use mask aligner by photoetching determination capacitive region 12, drain region 13 and channel region 11, etch away the oxidization isolation layer above channel region, by ion implantor, the group iii elements atomic ions such as boron injected into channel region or use high temperature dispersing furnace boron to be diffused into formation P type substrate in channel region under the setting of 1000 degrees Celsius, substrate doping is controlled 10
15~ 10
17cm
-3in scope, and by a substrate etching part also oxidation formation oxide layer 14;
(2) in capacitive region 13 and drain region 12, grow one deck oxidization isolation layer 18,19,110 under using high temperature oxidation furnace to arrange at 1000 degrees Celsius, oxidated layer thickness is within the scope of 4 ~ 20nm.
(3) use mask aligner by the oxidization isolation layer in photoetching and ion etching machine engraving eating away control gate electrode layer and control drain electrode layer position;
(4) use physical chemistry vapor deposition apparatus by aluminium or copper metallic atom depositing technics, respectively formation control gate electrode layer 15, control drain electrode layer 16 and underlayer electrode layer 17.
Embodiment 2
As shown in Figure 2, the preparation of semicoductor capacitor device that hole conduction type raceway groove of the present invention controls based on trap comprises the following steps:
(1) highly doped n type material is chosen, high temperature oxidation furnace is used to grow one deck oxidization isolation layer at substrate surface under the high temperature of 1000 degrees Celsius is arranged, use mask aligner by photoetching determination capacitive region 22, drain region 23 and channel region 21, etch away the oxidization isolation layer above channel region, by ion implantor ion implantor, the group iii elements atomic ions such as phosphorus injected into channel region or use high temperature dispersing furnace boron to be diffused into formation N-type substrate in channel region under the setting of 1000 degrees Celsius, substrate doping is controlled 10
15~ 10
17cm
-3in scope, and by a substrate etching part also oxidation formation oxide layer 24;
(2) in capacitive region 22 and drain region 23, grow one deck oxidization isolation layer 28,29,210 under using high temperature oxidation furnace to arrange at 1000 degrees Celsius, oxidated layer thickness is within the scope of 4 ~ 20nm.
(3) use mask aligner by photoetching and use ion etching machine engraving eating away control gate electrode layer and the oxidization isolation layer controlled on drain electrode layer position;
(4) use physical chemistry vapor deposition apparatus that aluminium or copper metallic atom depositing technics are passed through metal deposition process, respectively formation control gate electrode layer 25, control drain electrode layer 26 and underlayer electrode layer 27.
Embodiment 3
Based on the application process of the semicoductor capacitor device that trap controls, the method comprises the following steps:
(1) as drain terminal voltage V
dwhen being greater than 0V, gate voltage is set up corresponding raceway groove spent condition, injects into capacitive region by the hole of generation, is capacitive region charging;
(2) as drain terminal voltage V
dwhen being less than 0V, gate voltage is set up corresponding raceway groove spent condition, and the hole of capacitive region is drawn in channel region and participates in compound, is capacitive region electric discharge.
Effect example
As shown in Figure 3, Fig. 3 is that N-semiconductor capacitor element is at V
dworking mechanism's principle under >0V situation can be with schematic diagram; Small circle with multiplication sign in figure represents trap level.In Fig. 3, in N-semiconductor capacitor element, when drain region does not apply bias voltage, capacitive region, channel region are identical with the quasi-Fermi level in drain region.(the V when drain electrode applies positive bias
d>0V), the entirety of being with in drain region moves down, and this makes the quasi-Fermi level E in therefore drain region
fNlower than the quasi-Fermi level of raceway groove and capacitive region, the flow direction drains by the electronics therefore produced due to trap in raceway groove, and hole then flows to the capacitive region of suspension.Namely the working mechanism of the N-semiconductor capacitor element described in being with of Fig. 3 is defined.
As shown in Figure 4, Fig. 4 is that N-semiconductor capacitor element is at V
dworking mechanism's principle of <0V situation can be with schematic diagram; Small circle with multiplication sign in figure represents trap level.In Fig. 4, in N-semiconductor capacitor element, when drain region does not apply bias voltage, capacitive region, channel region are identical with the quasi-Fermi level in drain region.(the V when drain electrode applies positive bias
d<0V), being with of drain region moves on the whole, and this makes the quasi-Fermi level E in therefore drain region
fNhigher than the quasi-Fermi level of raceway groove and capacitive region.Therefore in raceway groove due to need in trap recombination process electronics will from drain region, namely electronics flows to raceway groove from drain region.The hole needed in trap recombination process in raceway groove is then from the capacitive region suspended, and namely hole flows to raceway groove from capacitive region.Namely the working mechanism of the N-semiconductor capacitor element described in being with of Fig. 4 is defined.
As shown in Figure 5, Fig. 5 is N-semiconductor capacitor element charging and discharging currents I
dschematic diagram.In Fig. 5, for N-semiconductor capacitor element, based on the mechanism in Fig. 3 and Fig. 4, the drain terminal electric current I that the generation current that raceway groove trap causes is formed
dfor the drain terminal electric current I that the recombination current caused on the occasion of, raceway groove trap is formed
dfor negative value.Therefore for N-semiconductor capacitor element, in Fig. 5, as the drain voltage V that drain electrode applying one is positive
dvalue, now gate voltage arranges a positive V
gand V
gmake raceway groove be in as spent condition, now based on Fig. 3, drain generation current positive for outflow one.If as the drain voltage V that drain electrode applying one is negative
dvalue, now gate voltage arranges a negative V
gand V
gmake now raceway groove be in spent condition, now based on Fig. 3, drain recombination current negative for outflow one.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. based on the semicoductor capacitor device that trap controls, it is characterized in that, comprise capacitive region and drain region, between described capacitive region and drain region, be provided with the oxidation insulating layer of mounted on top and the channel region of substrate formation; Described capacitive region top capping oxidation separator; Underlayer electrode layer is provided with bottom described channel region; Described oxidation insulating layer top Coverage Control gate electrode layer; Top, described drain region is provided with control drain electrode layer, and described control drain electrode layer periphery is provided with oxidization isolation layer.
2., as claimed in claim 1 based on the semicoductor capacitor device that trap controls, it is characterized in that, described substrate is P type substrate.
3., as claimed in claim 1 based on the semicoductor capacitor device that trap controls, it is characterized in that, described substrate is N-type substrate.
4. the preparation method of the semicoductor capacitor device based on trap control described in any one of claims 1 to 3, it is characterized in that, the method comprises the following steps:
(1) highly doped N-type or P-type material is chosen, one deck oxidization isolation layer is grown at substrate surface, by photoetching determination capacitive region, drain region and channel region, etch away the oxidization isolation layer above channel region, P type substrate or N-type substrate is formed by ion implantation or diffusion method, and by a substrate etching part also oxidation formation oxide layer;
(2) in capacitive region and drain region, one deck oxidization isolation layer is grown;
(3) by photoetching and the oxidization isolation layer that etches away control gate electrode layer and control on drain electrode layer position;
(4) by metal deposition process, formation control gate electrode layer, control drain electrode layer and underlayer electrode layer respectively.
5. the application process of the semicoductor capacitor device based on trap control described in any one of claims 1 to 3, it is characterized in that, the method comprises the following steps:
(1) as drain terminal voltage V
dwhen being greater than 0V, gate voltage is set up corresponding raceway groove spent condition, injects into capacitive region by the hole of generation, is capacitive region charging;
(2) as drain terminal voltage V
dwhen being less than 0V, gate voltage is set up corresponding raceway groove spent condition, and the hole of capacitive region is drawn in channel region and participates in compound, is capacitive region electric discharge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510271666.5A CN104882438A (en) | 2015-05-25 | 2015-05-25 | Trap control-based semiconductor capacitor and preparation method and application thereof |
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|---|---|---|---|
| CN201510271666.5A CN104882438A (en) | 2015-05-25 | 2015-05-25 | Trap control-based semiconductor capacitor and preparation method and application thereof |
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| CN104882438A true CN104882438A (en) | 2015-09-02 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161484A (en) * | 2015-09-23 | 2015-12-16 | 西安邮电大学 | Semiconductor capacitor device based on trap characteristics, preparation method and applications thereof |
| CN111751698A (en) * | 2020-07-28 | 2020-10-09 | 哈尔滨工业大学 | Method for detecting fixed positive charge trap in oxide layer of electronic device |
-
2015
- 2015-05-25 CN CN201510271666.5A patent/CN104882438A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161484A (en) * | 2015-09-23 | 2015-12-16 | 西安邮电大学 | Semiconductor capacitor device based on trap characteristics, preparation method and applications thereof |
| CN111751698A (en) * | 2020-07-28 | 2020-10-09 | 哈尔滨工业大学 | Method for detecting fixed positive charge trap in oxide layer of electronic device |
| CN111751698B (en) * | 2020-07-28 | 2022-11-25 | 哈尔滨工业大学 | Method for detecting fixed positive charge trap in oxide layer of electronic device |
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Application publication date: 20150902 |