CN109659236B - Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof - Google Patents
Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000011084 recovery Methods 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- 239000010703 silicon Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 29
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 28
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 19
- -1 phosphorus ions Chemical class 0.000 claims description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims description 14
- 239000011574 phosphorus Substances 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 230000008020 evaporation Effects 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 18
- 238000002513 implantation Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 229910001385 heavy metal Inorganic materials 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a process method for reducing VDMOS recovery time and a VDMOS semiconductor device thereof, and relates to the technical field of semiconductor device manufacturing.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a process method for reducing VDMOS recovery time and a VDMOS semiconductor device thereof.
Background
The technological method for reducing the VDMOS recovery time in the technical field of semiconductor device manufacturing mainly comprises an electron irradiation technology, a heavy metal doping technology and the like, and heavy metal doping is a common measure. The technical measure of heavy metal doping is that a layer of metal is sputtered on the surface of a silicon wafer to serve as a doping source and enters the interior of a semiconductor to form a composite center, so that the service life of minority carriers in a silicon PN junction is shortened, the storage time is shortened, and the switching speed is increased. Because heavy metal impurity atoms have strong diffusion capacity in semiconductors, electrical parameters of VDMOS devices are poor, and in order to prevent platinum from escaping due to subsequent high-temperature working steps such as alloying and baking processes, furnace tubes, injection machines, spin coaters and other equipment from being polluted and causing cross contamination in the production process, a whole set of production equipment such as the injection machines, the horizontal diffusion furnaces, the photoetching machines, the spin coaters and the like must be purchased independently and used separately from conventional equipment, and the equipment including work clamps and the like cannot be used together, so that the manufacturing cost of the semiconductor devices is increased.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The first objective of the present invention is to provide a process method for reducing the recovery time of a VDMOS, which solves the technical problem of the conventional process method that the manufacturing cost of a semiconductor device is too high due to the escape of doped heavy metals.
The invention provides a process method for reducing VDMOS recovery time, which comprises the steps of sequentially carrying out thinning, back injection, high-temperature baking and metal sputtering treatment on a silicon wafer subjected to contact hole etching.
Further, in the thinning step, the silicon wafer after the etching of the contact hole is thinned, and the thickness of the thinned silicon wafer is 350-450 μm, preferably 400 μm.
Further, in the back side implantation step, ions are implanted into the thinned silicon wafer, wherein the implanted ions are selected from at least one of boron ions, phosphorus ions or arsenic ions, and preferably phosphorus ions.
Further, in the back side implantation step, the implantation dose of the phosphorus ions is 1.5 × 10 15 /cm 2 -2.5×10 15 /cm 2 Preferably 2X 10 15 /cm 2 。
Further, in the high-temperature baking step, the baking temperature is 850-.
Further, in the metal sputtering step, the metal used is platinum and/or gold, preferably platinum.
Further, the method also comprises a metal removing step arranged after the metal sputtering step;
preferably, in the metal removing step, the metal removing method is to place the silicon wafer in aqua regia at 60-80 ℃ for 20-30 min;
preferably, the metal removal method is to place the silicon wafer in aqua regia at 70 ℃ for 25 min.
Further, an annealing step is included after the metal removal step;
preferably, in the annealing step, the annealing temperature is 750-1000 ℃, preferably 900 ℃;
and/or the annealing time is 20-70min, preferably 30 min.
Further, the method also comprises an aluminum evaporation step arranged after the annealing step;
preferably, in the aluminum evaporation step, an aluminum layer is evaporated on the annealed silicon wafer, wherein the thickness of the aluminum layer is 2-4 μm, preferably 3 μm;
preferably, the method further comprises a photoetching step arranged after the aluminum evaporation step;
the exposure of the aluminum layer is preferably performed in a lithography step, wherein the exposure time is 200-300ms, preferably 260 ms.
The second purpose of the invention is to provide a VDMOS semiconductor device, which is prepared according to the process method for reducing the recovery time of the VDMOS.
Compared with the prior art, the invention has the beneficial effects that:
the process method for reducing the recovery time of the VDMOS semiconductor device not only saves equipment purchase cost and reduces the manufacturing cost of the semiconductor device, but also reduces the recovery time of the VDMOS, the zero gate voltage drain current, the resistivity of an epitaxial wafer and the thickness of the epitaxial layer, and simultaneously reduces the purchase cost of epitaxial materials, and has wide application prospect.
The VDMOS semiconductor device provided by the invention has the advantages of short recovery time, small zero gate voltage drain current, low cost and wide application prospect.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer.
According to the first aspect of the invention, the invention provides a process method for reducing the recovery time of a VDMOS (vertical double-diffused metal oxide semiconductor). according to the process method, thinning, back injection, high-temperature baking and metal sputtering treatment are sequentially carried out on a silicon wafer after a contact hole is etched.
The process method for reducing the recovery time of the VDMOS semiconductor device not only saves equipment purchase cost and reduces the manufacturing cost of the semiconductor device, but also reduces the recovery time of the VDMOS, the zero gate voltage drain current, the resistivity of an epitaxial wafer and the thickness of the epitaxial layer, and simultaneously reduces the purchase cost of epitaxial materials, and has wide application prospect.
In the present invention, the VDMOS is a vertical double-diffused metal-oxide semiconductor field effect transistor, which is a commonly used semiconductor device.
The contact hole etching refers to that a groove is formed in a lead hole by using an etching method, so that metal filling is facilitated; the thinning refers to reducing the thickness of the silicon wafer to the range provided by the invention, and the specifications of the grinding head are 320 meshes and 600 meshes; the back injection is ion doping by using an injection method, so that the aim of improving the contact resistance is fulfilled; the high-temperature baking refers to pushing back-doped ions into a semiconductor body in a high-temperature mode; metal sputtering refers to the formation of a metal layer on the surface of a silicon wafer by sputtering.
In the invention, after the step of the contact hole etching process is completed, the silicon wafer is firstly thinned to the required thickness, the processes of back injection, high-temperature baking and the like are carried out, then a metal doping source is formed on the surface of the silicon wafer by using a sputtering process, and metal enters silicon through a specific annealing process to form a composite center, so that the service life of minority carriers in a silicon PN junction is shortened, the storage time is shortened, and the switching speed is increased. The invention firstly uses the prior equipment to carry out the process steps of thinning, injecting, high-temperature baking and the like, and then carries out the metal doping process step, so the high-temperature process step does not exist after the metal doping process step, the doped heavy metal cannot escape, the pollution to an injector and a furnace tube and the cross contamination caused in other processes are avoided, and a whole set of production equipment such as an injector, a horizontal diffusion furnace, a photoetching machine, a spin coater and the like is not required to be purchased again, thereby the equipment purchase cost is saved, and the manufacturing cost of a semiconductor device is reduced.
In a preferred embodiment of the present invention, in the thinning step, the silicon wafer after the etching of the contact hole is thinned, and the thickness of the thinned silicon wafer is 350-450 μm.
Typical, but non-limiting, thicknesses of the thinned silicon wafer in the present invention are 350, 360, 370, 380, 390, 400, 410, 420, 430, 440, or 450 μm.
By controlling the thickness of the thinned silicon wafer, the VDMOS semiconductor device with more excellent performance can be prepared. The thickness of the thinned silicon wafer is in the range of 350-450 mu m, and the performance of the VDMOS semiconductor device is better.
In a further preferred embodiment of the invention, the thickness of the thinned silicon wafer is 400 μm.
The thickness of the thinned silicon wafer is further adjusted and optimized, so that the performance of the VDMOS semiconductor device is better.
In a preferred embodiment of the present invention, in the back-side implantation step, ions selected from at least one of boron, phosphorus, or arsenic ions, or other ions known to those skilled in the art to function similarly to the above-described function are implanted into the thinned silicon wafer.
In a further preferred embodiment of the present invention, in the back side implantation step, ions are implanted into the thinned silicon wafer, wherein the implanted ions are phosphorus ions.
In a preferred embodiment of the present invention, the implantation dose of phosphorus ions is 1.5 × 10 15 /cm 2 -2.5×10 15 /cm 2 。
In the present invention, a typical but non-limiting implantation dose of phosphorus ions is 1.5 × 10 15 /cm 2 、 1.6×10 15 /cm 2 、1.7×10 15 /cm 2 、1.8×10 15 /cm 2 、1.9×10 15 /cm 2 、2×10 15 /cm 2 、 2.1×10 15 /cm 2 、2.2×10 15 /cm 2 、2.3×10 15 /cm 2 、2.4×10 15 /cm 2 Or 2.5X 10 15 /cm 2 。
By controlling the mass ratio of the implantation dose of the phosphorus ions, a VDMOS semiconductor device with more excellent performance can be prepared. The implantation dosage of phosphorus ions is 1.5 × 10 15 /cm 2 -2.5×10 15 /cm 2 Within the range, the VDMOS semiconductor device has better performance.
In a further preferred embodiment of the present invention, the implantation dose of phosphorus ions is 2 × 10 15 /cm 2 。
The quality ratio of the implantation dosage of the phosphorus ions is further adjusted and optimized, so that the performance of the obtained VDMOS semiconductor device is better.
In a preferred embodiment of the present invention, in the high-temperature baking step, the baking temperature is 850-.
Typical but non-limiting temperatures for baking in the present invention are 850, 900, 950, 1000, 1050, 1100, 1150 or 1200 ℃.
By controlling the baking temperature, a VDMOS semiconductor device with more excellent performance can be prepared. The baking temperature is in the range of 850-1200 ℃, and the performance of the VDMOS semiconductor device is better.
In a preferred embodiment of the present invention, the metal used in the metal sputtering step is platinum and/or gold, or other metals known to those skilled in the art to function similarly to the above.
In a further preferred embodiment of the invention, the metal used is platinum.
In a preferred embodiment of the present invention, the method further comprises a metal removing step disposed after the metal sputtering step.
The metal removal means that the metal layer on the surface of the silicon wafer is removed in a corrosion mode.
In a preferred embodiment of the present invention, in the metal removing step, the metal is removed by placing the silicon wafer in aqua regia at 60-80 ℃ for 20-30 min.
Typical but non-limiting temperatures for metal removal in the present invention are 60, 65, 70, 75 or 80 ℃; typical but non-limiting times for metal removal are 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 or 30 min.
By controlling the temperature and time for removing the metal, a VDMOS semiconductor device with more excellent performance can be prepared. The temperature for removing the metal is within the range of 60-80 ℃ and the time for removing the metal is within the range of 20-30min, so that the VDMOS semiconductor device has better performance.
In a further preferred embodiment of the invention, the metal removal is carried out by placing the silicon wafer in aqua regia at 70 ℃ for 25 min.
The performance of the obtained VDMOS semiconductor device is better by further adjusting and optimizing the temperature and time for removing the metal.
In a preferred embodiment of the present invention, an annealing step is further included after the metal removal step.
Annealing refers to pushing metal ions remaining on the surface of the silicon wafer into the bulk of the semiconductor.
In a preferred embodiment of the present invention, the annealing temperature in the annealing step is 750-1000 ℃.
Typical but non-limiting temperatures for annealing in the present invention are 750, 760, 770, 780, 790, 800, 810, 820, 830, 840, 850, 860, 870, 880, 890, 900, 910, 920, 930, 940, 950, 960, 970, 980, 990 or 1000 ℃.
By controlling the annealing temperature, a VDMOS semiconductor device with more excellent performance can be prepared. The annealing temperature is within the range of 750-1000 ℃, and the performance of the VDMOS semiconductor device is better.
In a further preferred embodiment of the invention, the temperature of the annealing is 900 ℃.
The performance of the obtained VDMOS semiconductor device is better through further adjusting and optimizing the annealing temperature.
In a preferred embodiment of the invention, the annealing time is 20-70 min.
Typical but non-limiting times for annealing in the present invention are 20, 25, 30, 35, 40, 45, 50, 55, 60, 65 or 70 min.
By controlling the annealing time, a VDMOS semiconductor device with more excellent performance can be prepared. The annealing time is within the range of 20-70min, and the VDMOS semiconductor device has good performance.
In a further preferred embodiment of the invention, the annealing time is 30 min.
The performance of the obtained VDMOS semiconductor device is better through further adjusting and optimizing the annealing time.
In a preferred embodiment of the present invention, the method further includes an aluminum evaporation step provided after the annealing step.
Aluminum evaporation belongs to a physical vapor deposition method, and refers to a method for forming an aluminum metal layer by gasifying a plating material (aluminum) into atoms and molecules or ionizing the atoms and the molecules into ions under a vacuum condition and directly depositing the atoms and the molecules on the surface of a substrate.
In a further preferred embodiment of the present invention, in the aluminum evaporation step, an aluminum layer is evaporated on the annealed silicon wafer, wherein the aluminum layer has a thickness of 2 to 4 μm.
Typical but non-limiting thicknesses of the aluminum layer in the present invention are 2, 2.5, 3, 3.5 or 4 μm.
By controlling the thickness of the aluminum layer, the VDMOS semiconductor device with more excellent performance can be prepared. The thickness of the aluminum layer is within the range of 2-4 mu m, and the VDMOS semiconductor device has good performance.
In a further preferred embodiment of the invention the aluminium layer has a thickness of 3 μm.
The performance of the obtained VDMOS semiconductor device is better through further adjusting and optimizing the thickness of the aluminum layer.
In a preferred embodiment of the present invention, the method further includes a photolithography step provided after the aluminum evaporation step.
Metal lithography is a process of removing a specific portion of a thin film on a metal surface through a series of production steps. After that, the metal surface will leave a film with a micro-patterned structure. In the invention, a design circuit is formed on the surface of the metal layer according to the photoetching design structure, and finally the VDMOS semiconductor device is obtained.
In a preferred embodiment of the present invention, the aluminum layer is exposed in the metal photolithography step, wherein the exposure time is 200-300 ms.
Typical but non-limiting times for exposure in the present invention are 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 or 300 ms.
By controlling the exposure time, a VDMOS semiconductor device with more excellent performance can be prepared. The exposure time is within the range of 200-300ms, and the performance of the VDMOS semiconductor device is better.
In a further preferred embodiment of the invention, the exposure time is 260 ms.
The performance of the obtained VDMOS semiconductor device is better by further adjusting and optimizing the exposure time.
According to a second aspect of the invention, the invention provides a VDMOS semiconductor device, which is prepared according to the process method for reducing the recovery time of the VDMOS.
The VDMOS semiconductor device provided by the invention has the advantages of short recovery time, small zero gate voltage drain current, low cost and wide application prospect.
For further understanding of the present invention, the effects of the present invention will be described in further detail with reference to specific examples and comparative examples. All the raw materials related to the invention can be obtained commercially.
Example 1
The embodiment provides a VDMOS semiconductor device, and a preparation method thereof comprises the following steps:
(a) after finishing the process steps from wafer feeding to contact hole etching, the thickness of the silicon wafer is reduced to 400 mu m, and the back side injection dosage is 1.5 multiplied by 10 15 /cm 2 The phosphorus ions are baked at a high temperature of 1000 ℃, and the three main process steps are finished by using on-line conventional equipment.
(b) A platinum doping source is formed on the surface of a silicon wafer by using a sputtering process, then the silicon wafer is placed in aqua regia at 70 ℃ for 25min, and then annealing is carried out at 900 ℃ for 50 min, so that platinum enters silicon to form a composite center, and the service life of minority carriers in a silicon PN junction is shortened.
(c) And forming an aluminum layer with the thickness of 3 mu m on the surface of the silicon wafer through an aluminum evaporation process, and forming a designed circuit on the surface of the aluminum layer through metal photoetching, wherein the exposure time is 260ms, thus obtaining the VDMOS semiconductor device.
Example 2
The embodiment provides a VDMOS semiconductor device, and the manufacturing method of the embodiment is different from that of the embodiment 1 in that the thickness of a thinned silicon wafer is 350 μm.
Example 3
The embodiment provides a VDMOS semiconductor device, and the manufacturing method of the embodiment is different from that of embodiment 1 in that the thickness of a thinned silicon wafer is 450 μm.
Example 4
This example provides a VDMOS semiconductor device, and the manufacturing method of this example is different from that of example 1 in that the annealing temperature is 750 ℃.
Example 5
This example provides a VDMOS semiconductor device, and the manufacturing method of this example is different from that of example 1 in that the annealing temperature is 1000 ℃.
Example 6
The present example provides a VDMOS semiconductor device, and the manufacturing method of the present example is different from that of example 1 in that the annealing time is 20 min.
Example 7
The present example provides a VDMOS semiconductor device, and the manufacturing method of the present example is different from that of example 1 in that the annealing time is 70 min.
Comparative example 1
The comparative example provides a VDMOS semiconductor device, and the preparation method of the comparative example includes the steps of:
(a) after finishing the steps from the wafer feeding to the contact hole etching process, the thickness of the silicon wafer is reduced to 400 mu m, a platinum doping source is formed on the surface of the silicon wafer by using a sputtering process, then the silicon wafer is placed in aqua regia at 70 ℃ for 25min, and then the silicon wafer is annealed at 900 ℃ for 50 min.
(b) The back side implantation dose is 1.5 × 10 15 /cm 2 The phosphorus ions are baked at a high temperature of 1000 ℃.
(c) And forming an aluminum layer with the thickness of 3 mu m on the surface of the silicon wafer through an aluminum evaporation process, and forming a designed circuit on the surface of the aluminum layer through metal photoetching, wherein the exposure time is 260ms, thus obtaining the VDMOS semiconductor device.
Test example 1
Experiments were conducted to compare and study two performances, i.e., recovery time and zero gate voltage drain current, of the VDMOS semiconductor devices provided in examples 1 to 7 and comparative example 1.
The experimental data and results are as follows.
Table 1 performance data of different VDMOS semiconductor devices
| Recovery time (ns) | Zero gate voltage drain current (nA) | |
| Example 1 | 60 | 20 |
| Example 2 | 75 | 25 |
| Example 3 | 80 | 30 |
| Example 4 | 110 | 50 |
| Example 5 | 55 | 70 |
| Example 6 | 100 | 45 |
| Example 7 | 90 | 35 |
| Comparative example 1 | 300 | 370 |
As a result of analyzing the data, the recovery time of the VDMOS semiconductor devices provided in examples 1 to 7 is 60, 75, 80, 110, 55, 100, or 90ns, respectively, and the zero gate voltage drain current is 20, 25, 30, 50, 70, 45, or 35nA, respectively, which are superior to the recovery time (300ns) and the zero gate voltage drain current (370nA) of the VDMOS semiconductor device provided in comparative example 1, indicating that the VDMOS semiconductor device provided in the present invention has excellent performance and a wide application prospect.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (2)
1. A process method for reducing the recovery time of a VDMOS (vertical double-diffused metal oxide semiconductor), is characterized by comprising the following steps of:
(a) after finishing the process steps from wafer feeding to contact hole etching, the thickness of the silicon wafer is reduced to 400 mu m, and the back side injection dosage is 1.5 multiplied by 10 15 /cm 2 The phosphorus ions are baked at a high temperature of 1000 ℃;
(b) forming a platinum doping source on the surface of a silicon wafer by using a sputtering process, then placing the silicon wafer in aqua regia at 70 ℃ for 25min, and then annealing at 900 ℃ for 50 min to enable platinum metal to enter silicon to form a composite center;
(c) and forming an aluminum layer with the thickness of 3 mu m on the surface of the silicon wafer through an aluminum evaporation process, and forming a designed circuit on the surface of the aluminum layer through metal photoetching, wherein the exposure time is 260ms, so that the VDMOS semiconductor device is obtained.
2. A VDMOS semiconductor device, characterized in that, it is prepared by the process method for reducing the recovery time of VDMOS as claimed in claim 1.
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Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1471146A (en) * | 2003-06-18 | 2004-01-28 | 北京工业大学 | Method for manufacturnig silicon high-speed semiconductor switch device |
| CN101399227A (en) * | 2007-09-26 | 2009-04-01 | 中国科学院微电子研究所 | Method for making fully self-aligning bar gate power vertical bilateral diffusion field-effect tranisistor |
| CN101404292A (en) * | 2008-09-27 | 2009-04-08 | 电子科技大学 | VDMOS device |
| CN102157363A (en) * | 2011-03-08 | 2011-08-17 | 电子科技大学 | Ion implantation method of substrate back of power device |
| CN102184958A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Vertical double-diffusion MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| WO2012033437A1 (en) * | 2010-09-09 | 2012-03-15 | Учреждение Российской Академии Наук Ордена Трудового Красного Знамени Институт Нефтехимического Синтеза Им. А.В. Топчиева Ран (Инхс Ран) | Catalyst, method for producing same (embodiments) and method for the liquid-phase alkylation of isobutane with c2-c4 olefins in the presence of said catalyst |
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN102693981A (en) * | 2012-06-25 | 2012-09-26 | 吉林华微电子股份有限公司 | High-voltage VDMOS (Vertically Diffused Metal Oxide Semiconductor) tube taking LDMOS (Laterally Diffused Metal Oxide Semiconductor) as terminal |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| CN103515227A (en) * | 2012-06-14 | 2014-01-15 | 英飞凌科技奥地利有限公司 | Method of manufacturing a semiconductor device and a semiconductor device |
| CN103618006A (en) * | 2013-10-30 | 2014-03-05 | 国家电网公司 | A fast recovery diode and a manufacturing method thereof |
| CN104157569A (en) * | 2014-08-26 | 2014-11-19 | 清华大学 | Technology for manufacturing fast recovery diode |
| CN104282759A (en) * | 2013-07-10 | 2015-01-14 | 富士电机株式会社 | Super junction MOSFET, method of manufacturing the same, and complex semiconductor device |
| CN105140112A (en) * | 2015-06-24 | 2015-12-09 | 西安理工大学 | Power diode and preparation method thereof |
| WO2017146148A1 (en) * | 2016-02-23 | 2017-08-31 | 富士電機株式会社 | Semiconductor device |
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN108109922A (en) * | 2017-12-19 | 2018-06-01 | 武汉新芯集成电路制造有限公司 | A kind of method for reducing metal-oxide-semiconductor stress effect |
| CN108550529A (en) * | 2018-04-28 | 2018-09-18 | 江阴新顺微电子有限公司 | A kind of manufacturing method of high pressure VDMOS device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3177973B2 (en) * | 1999-01-28 | 2001-06-18 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP4942134B2 (en) * | 2005-05-20 | 2012-05-30 | 日産自動車株式会社 | Method for manufacturing silicon carbide semiconductor device |
| CN100477270C (en) * | 2007-02-14 | 2009-04-08 | 上海富华微电子有限公司 | VDMOS and IGBT power unit using the PSG doping technology and making process thereof |
| CN101383287B (en) * | 2008-09-27 | 2010-12-08 | 电子科技大学 | Manufacturing method for vertical DMOS device |
| JP5404812B2 (en) * | 2009-12-04 | 2014-02-05 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US8216923B2 (en) * | 2010-10-01 | 2012-07-10 | Varian Semiconductor Equipment Associates, Inc. | Integrated shadow mask/carrier for patterned ion implantation |
| CN102931081B (en) * | 2011-08-12 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for semiconductor device with field barrier layer |
| TWI451498B (en) * | 2011-12-28 | 2014-09-01 | Pfc Device Corp | Mos pn junction diode with enhanced response speed and associated manufacturing method |
| CN104051524B (en) * | 2013-03-15 | 2017-12-05 | 英飞凌科技奥地利有限公司 | Semiconductor devices |
| CN104681438B (en) * | 2013-11-27 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of semiconductor devices |
| CN104393029A (en) * | 2014-11-03 | 2015-03-04 | 吉林华微电子股份有限公司 | Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof |
| CN106128938B (en) * | 2016-08-01 | 2018-10-19 | 中国电子科技集团公司第四十六研究所 | A kind of VDMOS device method that thick-layer extension is prepared on thin Sb substrates |
| US10032766B2 (en) * | 2016-09-16 | 2018-07-24 | Globalfoundries Singapore Pte. Ltd. | VDMOS transistors, BCD devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices |
| CN107275407B (en) * | 2017-06-09 | 2020-03-17 | 电子科技大学 | Silicon carbide VDMOS device and manufacturing method thereof |
-
2018
- 2018-12-17 CN CN201811545641.XA patent/CN109659236B/en active Active
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1471146A (en) * | 2003-06-18 | 2004-01-28 | 北京工业大学 | Method for manufacturnig silicon high-speed semiconductor switch device |
| CN101399227A (en) * | 2007-09-26 | 2009-04-01 | 中国科学院微电子研究所 | Method for making fully self-aligning bar gate power vertical bilateral diffusion field-effect tranisistor |
| CN101404292A (en) * | 2008-09-27 | 2009-04-08 | 电子科技大学 | VDMOS device |
| WO2012033437A1 (en) * | 2010-09-09 | 2012-03-15 | Учреждение Российской Академии Наук Ордена Трудового Красного Знамени Институт Нефтехимического Синтеза Им. А.В. Топчиева Ран (Инхс Ран) | Catalyst, method for producing same (embodiments) and method for the liquid-phase alkylation of isobutane with c2-c4 olefins in the presence of said catalyst |
| CN102157363A (en) * | 2011-03-08 | 2011-08-17 | 电子科技大学 | Ion implantation method of substrate back of power device |
| CN102184958A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Vertical double-diffusion MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN103515227A (en) * | 2012-06-14 | 2014-01-15 | 英飞凌科技奥地利有限公司 | Method of manufacturing a semiconductor device and a semiconductor device |
| CN102693981A (en) * | 2012-06-25 | 2012-09-26 | 吉林华微电子股份有限公司 | High-voltage VDMOS (Vertically Diffused Metal Oxide Semiconductor) tube taking LDMOS (Laterally Diffused Metal Oxide Semiconductor) as terminal |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| CN104282759A (en) * | 2013-07-10 | 2015-01-14 | 富士电机株式会社 | Super junction MOSFET, method of manufacturing the same, and complex semiconductor device |
| CN103618006A (en) * | 2013-10-30 | 2014-03-05 | 国家电网公司 | A fast recovery diode and a manufacturing method thereof |
| CN104157569A (en) * | 2014-08-26 | 2014-11-19 | 清华大学 | Technology for manufacturing fast recovery diode |
| CN105140112A (en) * | 2015-06-24 | 2015-12-09 | 西安理工大学 | Power diode and preparation method thereof |
| WO2017146148A1 (en) * | 2016-02-23 | 2017-08-31 | 富士電機株式会社 | Semiconductor device |
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN108109922A (en) * | 2017-12-19 | 2018-06-01 | 武汉新芯集成电路制造有限公司 | A kind of method for reducing metal-oxide-semiconductor stress effect |
| CN108550529A (en) * | 2018-04-28 | 2018-09-18 | 江阴新顺微电子有限公司 | A kind of manufacturing method of high pressure VDMOS device |
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